阅读说明：本技术 用于hemt器件的侧壁钝化 (Sidewall passivation for HEMT devices ) 是由 邱汉钦 陈祈铭 蔡正原 姚福伟 于 2015-04-29 设计创作，主要内容包括：本发明的一些实施例涉及包括布置在半导体衬底上方的异质结结构的高电子迁移率晶体管(HEMT)。异质结结构包括用作e-HEMT的沟道区的由第一III-氮化物材料制成的二元III/V半导体层以及用作阻挡层的布置在二元III/V半导体层上方并且由第二III-氮化物材料制成的三元III/V半导体层。源极区和漏极区布置在三元III/V半导体层上方并且彼此横向间隔开。栅极结构布置在异质结结构上方并且布置在源极区和漏极区之间。栅极结构由第三III-氮化物材料制成。第一钝化层设置在栅极结构的侧壁周围并且由第四III-氮化物材料制成。本发明的实施例还涉及用于HEMT器件的侧壁钝化。(Some embodiments of the invention relate to a High Electron Mobility Transistor (HEMT) including a heterojunction structure disposed above a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material that serves as a channel region of the e-HEMT and a ternary III/V semiconductor layer disposed over the binary III/V semiconductor layer and made of a second III-nitride material that serves as a barrier layer. The source and drain regions are disposed over the ternary III/V semiconductor layer and are laterally spaced apart from each other. A gate structure is disposed over the heterojunction structure and between the source region and the drain region. The gate structure is made of a third III-nitride material. The first passivation layer is disposed around sidewalls of the gate structure and is made of a fourth ill-nitride material. Embodiments of the invention also relate to sidewall passivation for HEMT devices.)

1. A High Electron Mobility Transistor (HEMT), comprising:

a heterojunction structure disposed on a semiconductor substrate, the heterojunction structure comprising: a channel layer comprising a first Ill-nitride material, and a barrier layer comprising a second Ill-nitride material;

a source region and a drain region in direct contact with an upper surface of the heterojunction structure and laterally spaced from each other;

a gate structure disposed over the heterojunction structure and between the source region and the drain region, wherein the gate structure comprises a third ill-nitride material in direct contact with the upper surface of the heterojunction structure;

a first passivation layer conformally disposed around sidewalls and over an upper surface of the gate structure and comprising a fourth ill-nitride material; and

a second passivation layer conformally disposed over the first passivation layer;

wherein the first passivation layer has a first thickness and the second passivation layer has a second thickness greater than the first thickness;

a capping layer conformally disposed on the second passivation layer;

a metal gate electrode including an edge overlying an upper surface of the capping layer and including inner sidewalls extending down sidewalls of the opening through the capping layer, the second passivation layer and the first passivation layer, a bottom surface of the metal gate electrode being lower than a top surface of the gate structure to extend into the gate structure to be electrically connected with the gate structure.

2. The hemt of claim 1, wherein the fourth ill-nitride material of the first passivation layer is a binary III/V semiconductor material and has a different binary semiconductor composition than the first and second ill-nitride materials.

3. The high electron mobility transistor of claim 1, further comprising:

one or more buffer layers below the channel layer, wherein an uppermost buffer layer is made of the second III-nitride material and a lower buffer layer below the uppermost buffer layer is made of the fourth III-nitride material.

4. The hemt of claim 3, wherein the first passivation layer is made of the same material as the lower buffer layer.

5. The high electron mobility transistor of claim 1, wherein:

the first III-nitride material includes GaN;

the second III-nitride material includes Al_xGa_1-xAnd N is added. And

the fourth ill-nitride material includes AlN or BN.

6. The hemt of claim 1, wherein the source and drain regions extend through the first and second passivation layers and terminate on the barrier layer.

7. A method of forming a High Electron Mobility Transistor (HEMT), comprising:

forming a heterojunction structure on a semiconductor substrate;

forming a gate structure on the heterojunction structure;

forming a first passivation layer conformally disposed around sidewalls of the gate structure and extending over an upper surface of the gate structure;

forming a second passivation layer conformally overlying the first passivation layer, wherein the second passivation layer has a material composition different from a material composition of the first passivation layer;

etching source/drain openings through the first and second passivation layers on opposite sides of the gate structure; and

filling the source/drain openings with a conductive material to form source and drain conductors on the opposite sides of the gate structure.

8. A method of forming a High Electron Mobility Transistor (HEMT), comprising:

forming an AlN buffer layer over the substrate;

forming an AlGaN buffer layer above the AlN buffer layer;

forming a GaN channel layer over the AlGaN buffer layer;

forming an AlGaN barrier layer above the GaN channel layer;

forming a GaN gate structure in direct contact with an upper surface of the AlGaN barrier layer, wherein the GaN gate structure is doped with acceptor or donor impurities and has a gate structure upper surface and a gate structure outer sidewall;

forming an AlN or BN conformal passivation layer which is in direct contact with the AlGaN barrier layer, extends on the upper surface of the GaN gate structure and is adjacent to the outer side wall of the GaN gate structure;

conformally forming a second passivation layer on the AlN or BN conformal passivation layer, wherein the material composition of the second passivation layer is different from the material composition of the AlN or BN conformal passivation layer.

Forming source/drain openings through the AlN or BN conformal passivation layer and the second passivation layer; and

forming conductive source and drain regions in the source/drain openings to directly contact an upper surface of the AlGaN barrier layer.

9. The method of forming a High Electron Mobility Transistor (HEMT) according to claim 8, further comprising:

forming a capping layer conformally disposed on an upper surface of the second passivation layer, wherein the capping layer is conformally disposed along outer sidewalls of the second passivation layer and on the upper surface of the second passivation layer;

forming an opening in the capping layer between the source/drain openings and forming a metal gate electrode including an edge overlying an upper surface of the capping layer and including inner sidewalls extending down sidewalls of the opening through the capping layer, the second passivation layer, and the AlN or BN conformal passivation layer, the metal gate electrode being electrically connected with the gate structure.

10. The method of forming a High Electron Mobility Transistor (HEMT) of claim 8, wherein the source and drain regions extend through the AlN or BN conformal passivation layer and the second passivation layer, the source and drain regions having a lower portion that overlaps the GaN gate structure in lateral projection, the AlN or BN conformal passivation layer and the second passivation layer simultaneously abutting sidewalls of the lower portion.

Technical Field

Embodiments of the invention relate to integrated circuit devices and, more particularly, to sidewall passivation for HEMT devices.

Background

High Electron Mobility Transistors (HEMTs), also known as heterostructure fets (hfets) or modulation doped fets (modfets), are one type of field effect transistors. Whereas a conventional n-type MOSFET includes a gate electrode disposed over a p-type doped channel region separating n-type source/drain regions, for example, HEMT devices use a heterojunction as the channel rather than a doped region as the channel. The heterojunction is defined by an interface where two materials having different band gaps are in contact with each other. III-N (trinitride) devices are one type of HEMT In which the heterojunction is composed of group III materials (e.g., Al, Ga, In) and nitride (N) materials. These III-N devices show very promising performance in high power and high frequency applications. For example, III-N devices may be used in high power-high frequency applications such as transmitters for cell phone base stations, Direct Broadcast Satellite (DBS) receivers, electronic countermeasure systems, and the like.

Disclosure of Invention

An embodiment of the present invention provides a High Electron Mobility Transistor (HEMT), including: a heterojunction structure disposed over a semiconductor substrate, the heterojunction structure comprising: a binary III/V semiconductor layer made of a first III-nitride material serving as a channel region of the HEMT and a ternary III/V semiconductor layer arranged above the binary III/V semiconductor layer and made of a second III-nitride material serving as a barrier layer; source and drain regions disposed above the ternary III/V semiconductor layer and laterally spaced apart from each other; a gate structure disposed over the heterojunction structure and between the source region and the drain region, wherein the gate structure is made of a third ill-nitride material; and a first passivation layer disposed around sidewalls of the gate structure and made of a fourth III-nitride material.

According to another embodiment of the present invention, there is provided a method of forming an enhancement-mode, high electron mobility transistor (e-HEMT) on a substrate, comprising: forming a binary III-nitride channel layer over the substrate; forming a ternary III-nitride barrier layer over the binary III-nitride channel layer, wherein the ternary III-nitride barrier layer is in contact with the binary III-nitride channel layer at a heterojunction interface; forming a binary III-nitride gate layer over the ternary III-nitride barrier layer and doping the binary III-nitride gate layer with donor or acceptor impurities; removing selected portions of the doped binary III-nitride gate layer to form a patterned doped binary III-nitride gate structure having a gate upper surface and gate outer sidewalls and leaving exposed upper surface regions of the ternary III-nitride barrier layer; and forming a first conformal passivation layer over the upper surface of the gate, the outer sidewall of the gate, and the exposed upper surface region of the ternary III-nitride barrier layer.

According to still another embodiment of the present invention, there is provided an enhancement-mode High Electron Mobility Transistor (HEMT) formed on a substrate, including: an AlN buffer layer located above the substrate; an AlGaN buffer layer located above the AlN buffer layer; a GaN channel layer located over the AlGaN buffer layer; an AlGaN barrier layer located above the GaN channel layer; a GaN gate structure located over the AlGaN barrier layer, wherein the GaN gate structure is doped with acceptor or donor impurities and has a gate structure upper surface and a gate structure outer sidewall; and an AlN or BN conformal passivation layer located above the upper surface of the gate structure and abutting the outer side wall of the gate structure.

Drawings

Aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

Fig. 1 illustrates some embodiments of cross-sectional views of HEMT devices according to some embodiments of the present invention.

Fig. 2 illustrates a flow diagram of a method of fabricating an e-HEMT device according to some embodiments of the present invention.

Fig. 3-11 illustrate a series of cross-sectional views that collectively illustrate a method of fabricating a HEMT device, according to some embodiments of the present invention.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

HEMT devices use a heterojunction between two materials with different band gaps as a channel. For example, in some III-NHEMT devices, a wide bandgap AlGaN layer may form a heterojunction with a narrow bandgap GaN layer. The lattice constants of these two materials are usually slightly different. The difference in lattice structure of these types of materials creates strain that can lead to piezoelectrically induced polarization and band bending at the heterojunction interface. For example, GaN HEMTs typically have a strong surface polarization that causes them to operate in a normally-on (depletion mode) state. To overcome surface polarization and control the flow of charge carriers in enhancement mode devices, a gate of p-GaN material with a high work function can be formed directly on top of the AlGaN layer.

However, GaN HEMTs with AlGaN/GaN as schottky barrier and p-GaN gate as control gate result in large gate leakage. Furthermore, many III-N surfaces are subject to process-induced traps or damage in order to form enhancement mode device structures. These traps or damage mainly result in gate leakage or device leakage currents that degrade device performance. In an attempt to limit the number of traps (and thereby improve device performance), the present invention sets forth techniques for forming a passivation layer on III-N surfaces (e.g., sidewalls of p-GaN). The passivation layer terminates and passivates dangling bonds on the surface of the gate sidewall surface to limit the number of interface traps and thereby help improve device performance. Thus, gate leakage can be reduced by introducing such a passivation layer.

Fig. 1 shows some embodiments of cross-sectional views of HEMT devices 100 according to the present invention. The HEMT device 100 includes a heterojunction structure 102 disposed over a semiconductor substrate 104. The heterojunction structure 102 is comprised of a binary III/V semiconductor layer 106 and a ternary III/V semiconductor layer 108 disposed over the binary III/V semiconductor layer 106. The binary III/V semiconductor layer 106 is made of a first III-nitride material and serves as a channel region of the e-HEMT. The ternary III/V semiconductor layer 108 is made of a second III-nitride layer and serves as a barrier layer somewhat similar to the gate dielectric used for conventional MOSFETs. In some embodiments, the binary III/V semiconductor layer 106 is made of gallium nitride (GaN) and the ternary III/V semiconductor layer 108 is made of aluminum gallium nitride (Al)_xGa_1-xN, wherein, 0<x<1) And (4) preparing.

One or more buffer layers 110 may be disposed between the heterostructure 102 and the substrate 104. These buffer layers 110 may help to gradually distribute the strain over their thickness, where the strain is caused by the lattice mismatch between the substrate 104 and the binary III/V layer 106. By distributing strain, these buffer layers 110 may help in some aspects avoid the formation of traps. The illustrated buffer layer 110 includes an uppermost buffer layer 112 adjacent to the binary III/V layer 106 and a lower buffer layer 114 between the uppermost buffer layer 112 and the substrate 104. In some embodiments, the uppermost buffer layer 112 may be made of AlGaN, and the lower buffer layer 114 may be made of AlN. In other embodiments, more than two buffer layers may be included between the heterostructure 102 and the substrate 104.

Conductive source and drain regions 116 and 118 are disposed above the ternary III/V semiconductor layer 108 and are laterally spaced apart from each other. Conductive source and drain regions 116 and 118 have respective lower regions that adjoin the ternary III/V semiconductor layer 108 and are ohmically connected to the ternary III/V semiconductor layer 108. In some embodiments, source/ drain regions 116, 118 are located directly on ternary III/V semiconductor layer 108 and abut ternary III/V semiconductor layer 108 and are spaced apart from binary III/V semiconductor layer 106. However, in other embodiments, source/ drain regions 116, 118 extend through ternary III/V semiconductor layer 108 and abut binary III/V semiconductor layer 106.

A gate structure 120 is disposed over the heterojunction structure 102 and laterally between the conductive source and drain regions 116 and 118. The gate structure 120 is made of a third III-nitride material. For example, in some embodiments, the gate structure 120 may be made of GaN that has been doped with a donor impurity to form an n-type gate structure or an acceptor impurity to form a p-type gate structure. These dopants help to cause the resulting HEMT device 100 to operate in an enhancement mode as opposed to a depletion mode.

A first conformal passivation layer 122 is disposed around the gate structure sidewalls 120A, 120B and over the gate structure upper surface 120C. A first conformal passivation layer 122 is also disposed over the upper surface 108A of the ternary III/V semiconductor layer 108. In some embodiments, the first conformal passivation layer 122, which may be made of aluminum nitride (AlN) or Boron Nitride (BN), may be a high quality thin film to prevent current leakage from the gate structure 120. Thus, in some embodiments, the first conformal passivation layer 122 is grown by an Atomic Layer Deposition (ALD) technique, which, while time consuming, produces a very high quality film. In some embodiments, the first conformal passivation layer 122 may have a thickness between about 5 angstroms and about 500 angstroms. In addition to providing high quality films, ALD techniques are advantageous because they can be implemented at relatively low temperatures, e.g., between 200 ℃ and 500 ℃, which helps limit thermal budget issues, and because ALD techniques provide good step coverage compared to PVD.

A second conformal passivation layer 124 is disposed over the first conformal passivation layer 122. The second conformal passivation layer 124 may help protect the first conformal passivation layer 122 during processing. In some embodiments, the second conformal passivation layer 124 may be made of a nitride (e.g., SiN) or an oxide (e.g., SiO)₂) And (4) preparing. Thickness of the second conformal passivation layer 124The degree may be greater than the thickness of the first conformal passivation layer 122, and the second conformal passivation layer 124 may be formed by a different technique than the technique used to form the first conformal passivation layer 122. For example, in some embodiments, the second conformal passivation layer 124 may have a thickness of about 50 nanometers to about 500 nanometers. Further, for example, in some embodiments, the second conformal passivation layer 124 may be formed by Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or Physical Vapor Deposition (PVD).

Conductive source/ drain regions 116, 118 extend down through the first and second passivation layers 122, 124 to ohmically couple to the ternary III/V semiconductor layer 108. For example, conductive source/ drain regions 116, 118 may be a metal such as copper, aluminum, tungsten, nickel, iron, cobalt, silver, gold, or platinum.

A conformal dielectric cap 126 overlies the conductive source/ drain regions 116, 118. For example, in some embodiments, the conformal dielectric cap layer 126 is a nitride (e.g., SiN) or an oxide (e.g., SiO)₂). In some embodiments, the thickness of the conformal dielectric cap layer 126 is greater than or equal to the thickness of the second conformal passivation layer 124.

A metal electrode pad or metal electrode contact 128 extends down through the dielectric capping layer 126 and through the first and second passivation layers 122 and 124 to form an ohmic connection with the gate structure 120. In some embodiments, the metal electrode pad or metal electrode contact 128 is formed by PVD or CVD. A metal electrode pad or metal electrode contact 128 may extend down the sidewalls of the capping layer 126 and the sidewalls of the first and second passivation layers 122, 124 before making ohmic contact with the upper surface region of the gate structure 120.

Due to the difference in band gap between the binary III/V layer 106 and the ternary III-V layer 108, highly mobile charge carriers in the form of a two-dimensional electron gas (2DEG) are established at the interface between the layers 106, 108. Thus, during operation, a voltage applied to gate electrode 120 controls the number of carriers (e.g., 2DEG) that can flow from source 116 through the channel region in layer 106 to drain 118 (or vice versa). Thus, whether the HEMT 100 is in a conductive state or a resistive state can be controlled by controlling the 2DEG with the help of the gate electrode 120. In many cases, the HEMT device 100 is an enhancement mode device that operates similar to a silicon MOSFET device by being generally in a non-conductive state (normally off). Due to the nature of the heterojunction interface between 106/108 and the formation of a 2DEG at this heterojunction interface in a HEMT, such devices formed in III-N material systems tend to be normally-on or depletion mode devices. The high electron mobility of the 2DEG at the interface of the AlGaN/GaN layers allows III-N devices, such as HEMT devices, to conduct without the application of a gate potential.

In the off-state, conventional enhancement mode HEMT (e-HEMT) devices may exhibit current leakage from their gate structures. In some cases, the passivation layer 122 may help limit this current leakage by about an order of magnitude.

Fig. 2 illustrates a flow diagram of some embodiments of a method of fabricating a HEMT device according to some embodiments of the present invention. While the methods are illustrated and described below as a series of steps or events, it will be appreciated that the illustrated ordering of such steps or events are not to be interpreted in a limiting sense. For example, some steps may be performed in a different order and/or concurrently with other steps or events apart from those illustrated and/or described herein. Moreover, not all illustrated steps may be required to implement one or more aspects or embodiments described herein. Further, one or more of the steps illustrated herein may be implemented in one or more separate steps and/or stages.

In step 202, a first buffer layer made of a first III-nitride material is formed over a substrate. In step 204, a second buffer layer is formed over the first buffer layer, wherein the second buffer layer is made of a second ill-nitride material that is different from the first ill-nitride material. In step 206, a binary III-nitride channel layer is formed over the second buffer layer. In step 208, a ternary III-nitride barrier layer is formed over the binary III-nitride channel layer. The ternary III-nitride barrier layer is in contact with the binary III-nitride channel layer at the heterojunction interface. In step 210, a binary III-nitride gate layer is formed over the ternary III-nitride barrier layer and is doped with donor or acceptor impurities. In step 212, selected portions of the doped binary III-nitride gate layer are removed to form a patterned doped binary III-nitride gate structure having a gate upper surface and gate outer sidewalls. Removal of these selected portions exposes the upper surface regions of the ternary ill-nitride barrier layer. In step 214, a first conformal passivation layer is formed over the gate upper surface, the gate outer sidewalls and the exposed upper surface regions of the ternary ill-nitride barrier layer. The first conformal passivation layer may help reduce gate sidewall traps and thus help limit current leakage from the gate structure during operation of the device.

Turning now to fig. 3-11, a series of cross-sectional views that collectively illustrate the formation of a HEMT device can be seen, in accordance with some embodiments. It will be understood that although specific structural components are disclosed in these cross-sectional views, these specific structural components are not required in all embodiments.

Fig. 3 is consistent with some embodiments of the structure formed by reference numerals 202 to 210 of fig. 2. The structure of fig. 3 includes a substrate 302 that may take a variety of different forms. In some embodiments, substrate 302 is a silicon substrate, a silicon carbide (SiC) substrate, or a sapphire substrate. A first buffer layer 304 is then formed over the substrate 302, for example, by epitaxial growth techniques, and in some cases, the first buffer layer 304 may be referred to as a lower buffer layer. In some cases, the first buffer layer 304 is an aluminum nitride (AlN) layer. A second buffer layer 306 is then formed over the first buffer layer 304, for example, by epitaxial growth techniques, and in some cases, the second buffer layer 306 may be referred to as the uppermost buffer layer. In some cases, the second buffer layer 306 is an AlGaN layer. A binary III-nitride channel layer 308 is then formed over the second buffer layer 306, for example, by epitaxial growth techniques. In some cases, binary III-nitride channel layer 308 is a GaN layer. A ternary ill-nitride barrier layer 310 is formed over binary ill-nitride channel layer 308, for example, by an epitaxial growth technique. In some embodiments, ternary ill-nitride barrier layer 310 is Al_xGa_{1- x}N layers of which 0<x<1. A binary III-nitride gate layer 312 is formed over ternary III-nitride barrier layer 310, for example, by epitaxial growth techniques, and binary III-nitride gate layer 312 is doped with donor or acceptor impurities. In some embodiments, binary III-nitride gate layer 312 is an n-type or p-type GaN layer.

In fig. 4, a gate structure mask layer is formed and patterned over the binary III-nitride gate layer. The gate structure mask layer may be a photoresist layer, a hard mask layer such as a nitride layer, and/or other individual layers or combinations of layers. With the patterned gate structure mask 402 in place, an etch is performed to selectively remove the exposed portions of the binary III-nitride gate layer 312, leaving the gate structure 312' with the gate structure mask 402 over it. The patterned gate structure mask 402 is then removed.

In fig. 5, a first conformal passivation layer 502 is formed by Atomic Layer Deposition (ALD). In some embodiments, the first conformal passivation layer 502 is AlN or BN and is deposited to have a thickness between about 5 angstroms and 500 angstroms. To limit gate sidewall traps, the first conformal passivation layer 502 directly abuts the sidewalls and upper surface of the gate electrode 312'.

In fig. 6, a second conformal passivation layer 602 is formed over the first conformal passivation layer 502 to protect the first conformal passivation layer 502 during processing. In some embodiments, the second conformal passivation layer is a nitride such as, for example, SiN, or a material such as, for example, SiO₂An oxide of (a). In some embodiments, the second conformal passivation layer 602 is formed by a different technique than the first conformal passivation layer 502. For example, the second conformal passivation layer 602 may be formed by CVD, PECVD, or PVD with a faster deposition rate than that of ALD to maintain process throughput at a good level. To help protect the first conformal passivation layer 502, the thickness of the second passivation layer 602 may be in the range of about 50nm and about 500 nm.

In fig. 7, a source/drain mask 700 has been formed over the second conformal passivation layer. With the source/drain mask 700 in place, an etch, such as, for example, a dry etch, is performed to form source/drain openings 702, the source/drain openings 702 extending through the first and second conformal passivation layers 502, 602 and terminating on the ternary ill-nitride barrier layer 310. Some portions of the ternary ill-nitride barrier layer 310 may be removed/consumed during this etch and other portions may remain under the source/drain openings 702 located above the ternary ill-nitride barrier layer 310. In fig. 8, the source/drain mask 700 is removed and the source/drain openings are filled with a conductive material, such as a metal. The initially formed metal extends over the entire exposed surface of the second conformal passivation layer. Subsequently, a mask (not shown), such as a photoresist mask, is formed over the source/drain regions, and an etch, such as a dry etch, is performed to form the conductive source/drain regions 802 as shown.

In fig. 9, a conformal dielectric cap layer 902 is formed. In some embodiments, the conformal dielectric cap layer is a nitride such as, for example, SiN or a nitride such as, for example, SiO₂An oxide of (a).

In fig. 10, a gate electrode mask 1000 is formed over the dielectric capping layer. With the gate electrode mask in place, etching such as dry etching is performed to form a gate electrode opening 1002. A gate electrode opening extends through the dielectric capping layer, the first conformal passivation layer, and the second conformal passivation layer. The gate electrode opening terminates on a patterned doped binary III-nitride gate structure.

In fig. 11, a conductive gate electrode pad 1100 is formed in the gate electrode opening. In some embodiments, the conductive gate electrode liner is deposited by PVD or CVD. For example, the conductive gate electrode layer may include a metal such as aluminum, copper, tungsten, or nickel or may include other conductive materials such as doped polysilicon, for example.

It will be appreciated from the foregoing that the present invention sets forth techniques for forming a passivation layer over the sidewalls of the gate electrode to confine interface traps. The passivation layer terminates and passivates dangling bonds on the surface of the gate sidewall surface to limit the number of interface traps and help improve device performance. In particular, the passivation layer reduces gate leakage current.

Accordingly, some embodiments of the present invention are directed to High Electron Mobility Transistors (HEMTs) that include a heterojunction structure disposed above a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material that serves as a channel region of the e-HEMT and a ternary III/V semiconductor layer disposed over the binary III/V semiconductor layer and made of a second III-nitride material that serves as a barrier layer. The source and drain regions are disposed over the ternary III/V semiconductor layer and are laterally spaced apart from each other. A gate structure is disposed over the heterojunction structure and between the source region and the drain region. The gate structure is made of a third III-nitride material. The first conformal passivation layer is disposed around sidewalls of the gate structure and is made of a fourth ill-nitride material.

In the above HEMT, wherein the third III-nitride material of the gate structure is a binary III/V semiconductor material and has the same binary semiconductor composition as the first III-nitride material, and the fourth III-nitride material of the first passivation layer is a binary III/V semiconductor material and has a different binary semiconductor composition than the first III-nitride material and the second III-nitride material.

In the above HEMT, wherein the gate structure is a doped n-type or doped p-type gate structure and wherein the binary III/V semiconductor layer is an intrinsic semiconductor material.

In the above HEMT, wherein the first passivation layer is conformal and has a thickness between 5 and 500 angstroms.

In the HEMT, the HEMT further comprises: a second passivation layer having a thickness of 50nm to 500nm and conformally covering the first passivation layer, wherein a material composition of the second passivation layer is different from a material composition of the first passivation layer.

In the HEMT, the HEMT further comprises: one or more buffer layers below the binary III/V semiconductor layer, wherein an uppermost buffer layer is made of the second III-nitride material, and wherein a lower buffer layer below the uppermost buffer layer is made of the first III-nitride material.

In the HEMT, the HEMT further comprises: one or more buffer layers below the binary III/V semiconductor layer, wherein an uppermost buffer layer is made of the second III-nitride material, and wherein a lower buffer layer below the uppermost buffer layer is made of the first III-nitride material, wherein the first passivation layer is made of the same material as the lower buffer layer.

In the HEMT, the HEMT further comprises: one or more buffer layers below the binary III/V semiconductor layer, wherein an uppermost buffer layer is made of the second III-nitride material, and wherein a lower buffer layer below the uppermost buffer layer is made of the first III-nitride material, wherein the first passivation layer is made of the same material as the lower buffer layer, wherein the first III-nitride material of the binary III/V semiconductor layer is GaN; the second III-nitride material of the ternary III/V semiconductor layer is Al_xGa_1-xN; the third III-nitride material of the gate structure is n-type GaN or p-type GaN; and the fourth III-nitride material of the first passivation layer is AlN or BN.

In the HEMT, the HEMT further comprises: a second passivation layer conformally disposed over the first passivation layer and having a second thickness that is greater than the first thickness of the first passivation layer; a capping layer conformally disposed over an upper surface region of the second passivation layer; and a metal gate electrode including an edge overlying the upper surface region of the capping layer and including an inner sidewall extending down the capping layer along a sidewall of the opening, through the second passivation layer and through the first passivation layer to be in direct electrical connection with the upper surface of the gate structure.

Other embodiments of the invention are directed to a method of forming an enhancement-mode, high electron mobility transistor (e-HEMT) on a substrate. In the method, a binary III-nitride channel layer is formed over a substrate. A ternary III-nitride barrier layer is formed over the binary III-nitride channel layer. The ternary III-nitride barrier layer is in contact with the binary III-nitride channel layer at the heterojunction interface. A binary III-nitride gate layer is formed over the ternary III-nitride barrier layer and is doped with donor or acceptor impurities. Select portions of the doped binary III-nitride gate layer are removed to form a patterned doped binary III-nitride gate structure having a gate upper surface and gate outer sidewalls. Removing selected portions of the gate layer exposes upper surface regions of the ternary ill-nitride barrier layer. A first conformal passivation layer is formed over the upper surface of the gate, over the outer sidewalls of the gate, and over the exposed upper surface regions of the ternary ill-nitride barrier layer.

In the above method, wherein the first conformal passivation layer is formed by Atomic Layer Deposition (ALD).

In the above method, further comprising: forming a second conformal passivation layer over the first conformal passivation layer, wherein the second conformal passivation layer is formed by a different technique than the first conformal passivation layer.

In the above method, further comprising: forming a second conformal passivation layer over the first conformal passivation layer, wherein the second conformal passivation layer is formed by a different technique than the first conformal passivation layer, wherein the first conformal passivation layer is formed by ALD and has a thickness between about 5 angstroms and about 500 angstroms, and wherein the second conformal passivation layer is formed by CVD, PECVD or PVD and has a thickness between about 50nm and about 500nm to protect the first conformal passivation layer during processing.

In the above method, further comprising: forming a second conformal passivation layer over the first conformal passivation layer, wherein the second conformal passivation layer is formed by a different technique than the first conformal passivation layer, wherein the method further comprises: forming a source/drain mask over the second conformal passivation layer; performing an etch with the source/drain mask in place to form source/drain openings that extend through the first and second conformal passivation layers and terminate on the ternary ill-nitride barrier layer; and filling the source/drain openings with a conductive material.

In the above method, further comprising: forming a second conformal passivation layer over the first conformal passivation layer, wherein the second conformal passivation layer is formed by a different technique than the first conformal passivation layer, wherein the method further comprises: forming a source/drain mask over the second conformal passivation layer; performing an etch with the source/drain mask in place to form source/drain openings that extend through the first and second conformal passivation layers and terminate on the ternary ill-nitride barrier layer; and filling the source/drain openings with a conductive material, the method further comprising: patterning the conductive material to form source/drain conductive bodies; forming a dielectric capping layer over the source/drain conductive body; forming a gate electrode mask over the dielectric capping layer; performing an etch with the gate electrode mask in place to form a gate electrode opening extending through the dielectric cap layer, the first conformal passivation layer, and the second conformal passivation layer, wherein the gate electrode opening terminates on the patterned doped binary ill-nitride gate structure; and forming a conductive gate electrode pad in the gate electrode opening.

In the above method, further comprising: forming a second conformal passivation layer over the first conformal passivation layer, wherein the second conformal passivation layer is formed by a different technique than the first conformal passivation layer, wherein the method further comprises: forming a source/drain mask over the second conformal passivation layer; performing an etch with the source/drain mask in place to form source/drain openings that extend through the first and second conformal passivation layers and terminate on the ternary ill-nitride barrier layer; and filling the source/drain openings with a conductive material, the method further comprising: patterning the conductive material to form source/drain conductive bodies; forming a dielectric capping layer over the source/drain conductive body; over the dielectric cap layerForming a gate electrode mask; performing an etch with the gate electrode mask in place to form a gate electrode opening extending through the dielectric cap layer, the first conformal passivation layer, and the second conformal passivation layer, wherein the gate electrode opening terminates on the patterned doped binary ill-nitride gate structure; and forming a conductive gate electrode pad in the gate electrode opening, wherein the binary III-nitride channel layer is made of GaN; the ternary III-nitride barrier layer is made of Al_xGa_1-xN is prepared; the patterned doped binary III-nitride gate structure is n-type GaN or p-type GaN; the first conformal passivation layer is AlN or BN; the second conformal passivation layer is SiO₂Or SiN; and the dielectric cap layer is SiN or SiO₂。

In the above method, further comprising: forming a second conformal passivation layer over the first conformal passivation layer, wherein the second conformal passivation layer is formed by a different technique than the first conformal passivation layer, wherein the method further comprises: forming a first buffer layer prior to forming the binary III-nitride channel layer over the substrate; and forming a second buffer layer over the first buffer layer prior to forming the binary ill-nitride channel layer over the substrate.

In the above method, further comprising: forming a second conformal passivation layer over the first conformal passivation layer, wherein the second conformal passivation layer is formed by a different technique than the first conformal passivation layer, wherein the method further comprises: forming a first buffer layer prior to forming the binary III-nitride channel layer over the substrate; and forming a second buffer layer over the first buffer layer prior to forming the binary ill-nitride channel layer over the substrate, wherein the first conformal passivation layer is made of the same material as the first buffer layer.

Still other embodiments relate to a High Electron Mobility Transistor (HEMT) formed on a substrate. The HEMT includes an AlN buffer layer located over a substrate. The AlGaN buffer layer is disposed over the AlN buffer layer. The GaN channel layer is disposed over the AlGaN buffer layer. An AlGaN barrier layer is disposed over the GaN channel layer. A GaN gate structure is disposed over the AlGaN barrier layer. The GaN gate structure is doped with acceptor or donor impurities and has a gate structure upper surface and a gate structure outer sidewall. An AlN or BN conformal passivation layer is disposed over the gate structure upper surface and abuts the gate structure outer sidewalls.

In the above HEMT, the HEMT further comprises: a second passivation layer having a thickness of 50nm to 500nm and conformally covering the AlN or BN conformal passivation layer, wherein a material composition of the second passivation layer is different from a material composition of the AlN or BN conformal passivation layer.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.