阅读说明：本技术 屏蔽栅沟槽功率器件及其制造方法 (Shielded gate trench power device and method of making same ) 是由 杨亚锋 石磊 于 2020-08-06 设计创作，主要内容包括：本发明公开了一种屏蔽栅沟槽功率器件,器件单元区的栅极结构包括：形成在栅极沟槽的内侧表面的屏蔽介质层；屏蔽介质层由热氧化层和CVD介质层叠加而成；在屏蔽介质层填充形成的间隙区中填充有源多晶硅；在源多晶硅两侧形成有由对靠近栅极沟槽的侧面的部分屏蔽介质层刻蚀后形成的顶部沟槽,顶部沟槽完全位于热氧化层中；顶部沟槽的第二侧面和源多晶硅之间的屏蔽介质层作为多晶硅间介质层；在顶部沟槽中填充有多晶硅栅且在顶部沟槽的第一侧面上形成有栅介质层。本发明还公开了一种屏蔽栅沟槽功率器件的制造方法。本发明能提高沟槽侧壁及底部屏蔽介质层的厚度均匀性,从而能保证器件的耐压的同时降低器件的导通电阻,同时还能降低器件的栅源电容。(The invention discloses a power device of a shielded gate groove, wherein a gate structure of a device unit area comprises: the shielding dielectric layer is formed on the inner side surface of the grid groove; the shielding dielectric layer is formed by superposing a thermal oxidation layer and a CVD dielectric layer; filling source polysilicon in a gap region formed by filling the shielding dielectric layer; forming top grooves formed by etching partial shielding medium layers close to the side faces of the grid grooves on two sides of the source polycrystalline silicon, wherein the top grooves are completely positioned in the thermal oxidation layer; a shielding dielectric layer between the second side surface of the top groove and the source polysilicon is used as an inter-polysilicon dielectric layer; the top trench is filled with a polysilicon gate and a gate dielectric layer is formed on a first side of the top trench. The invention also discloses a manufacturing method of the shielding grid groove power device. The invention can improve the thickness uniformity of the side wall and the bottom shielding dielectric layer of the groove, thereby ensuring the withstand voltage of the device, reducing the on-resistance of the device and simultaneously reducing the gate-source capacitance of the device.)

1. A shielded gate trench power device, wherein the gate structure of the device unit region comprises:

the semiconductor device comprises a first conductive type doped epitaxial layer formed on a semiconductor substrate, wherein a grid groove is formed in the epitaxial layer;

forming shielding dielectric layers on the bottom surface and the side surface of the grid groove; the shielding dielectric layer is formed by overlapping a thermal oxidation layer and a CVD dielectric layer, so that the thickness of the shielding dielectric layer is increased, and the thickness uniformity of the side wall of the groove and the thickness of the bottom shielding dielectric layer is ensured, thereby increasing the withstand voltage of the shielding dielectric layer and reducing the withstand voltage requirement of the epitaxial layer;

the shielding medium layer does not completely fill the grid groove, a clearance area is formed in the central area of the grid groove, and source polycrystalline silicon is filled in the clearance area;

forming top grooves formed by performing anisotropic etching on partial areas of the shielding medium layer close to the side faces of the grid grooves on two sides of the source polycrystalline silicon, wherein the top grooves are completely positioned in the thermal oxidation layer; the first side face of the top groove is the exposed side face of the grid groove, the shielding dielectric layer between the second side face of the top groove and the source polycrystalline silicon is used as an inter-polycrystalline silicon dielectric layer, the inter-polycrystalline silicon dielectric layer is a superposed structure of the CVD dielectric layer and the thermal oxidation layer with partial thickness along the width direction of the inter-polycrystalline silicon dielectric layer, the width of the top groove is defined through photoetching, the width of the inter-polycrystalline silicon dielectric layer is defined at the same time, and the width of the inter-polycrystalline silicon dielectric layer is increased so as to increase the Cgs of the device;

and forming a gate dielectric layer on the first side surface of the top groove, and forming the polysilicon gate which completely fills the top groove in the top groove with the gate dielectric layer.

2. The shielded gate trench power device of claim 1 wherein: the semiconductor substrate comprises a silicon substrate, and the epitaxial layer is a silicon epitaxial layer.

3. The shielded gate trench power device of claim 2 wherein: the CVD dielectric layer is an oxide layer deposited by a CVD process, and the gate dielectric layer is a gate oxide layer.

4. The shielded gate trench power device of claim 3 wherein: the working voltage of the shielded gate trench power device is larger than or equal to 150V.

5. The shielded gate trench power device of claim 1 wherein: the power device of the shielding grid groove is a power MOSFET device of the shielding grid groove, and the structure of the device unit area further comprises:

the body region is formed on the surface of the epitaxial layer and doped with the second conduction type, the top groove penetrates through the body region, and the surface of the body region covered by the side face of the polysilicon gate is used for forming a channel;

forming a source region heavily doped with a first conductive type on the surface of the body region;

the semiconductor substrate is provided with a first conduction type heavily doped structure, and the drain region is formed on the back surface of the thinned semiconductor substrate.

6. The shielded gate trench power device of claim 5 wherein: the shielding grid groove power device also comprises a grid lead-out region; the grid electrode leading-out area is positioned at the outer side of the device unit area, the grid electrode structure is also arranged in the grid electrode leading-out area, the grid electrode structure in the grid electrode leading-out area and the grid electrode structure in the device unit area are formed at the same time, and the polycrystalline silicon gate in the grid electrode leading-out area is contacted with the polycrystalline silicon gate in the device unit area;

a contact hole is formed in the top of the polysilicon gate of the gate structure of the gate lead-out region, and the contact hole in the top of the polysilicon gate is connected to a gate consisting of a front metal layer;

the power device of the shielding grid groove also comprises a source polycrystalline silicon leading-out area, the grid groove is also formed in the source polycrystalline silicon leading-out area, the shielding dielectric layer and the source polycrystalline silicon are formed in the grid groove of the source polycrystalline silicon leading-out area, and the top groove, the grid dielectric layer and the polycrystalline silicon grid are not formed in the grid groove of the source polycrystalline silicon leading-out area; the source polycrystalline silicon in the source polycrystalline silicon leading-out region is contacted with the source polycrystalline silicon in the device unit region; a contact hole is formed at the top of the source polysilicon in the source polysilicon lead-out region and is connected to a source electrode consisting of a front metal layer;

the top of the source region is also formed with a contact hole and connected to the source electrode.

7. The shielded gate trench power device of claim 4 wherein: in the shielding medium layer, the shielding medium layer is provided with a shielding layer,the thickness of the thermal oxidation layer is

8. The shielded gate trench power device of any of claims 1-7 wherein: the shielding grid groove power device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type; or, the shielding grid groove power device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.

9. A manufacturing method of a shielded gate trench power device is characterized in that a gate structure of a device unit area is formed by the following steps:

providing a semiconductor substrate, forming an epitaxial layer doped with a first conduction type on the semiconductor substrate, and forming a grid groove in the epitaxial layer;

step two, forming shielding dielectric layers on the bottom surface and the side surfaces of the grid groove;

the shielding dielectric layer comprises a thermal oxidation layer formed by a thermal oxidation process and a CVD dielectric layer formed by a CVD deposition process, and the thickness of the shielding dielectric layer is increased by the superposition structure of the thermal oxidation layer and the CVD dielectric layer, and the thickness uniformity of the side wall of the grid groove and the thickness of the bottom shielding dielectric layer is ensured, so that the withstand voltage of the shielding dielectric layer is increased and the withstand voltage requirement of the epitaxial layer is reduced;

the shielding medium layer does not completely fill the grid groove and a gap area is formed in the central area of the grid groove;

step three, carrying out a polysilicon growth and etch-back process to fill source polysilicon in the gap region of the gate trench;

fourthly, opening a forming area of the top groove by carrying out a photoetching process, wherein the forming area of the top groove corresponds to a partial area of the shielding dielectric layer close to the side surface of the grid groove; performing anisotropic etching on the shielding dielectric layer in the opening area to form the top groove, wherein the top groove is completely positioned in the thermal oxidation layer; the first side face of the top groove is the exposed side face of the grid groove, the shielding dielectric layer between the second side face of the top groove and the source polycrystalline silicon is used as an inter-polycrystalline silicon dielectric layer, the inter-polycrystalline silicon dielectric layer is a superposed structure of the CVD dielectric layer and the thermal oxidation layer with partial thickness along the width direction of the inter-polycrystalline silicon dielectric layer, and the width of the top groove and the width of the inter-polycrystalline silicon dielectric layer are simultaneously defined through photoetching, so that the width of the inter-polycrystalline silicon dielectric layer is increased to increase the Cgs of a device;

and fifthly, forming a gate dielectric layer on the first side surface of the top groove, and filling polysilicon into the top groove with the gate dielectric layer and forming the polysilicon gate by a polysilicon growth and etch-back process.

10. The method of manufacturing a shielded gate trench power device of claim 9 wherein: the semiconductor substrate comprises a silicon substrate, and the epitaxial layer is a silicon epitaxial layer.

11. The method of manufacturing a shielded gate trench power device of claim 10 wherein: the CVD dielectric layer is an oxide layer deposited by a CVD process, and the gate dielectric layer is a gate oxide layer.

12. The method of manufacturing a shielded gate trench power device of claim 11 wherein: the working voltage of the shielded gate trench power device is larger than or equal to 150V.

13. The method of manufacturing a shielded gate trench power device of claim 9 wherein: the shielding grid groove power device is a shielding grid groove power MOSFET device, and further comprises the following front process steps:

forming a body region doped with a second conductive type on the surface of the epitaxial layer, wherein the top groove penetrates through the body region, and the surface of the body region covered by the side face of the polysilicon gate is used for forming a channel;

forming a source region heavily doped with a first conductive type on the surface of the body region of the device unit region;

the semiconductor substrate is provided with a first conductive type heavily doped structure, and after the front surface process is finished, the method further comprises the following back surface process:

thinning the semiconductor substrate;

forming a drain region by the thinned semiconductor substrate; or carrying out back doping on the thinned semiconductor substrate to form a first conduction type heavily doped drain region.

14. The method of manufacturing a shielded gate trench power device of claim 13 wherein: the shielding grid groove power device also comprises a grid lead-out region; the grid electrode leading-out area is positioned at the outer side of the device unit area, the grid electrode structure is also arranged in the grid electrode leading-out area, the grid electrode structure in the grid electrode leading-out area and the grid electrode structure in the device unit area are formed at the same time, and the polycrystalline silicon gate in the grid electrode leading-out area is contacted with the polycrystalline silicon gate in the device unit area;

the power device of the shielding grid groove also comprises a source polycrystalline silicon leading-out area, the grid groove is also formed in the source polycrystalline silicon leading-out area, the shielding dielectric layer and the source polycrystalline silicon are formed in the grid groove of the source polycrystalline silicon leading-out area, and the top groove, the grid dielectric layer and the polycrystalline silicon grid are not formed in the grid groove of the source polycrystalline silicon leading-out area; the source polycrystalline silicon in the source polycrystalline silicon leading-out region is contacted with the source polycrystalline silicon in the device unit region;

the front side process further comprises:

forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a grid electrode and a source electrode;

a contact hole is formed at the top of the polysilicon gate of the gate structure of the gate lead-out region, and the contact hole at the top of the polysilicon gate is connected to the gate;

a contact hole is formed at the top of the source polysilicon in the source polysilicon lead-out region and connected to the source electrode;

the top of the source region is also formed with a contact hole and connected to the source electrode.

15. The method of manufacturing a shielded gate trench power device of claim 12 wherein: in the shielding dielectric layer, the thickness of the thermal oxidation layer is

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a Shielded Gate (SGT) gate trench power device. The invention also relates to a manufacturing method of the shielding grid groove power device.

Background

As shown in fig. 1A, is a photograph of a top structure of a prior art Shielded Gate Trench (SGT) power device; as shown in fig. 1B, is a photograph of the bottom of the gate structure of the shielded gate trench power device corresponding to fig. 1A; the gate structure of the device unit region of the existing shielded gate trench power device includes:

a gate trench 102 is formed in the epitaxial layer 101. .

A shielding dielectric layer 103 is formed on the bottom surface and the side surface of the gate trench 102; the shielding dielectric layer 103 is composed of a thermal oxide layer.

The gate trench 102 is not completely filled by the shielding dielectric layer 103, and a gap region is formed in the central region of the gate trench 102, and the gap region is filled with source polysilicon 104.

Top grooves formed by anisotropic etching of the shielding dielectric layer 103 are formed on two sides of the source polysilicon 104.

A gate oxide layer 105 is formed on the first side surface of the top trench, that is, the side surface of the gate trench 102 exposed from the top trench, the gate oxide layer 105 is usually formed by a thermal oxidation process, an inter-polysilicon oxide layer 106 is formed while the gate oxide layer 105 is formed, and the thickness of the inter-polysilicon oxide layer 106 is greater than that of the gate oxide layer 105 by utilizing the characteristic that the oxidation rate of the source polysilicon 104 is faster than that of the epitaxial layer 101.

The polysilicon gate 107 is formed in the top trench in which the gate oxide layer 105 is formed to completely fill the top trench.

A body region is formed on the surface of the epitaxial layer 101 between the gate structures, and a heavily doped source region is formed on the surface of the body region.

An interlayer film 108 and a contact hole passing through the interlayer film 108 are also formed. The opening 109 of the contact hole is shown in fig. 1A, and the opening 109 in fig. 1A exposes the source region surface at the bottom.

The structure shown in fig. 1A is a left-right (L/R) SGT device, and for the prior art L/RSGT with a voltage of 150V or more, due to general process limitations, the thermal oxide layer of the shielding dielectric layer 103 is usually a thermal oxide layer

Due to the limitation of the thermal oxidation process, the thickness of the shielding dielectric layer 103 cannot be increased, and the thicknesses of the shielding dielectric layer 103 on the sidewall and the bottom of the trench 102 are not uniform, so that the withstand voltage of the device cannot be effectively improved by increasing the thickness of the shielding dielectric layer 103, and at this time, in order to improve the withstand voltage of the device, the doping concentration of the epitaxial layer 101 needs to be reduced, which may cause the on-resistance of the device to be less dominant.

In addition, as shown in fig. 1B, due to the characteristics of the thermal oxidation process, the thickness of the shielding dielectric layer 103 is not uniform, wherein the thickness near the bottom of the gate trench 102 becomes smaller, which further degrades the performance of the device.

As shown in fig. 2, the photo of the etched shield dielectric layer in the polysilicon gate forming region of the shield gate trench power device with an improved structure is shown; the gate structure includes:

a gate trench 202 formed in the epitaxial layer 201, and a shield dielectric layer 203 formed on an inner side of the gate trench 202. In order to overcome the problem of the limited thickness of the shielding dielectric layer 203 of the prior art structure of fig. 1A and 1B, the shielding dielectric layer 203 of fig. 2 adopts a stacked structure of a thermal oxide layer plus a CVD deposited oxide layer.

Thereafter, the gate trench 202 is filled with source polysilicon 204.

After the top trench 205 is formed by isotropic etching of the shielding dielectric layer 203 in fig. 2, it can be seen that the depth of the top trench 205 is not uniform, which is caused by the non-uniform etching rate of the thermal oxide layer of the shielding dielectric layer 203 and the CVD-deposited oxide layer by isotropic wet etching, and the CVD-deposited oxide layer has a faster etching rate, which results in the bottom of the top trench 205 having a lower tip structure 206. Such a lower tip structure 206 may eventually increase the gate-source capacitance Cgs of the device, since Cgs may increase due to both the thinning of the thickness of the shield dielectric layer in the lower tip structure 206 and the filling of the polysilicon gate, which may increase the overlap area between the polysilicon gate and the source polysilicon 204.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a shielded gate trench power device, which can improve the thickness of a shielding dielectric layer and the thickness uniformity of the shielding dielectric layer, thereby improving the withstand voltage of the device, reducing the on-resistance of the device, and simultaneously reducing the gate-source capacitance of the device. Therefore, the invention also provides a manufacturing method of the shielded gate trench power device.

In order to solve the above technical problem, the gate structure of the device unit region of the shielded gate trench power device provided by the present invention comprises:

the semiconductor device includes a first-conductivity-type-doped epitaxial layer formed on a semiconductor substrate, in which a gate trench is formed.

Forming shielding dielectric layers on the bottom surface and the side surface of the grid groove; the shielding dielectric layer is formed by overlapping a thermal oxidation layer and a CVD dielectric layer, so that the thickness of the shielding dielectric layer is increased, and particularly, the thickness uniformity of the side wall of the grid groove and the thickness uniformity of the bottom shielding dielectric layer are improved, thereby increasing the withstand voltage of the shielding dielectric layer and reducing the withstand voltage requirement of the epitaxial layer.

And the shielding dielectric layer does not completely fill the grid groove, a gap area is formed in the central area of the grid groove, and source polycrystalline silicon is filled in the gap area.

Forming top grooves formed by performing anisotropic etching on partial areas of the shielding medium layer close to the side faces of the grid grooves on two sides of the source polycrystalline silicon, wherein the top grooves are completely positioned in the thermal oxidation layer; the first side face of the top groove is the exposed side face of the grid groove, the shielding dielectric layer between the second side face of the top groove and the source polycrystalline silicon is used as an inter-polycrystalline silicon dielectric layer, the inter-polycrystalline silicon dielectric layer is a superposed structure of the CVD dielectric layer and the thermal oxidation layer with partial thickness along the width direction of the inter-polycrystalline silicon dielectric layer, the width of the top groove is defined through photoetching, the width of the inter-polycrystalline silicon dielectric layer is defined at the same time, and the width of the inter-polycrystalline silicon dielectric layer is increased so as to increase the Cgs of the device.

And forming a gate dielectric layer on the first side surface of the top groove, and forming the polysilicon gate which completely fills the top groove in the top groove with the gate dielectric layer.

In a further improvement, the semiconductor substrate comprises a silicon substrate, and the epitaxial layer is a silicon epitaxial layer.

The further improvement is that the CVD dielectric layer is an oxide layer deposited by a CVD process, and the gate dielectric layer is a gate oxide layer.

The further improvement is that the working voltage of the shielded gate trench power device is more than or equal to 150V.

In a further improvement, the shielded gate trench power device is a shielded gate trench power MOSFET device, and the structure of the device unit region further includes:

and the top groove penetrates through the body region, and the surface of the body region covered by the side surface of the polysilicon gate is used for forming a channel.

And a source region heavily doped with the first conductivity type is formed on the surface of the body region.

The semiconductor substrate is provided with a first conduction type heavily doped structure, and the drain region is formed on the back surface of the thinned semiconductor substrate.

The further improvement is that the shielded gate trench power device further comprises a gate lead-out region; the grid electrode leading-out area is located on the outer side of the device unit area, the grid electrode structure is also arranged in the grid electrode leading-out area, the grid electrode structure in the grid electrode leading-out area and the grid electrode structure in the device unit area are formed simultaneously, and the polycrystalline silicon gate in the grid electrode leading-out area is contacted with the polycrystalline silicon gate in the device unit area.

And a contact hole is formed at the top of the polysilicon gate of the gate structure of the gate lead-out region, and the contact hole at the top of the polysilicon gate is connected to the gate consisting of the front metal layer.

The power device of the shielding grid groove also comprises a source polycrystalline silicon leading-out area, the grid groove is also formed in the source polycrystalline silicon leading-out area, the shielding dielectric layer and the source polycrystalline silicon are formed in the grid groove of the source polycrystalline silicon leading-out area, and the top groove, the grid dielectric layer and the polycrystalline silicon grid are not formed in the grid groove of the source polycrystalline silicon leading-out area; the source polycrystalline silicon in the source polycrystalline silicon leading-out region is contacted with the source polycrystalline silicon in the device unit region; and a contact hole is formed at the top of the source polysilicon in the source polysilicon lead-out region and connected to a source electrode composed of a front metal layer.

The top of the source region is also formed with a contact hole and connected to the source electrode.

In a further improvement, in the shielding dielectric layer, the thickness of the thermal oxidation layer is

The thickness of the CVD dielectric layer is

The power device of the shielding grid groove is an N-type device, the first conduction type is an N type, and the second conduction type is a P type; or, the shielding grid groove power device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.

In order to solve the above technical problem, in the method for manufacturing a shielded gate trench power device according to the present invention, a gate structure of a device cell region is formed by the following steps:

step one, providing a semiconductor substrate, forming an epitaxial layer doped with a first conduction type on the semiconductor substrate, and forming a grid groove in the epitaxial layer.

And step two, forming a shielding dielectric layer on the bottom surface and the side surface of the grid groove.

The shielding dielectric layer comprises a thermal oxidation layer formed by a thermal oxidation process and a CVD dielectric layer formed by a CVD deposition process, and the thickness of the shielding dielectric layer is increased by the superposition structure of the thermal oxidation layer and the CVD dielectric layer, and the thickness uniformity of the side wall of the grid groove and the thickness uniformity of the bottom shielding dielectric layer are ensured, so that the withstand voltage of the shielding dielectric layer is increased, and the withstand voltage requirement of the epitaxial layer is reduced.

The shielding dielectric layer does not completely fill the gate trench and a gap region is formed in the central region of the gate trench.

And step three, carrying out a polysilicon growth and etch-back process to fill source polysilicon in the gap region of the grid groove.

Fourthly, opening a forming area of the top groove by carrying out a photoetching process, wherein the forming area of the top groove corresponds to a partial area of the shielding dielectric layer close to the side surface of the grid groove; performing anisotropic etching on the shielding dielectric layer in the opening area to form the top groove, wherein the top groove is completely positioned in the thermal oxidation layer; the first side face of the top groove is the exposed side face of the grid groove, the shielding dielectric layer between the second side face of the top groove and the source polycrystalline silicon is used as an inter-polycrystalline silicon dielectric layer, the inter-polycrystalline silicon dielectric layer is a superposed structure of the CVD dielectric layer and the thermal oxidation layer with partial thickness along the width direction of the inter-polycrystalline silicon dielectric layer, and the width of the top groove and the width of the inter-polycrystalline silicon dielectric layer are simultaneously defined through photoetching, so that the width of the inter-polycrystalline silicon dielectric layer is increased to increase the Cgs of a device.

And fifthly, forming a gate dielectric layer on the first side surface of the top groove, and filling polysilicon into the top groove with the gate dielectric layer and forming the polysilicon gate by a polysilicon growth and etch-back process.

In a further improvement, the semiconductor substrate comprises a silicon substrate, and the epitaxial layer is a silicon epitaxial layer.

The further improvement is that the CVD dielectric layer is an oxide layer deposited by a CVD process, and the gate dielectric layer is a gate oxide layer.

The further improvement is that the working voltage of the shielded gate trench power device is more than or equal to 150V.

The further improvement is that the shielded gate trench power device is a shielded gate trench power MOSFET device, and the method further comprises the following front process steps:

and forming a body region doped with a second conductive type on the surface of the epitaxial layer, wherein the top groove penetrates through the body region, and the surface of the body region covered by the side face of the polysilicon gate is used for forming a channel.

And forming a source region heavily doped with the first conduction type on the surface of the body region of the device unit region.

The semiconductor substrate is provided with a first conductive type heavily doped structure, and after the front surface process is finished, the method further comprises the following back surface process:

and thinning the semiconductor substrate.

Forming a drain region by the thinned semiconductor substrate; or carrying out back doping on the thinned semiconductor substrate to form a first conduction type heavily doped drain region.

The further improvement is that the shielded gate trench power device further comprises a gate lead-out region; the grid electrode leading-out area is located on the outer side of the device unit area, the grid electrode structure is also arranged in the grid electrode leading-out area, the grid electrode structure in the grid electrode leading-out area and the grid electrode structure in the device unit area are formed simultaneously, and the polycrystalline silicon gate in the grid electrode leading-out area is contacted with the polycrystalline silicon gate in the device unit area.

The power device of the shielding grid groove also comprises a source polycrystalline silicon leading-out area, the grid groove is also formed in the source polycrystalline silicon leading-out area, the shielding dielectric layer and the source polycrystalline silicon are formed in the grid groove of the source polycrystalline silicon leading-out area, and the top groove, the grid dielectric layer and the polycrystalline silicon grid are not formed in the grid groove of the source polycrystalline silicon leading-out area; the source polysilicon in the source polysilicon lead-out region is in contact with the source polysilicon in the device unit region.

The front side process further comprises:

forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a grid electrode and a source electrode.

And a contact hole is formed at the top of the polysilicon gate of the gate structure of the gate lead-out region, and the contact hole at the top of the polysilicon gate is connected to the gate.

And a contact hole is formed at the top of the source polysilicon in the source polysilicon lead-out region and connected to the source electrode.

The top of the source region is also formed with a contact hole and connected to the source electrode.

In a further improvement, in the shielding dielectric layer, the thickness of the thermal oxidation layer is

The thickness of the CVD dielectric layer is

The grid structure of the device unit area of the shielded grid groove power device is of a left-right structure, the shielding dielectric layer adopts a superposed structure of the thermal oxidation layer and the CVD dielectric layer, the thickness of the shielding dielectric layer can be increased, the thickness uniformity of the shielding dielectric layer on the side wall and the bottom of the grid groove can be ensured, the withstand voltage of the shielding dielectric layer can be increased, and the withstand voltage requirement of the epitaxial layer can be reduced, so that the doping concentration of the epitaxial layer can be improved, the higher the doping concentration of the epitaxial layer is, the smaller the on-resistance of the device is, and the on-resistance of the device can be reduced under the condition that the withstand voltage of the device is improved or.

Meanwhile, the top groove for forming the polysilicon gate is defined by adopting a photoetching process, then the top groove is formed by utilizing anisotropic etching, and the top groove is completely positioned in the thermal oxide layer, so that the defects of non-uniform depth of the top groove and non-uniform thickness of the inter-polysilicon dielectric layer when the etching rate of the CVD dielectric layer is greater than that of the thermal oxide layer when the CVD dielectric layer is introduced for thickening the shielding dielectric layer can be prevented, the thickness of the inter-polysilicon dielectric layer can be accurately controlled and thickened, and the depth of the side surface of the polysilicon gate covering the inter-polysilicon dielectric layer is fixed and reduced, so that the Cgs of a device, namely the gate source capacitance can be reduced.

In addition, the shielding dielectric layer adopts a superposed structure of the thermal oxidation layer and the CVD dielectric layer, so that the defect that the thickness of the shielding dielectric layer is not uniform when the thermal oxidation layer is singly adopted can be eliminated, and finally, the uniformity of the thickness of the shielding dielectric layer can be improved.

In addition, although the top trench in the prior art is formed by anisotropic etching, a photolithography process is still required to form the gate and source lead-out regions outside the device cell region, so the photolithography process of the top trench of the present invention does not increase the process cost.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

fig. 1A is a photograph of a top structure of a prior art shielded gate trench power device;

fig. 1B is a photograph of the bottom of the gate structure of the shielded gate trench power device corresponding to fig. 1A;

FIG. 2 is a photograph of an etched shield dielectric layer in a polysilicon gate forming region of a prior art structure-improved shielded gate trench power device;

FIG. 3 is a schematic diagram of a shielded gate trench power device according to an embodiment of the present invention;

fig. 4A is a photograph of a shielded gate trench power device in accordance with an embodiment of the present invention;

fig. 4B is a photograph of the bottom of a gate structure of a shielded gate trench power device in accordance with an embodiment of the present invention;

fig. 5A-5D are schematic device structures in steps of a method for manufacturing a shielded gate trench power device according to an embodiment of the invention.

Detailed Description

Fig. 3 is a schematic structural diagram of a shielded gate trench power device according to an embodiment of the present invention; only one gate structure is shown in the device cell region 401 in fig. 3, and in practice, the device cell region 401 includes a plurality of device cells each provided with a gate structure. The gate structure of the device unit region 401 of the shielded gate trench power device according to the embodiment of the present invention includes:

a first conductivity type doped epitaxial layer 2 formed on a semiconductor substrate 1, a gate trench 301 being formed in said epitaxial layer 2. In fig. 3, the semiconductor substrate 1 is also denoted SUB and the epitaxial layer 2 is also denoted EPI.

In the embodiment of the present invention, the semiconductor substrate 1 includes a silicon substrate, and the epitaxial layer 2 is a silicon epitaxial layer 2.

A shielding dielectric layer 3 is formed on the bottom surface and the side surface of the gate trench 301; the shielding dielectric layer 3 is formed by overlapping a thermal oxidation layer 3a and a CVD dielectric layer 3b, so that the thickness of the shielding dielectric layer 3 is increased, and the uniformity of the thickness of the side wall of the grid groove 301 and the thickness of the bottom dielectric layer 3 is ensured, thereby increasing the withstand voltage of the shielding dielectric layer 3 and reducing the withstand voltage requirement of the epitaxial layer 2.

In the embodiment of the invention, the CVD medium layer 3b is an oxide layer deposited by a CVD process,

the shielding dielectric layer 3 does not completely fill the gate trench 301, and a gap region is formed in the central region of the gate trench 301, and the gap region is filled with source polysilicon 4.

A top trench 304 (shown in fig. 5C) formed by etching a partial region of the shielding dielectric layer 3 close to the side surface of the gate trench 301 is formed on both sides of the source polysilicon 4, and the top trench 304 is completely located in the thermal oxide layer 3 a; the first side face of the top groove 304 is the exposed side face of the gate groove 301, the shielding dielectric layer 3 between the second side face of the top groove 304 and the source polysilicon 4 is used as an inter-polysilicon dielectric layer 6, the inter-polysilicon dielectric layer 6 is a superposed structure of the CVD dielectric layer 3b and the thermal oxidation layer 3a with partial thickness along the width direction of the inter-polysilicon dielectric layer 6, the width of the top groove 304 is defined through photoetching, the width of the inter-polysilicon dielectric layer 6 is defined at the same time, and the width of the inter-polysilicon dielectric layer 6 is increased to increase the Cgs of the device.

A gate dielectric layer 5 is formed on a first side of the top trench 304, and the polysilicon gate 7 completely filling the top trench 304 is formed in the top trench 304 in which the gate dielectric layer 5 is formed.

In the embodiment of the invention, the gate dielectric layer 5 is a gate oxide layer.

The working voltage of the shielded gate trench power device is larger than or equal to 150V.

In the shielding dielectric layer 3, the thickness of the thermal oxidation layer 3a is

The thickness of the CVD dielectric layer 3b is

The shielded gate trench power device is a shielded gate trench power MOSFET device, and the structure of the device unit region 401 further includes:

a body region 8 doped with the second conductivity type is formed on the surface of the epitaxial layer 2, the top trench 304 penetrates through the body region 8, and the surface of the body region 8 covered by the side face of the polysilicon gate 7 is used for forming a channel.

A source region 9 heavily doped with the first conductivity type is formed on the surface of the body region 8.

The semiconductor substrate 1 is provided with a first conduction type heavily doped structure, and the drain region is formed on the back surface of the thinned semiconductor substrate 1.

The shielded gate trench power device further includes a gate lead-out region 402; the gate lead-out region 402 is located at the outer side of the device unit region 401, the gate structure is also included in the gate lead-out region 402, the gate structure in the gate lead-out region 402 and the gate structure in the device unit region 401 are formed at the same time, and the polysilicon gate 7 in the gate lead-out region 402 is in contact with the polysilicon gate 7 in the device unit region 401.

A contact hole 11 penetrating through the interlayer film 10 is formed at the top of the polysilicon gate 7 of the gate structure of the gate lead-out region 402, and the contact hole 11 at the top of the polysilicon gate 7 is connected to a gate composed of a front metal layer 12.

The shielded gate trench power device further comprises a source polysilicon leading-out region 403, the gate trench 301 is also formed in the source polysilicon leading-out region 403, the shielded dielectric layer 3 and the source polysilicon 4 are formed in the gate trench 301 of the source polysilicon leading-out region 403, and the top trench 304, the gate dielectric layer 5 and the polysilicon gate 7 are not formed in the gate trench 301 of the source polysilicon leading-out region 403; the source polysilicon 4 in the source polysilicon lead-out region 403 is in contact with the source polysilicon 4 in the device unit region 401; a contact hole 11 is formed on the top of the source polysilicon 4 of the source polysilicon escape region 403 and connected to a source electrode composed of a front metal layer 12.

The top of the source region 9 is also formed with a contact hole 11 and connected to the source electrode.

In the embodiment of the invention, the shielding gate groove power device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type. In other embodiments can also be: the shielding grid groove power device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.

The gate structure of the device unit region 401 of the shielded gate trench power device in the embodiment of the invention is a left-right structure, the shielding dielectric layer 3 adopts a superposed structure of the thermal oxidation layer 3a and the CVD dielectric layer 3b, the thickness of the shielding dielectric layer 3 and the thickness uniformity of the side wall of the gate trench and the bottom dielectric layer 3 can be increased, so that the withstand voltage of the shielding dielectric layer 3 can be increased and the withstand voltage requirement of the epitaxial layer 2 can be reduced, thus the doping concentration of the epitaxial layer 2 can be improved, and the higher the doping concentration of the epitaxial layer 2 is, the smaller the on-resistance of the device is, so that the embodiment of the invention can reduce the on-resistance of the device under the condition of improving the withstand voltage of.

Meanwhile, the top trench 304 for forming the polysilicon gate 7 in the embodiment of the invention is defined by adopting a photolithography process and then is subjected to anisotropic etching, and the top trench 304 is completely positioned in the thermal oxide layer 3a, so that the defects of non-uniform depth of the top trench 304 and non-uniform thickness of the inter-polysilicon dielectric layer 6 caused by the fact that the etching rate of the CVD dielectric layer 3b is greater than that of the thermal oxide layer 3a when the CVD dielectric layer 3b is introduced for thickening the shielding dielectric layer 3 can be prevented, the thickness of the inter-polysilicon dielectric layer 6 can be accurately controlled and thickened, the depth of the side surface of the polysilicon gate 7 covering the inter-polysilicon dielectric layer 6 is fixed and reduced, and finally the Cgs of a device, namely the gate source capacitance, can be.

In addition, the shielding dielectric layer 3 of the embodiment of the invention adopts a superposed structure of the thermal oxidation layer 3a and the CVD dielectric layer 3b, so that the defect that the thickness of the shielding dielectric layer 3 is not uniform when the thermal oxidation layer 3a is adopted independently can be eliminated, and finally, the uniformity of the thickness of the shielding dielectric layer 3 can be improved.

In addition, in the prior art, the top trench 304 is formed by isotropic etching, but a photolithography process is still required to form the lead-out region outside the device cell region, so the photolithography process of the top trench 304 in the embodiment of the present invention does not increase the process cost.

Fig. 4A is a photograph of a shielded gate trench power device according to an embodiment of the present invention; it can be seen that the thickness of the inter-polysilicon dielectric layer 6 of the embodiment of the invention is accurately controlled, i.e. the thickness uniformity is good, and finally the thickness can be increased; the coverage area of the polysilicon gate 7 to the side surface of the interpoly dielectric layer 6 cannot be increased, which is beneficial to reducing Cgs of the device.

Fig. 4B is a photograph of the bottom of the gate structure of the shielded gate trench power device according to an embodiment of the present invention; the thicknesses of the shielding dielectric layer 3 at the positions are shown in fig. 4B, and although the thickness of the thermal oxide layer 3a at the bottom of the gate trench 301 is small, the thickness of the shielding dielectric layer 3 at the positions can be made uniform by overlapping with the CVD dielectric layer 3B.

Fig. 5A to 5D are schematic diagrams of device structures in steps of a method for manufacturing a shielded gate trench power device according to an embodiment of the present invention; in the manufacturing method of the shielded gate trench power device according to the embodiment of the present invention, the gate structure of the device unit region 401 is formed by the following steps:

step one, as shown in fig. 5A, providing a semiconductor substrate 1, forming an epitaxial layer 2 doped with a first conductivity type on the semiconductor substrate 1, and forming a gate trench 301 in the epitaxial layer 2.

In the method of the embodiment of the invention, the semiconductor substrate 1 comprises a silicon substrate, and the epitaxial layer 2 is a silicon epitaxial layer 2.

A hard mask layer 302 is further used in forming the gate trench 301, and the forming steps include:

forming the hard mask layer 302 on the surface of the epitaxial layer 2; in the method of the embodiment of the invention, the hard mask layer 302 includes an ONO structure, and the ONO structure is a stacked structure of an oxide layer, a nitride layer, and an oxide layer. In other embodiments the method can also be: the hard mask layer 302 is silicon nitride or a stacked structure of silicon oxide and silicon nitride.

And performing photolithographic definition, and then sequentially etching the hard mask layer 302 and the epitaxial layer 2 to form the gate trench 301.

Step two, as shown in fig. 5B, a shielding dielectric layer 3 is formed on the bottom surface and the side surface of the gate trench 301.

The shielding dielectric layer 3 comprises a thermal oxidation layer 3a formed by a thermal oxidation process and a CVD dielectric layer 3b formed by a CVD deposition process, the thickness of the shielding dielectric layer 3 is increased by the overlapping structure of the thermal oxidation layer 3a and the CVD dielectric layer 3b, and the thickness uniformity of the side wall of the grid groove 301 and the bottom dielectric layer 3 is ensured, so that the withstand voltage of the shielding dielectric layer 3 is increased and the withstand voltage requirement of the epitaxial layer 2 is reduced.

The shielding dielectric layer 3 does not completely fill the gate trench 301 and a gap region is formed in the central region of the gate trench 301.

In the method of the embodiment of the invention, the CVD medium layer 3b is an oxide layer deposited by a CVD process.

The working voltage of the shielded gate trench power device is larger than or equal to 150V.

In the shielding dielectric layer 3, the thickness of the thermal oxidation layer 3a isThe thickness of the CVD dielectric layer 3b is

Step three, as shown in fig. 5B, a polysilicon growth and etch back process is performed to fill the gap region of the gate trench 301 with source polysilicon 4.

As shown in fig. 5B, the etched back surface of the source polysilicon 4 is lower than the surface of the epitaxial layer 2, for example, lower than the surface of the epitaxial layer 2

Step four, as shown in fig. 5C, a photoresist pattern 303 is formed by a photolithography process to open a forming region of the top trench 304, where the forming region of the top trench 304 corresponds to a partial region of the shielding dielectric layer 3 near the side surface of the gate trench 301; anisotropically etching the shielding dielectric layer 3 in the open area to form the top trench 304, wherein the top trench 304 is completely positioned in the thermal oxide layer 3a, so that the problem of uneven bottom depth of the top trench 304 caused by uneven etching rate of the thermal oxide layer 3a and the CVD dielectric layer 3b can be prevented; the first side face of the top groove 304 is the exposed side face of the gate groove 301, the shielding dielectric layer 3 between the second side face of the top groove 304 and the source polysilicon 4 is used as an inter-polysilicon dielectric layer 6, the inter-polysilicon dielectric layer 6 is a superposed structure of the CVD dielectric layer 3b and the thermal oxidation layer 3a with partial thickness along the width direction of the inter-polysilicon dielectric layer 6, the width of the top groove 304 and the width of the inter-polysilicon dielectric layer 6 are simultaneously defined by photoetching, the situation that the thickness of the inter-polysilicon dielectric layer 6 is small and the depth range of the top groove 304 covering the inter-polysilicon dielectric layer 6 is large can be avoided, and the width of the inter-polysilicon dielectric layer 6 is increased to increase the Cgs of a device.

In the method of the embodiment of the present invention, before the photolithography process for defining the top trench 304 is performed, a step of polishing the surface dielectric layer of the epitaxial layer 2 in a chemical vapor polishing manner is further included, that is, the hard mask layer 302 on the surface of the epitaxial layer 2 is removed.

Step five, as shown in fig. 5D, forming a gate dielectric layer 5 on the first side surface of the top trench 304, performing a polysilicon growth and etch back process to fill polysilicon in the top trench 304 formed with the gate dielectric layer 5 and form the polysilicon gate 7.

As shown in fig. 3, the shielded gate trench power device is a shielded gate trench power MOSFET device, and further includes the following front process steps:

and forming a body region 8 doped with the second conductivity type on the surface for forming the epitaxial layer 2, wherein the top groove 304 penetrates through the body region 8, and the surface of the body region 8 covered by the side face of the polysilicon gate 7 is used for forming a channel.

A source region 9 heavily doped with the first conductive type is formed at the surface of the body region 8 of the device cell region 401.

The semiconductor substrate 1 has a first conductivity type heavily doped structure, and after the front surface process is completed, the back surface process further comprises the following steps:

and thinning the semiconductor substrate 1.

Forming a drain region by the thinned semiconductor substrate 1; or carrying out back doping on the thinned semiconductor substrate 1 to form a first conduction type heavily doped drain region.

In the method of the embodiment of the present invention, the shielded gate trench power device further includes a gate lead-out region 402; the gate lead-out region 402 is located at the outer side of the device unit region 401, the gate structure is also included in the gate lead-out region 402, the gate structure in the gate lead-out region 402 and the gate structure in the device unit region 401 are formed at the same time, and the polysilicon gate 7 in the gate lead-out region 402 is in contact with the polysilicon gate 7 in the device unit region 401.

The shielded gate trench power device further comprises a source polysilicon leading-out region 403, the gate trench 301 is also formed in the source polysilicon leading-out region 403, the shielded dielectric layer 3 and the source polysilicon 4 are formed in the gate trench 301 of the source polysilicon leading-out region 403, and the top trench 304, the gate dielectric layer 5 and the polysilicon gate 7 are not formed in the gate trench 301 of the source polysilicon leading-out region 403; the source polysilicon 4 in the source polysilicon extension region 403 is in contact with the source polysilicon 4 in the device cell region 401.

The front side process further comprises:

an interlayer film 10, a contact hole 11 and a front metal layer 12 are formed, and the front metal layer 12 is patterned to form a gate electrode and a source electrode.

A contact hole 11 is formed at the top of the polysilicon gate 7 of the gate structure of the gate lead-out region 402, and the contact hole 11 at the top of the polysilicon gate 7 is connected to the gate.

A contact hole 11 is formed at the top of the source polysilicon 4 of the source polysilicon escape region 403 and connected to the source electrode.

The top of the source region 9 is also formed with a contact hole 11 and connected to the source electrode.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.