阅读说明：本技术 一种用于小分数锁相环电荷泵电路的电荷平均补偿系统 (Charge average compensation system for fractional phase-locked loop charge pump circuit ) 是由 吴巍 于金鑫 章剑 于 2020-06-23 设计创作，主要内容包括：本发明公开了一种用于小分数锁相环电荷泵电路的电荷平均补偿系统,包括可编程分频器,可编程分频器的输出端依次电连接有电荷泵、锁定检测电路,压控振荡器的输出端电连接有多模分频器,多模分频器的接口电连接有多比特数字解码器,多比特数字解码器的接口与锁定检测电路的输出端电连接,多比特数字解码器的输入端电连接有Sigma delta调制器,多比特数字解码器的输入端电连接有数模转换器,数模转换器的输出端与控制电压模块的输出端电连接,本发明涉及锁相环技术领域。该一种用于小分数锁相环电荷泵电路的电荷平均补偿系统,达到了电荷平均补偿的效果,具有更宽的环路带宽和极高的频率分辨率,有效地减少小分数毛刺,提高整个射频系统的信噪比。(The invention discloses a charge average compensation system for a fractional phase-locked loop charge pump circuit, which comprises a programmable frequency divider, wherein the output end of the programmable frequency divider is sequentially and electrically connected with a charge pump and a lock detection circuit, the output end of a voltage-controlled oscillator is electrically connected with a multi-mode frequency divider, the interface of the multi-mode frequency divider is electrically connected with a multi-bit digital decoder, the interface of the multi-bit digital decoder is electrically connected with the output end of the lock detection circuit, the input end of the multi-bit digital decoder is electrically connected with a Sigma delta modulator, the input end of the multi-bit digital decoder is electrically connected with a digital-to-analog converter, and the output end of the digital-to-analog converter is electrically connected with. The charge average compensation system for the small-fraction phase-locked loop charge pump circuit achieves the effect of charge average compensation, has wider loop bandwidth and extremely high frequency resolution, effectively reduces small-fraction burrs and improves the signal-to-noise ratio of the whole radio frequency system.)

1. A charge averaging compensation system for a fractional phase locked loop charge pump circuit, comprising a programmable divider, characterized in that: the output end of the programmable frequency divider is electrically connected with a charge pump and a locking detection circuit in sequence, the output end of the charge pump is electrically connected with a control voltage module, the output end of the control voltage module is electrically connected with a loop filter, the output end of the loop filter is electrically connected with a voltage-controlled oscillator, the output end of the voltage-controlled oscillator is electrically connected with a multi-mode frequency divider, an interface of the multi-mode frequency divider is electrically connected with a multi-bit digital decoder, an interface of the multi-bit digital decoder is electrically connected with the output end of the locking detection circuit, the input end of the multi-bit digital decoder is electrically connected with a Sigma delta modulator, the input end of the multi-bit digital decoder is electrically connected with a digital-to-analog converter, and.

2. The charge averaging compensation system for a fractional phase locked loop charge pump circuit of claim 1, wherein: the output end of the programmable frequency divider is respectively set to be up pulse and dn pulse, and the up pulse width and the dn pulse width of the output end of the programmable frequency divider are the same as the current pulse width.

3. The charge averaging compensation system for a fractional phase locked loop charge pump circuit of claim 1, wherein: the interface of the multi-mode frequency divider is feedback FCLK and is electrically connected with one input end of the programmable frequency divider.

4. The charge averaging compensation system for a fractional phase locked loop charge pump circuit of claim 1, wherein: one input interface of the Sigma delta modulator is a reference FCLK and is electrically connected with the other input terminal of the programmable frequency divider.

5. The charge averaging compensation system for a fractional phase locked loop charge pump circuit of claim 1, wherein: the other input interface of the Sigma delta modulator is set to a K-bit input.

Technical Field

The invention relates to the technical field of phase-locked loops, in particular to a charge average compensation system for a small-fraction phase-locked loop charge pump circuit.

Background

A typical Phase-locked loop (PLL) circuit includes a Phase Frequency Detector (PFD), a Charge Pump (CP), a loop filter (LPF), and a Voltage Controlled Oscillator (VCO). The phase frequency detector generates two clock phase error pulse signals UP and DN by comparing a reference clock signal and a feedback clock signal, and the two phase error signals are used as the input of a charge pump CP. The charge pump CP generates a corresponding current in response to the previous phase error signal. The current signal flows into the loop filter LPF and generates a voltage signal that controls the voltage controlled oscillator to change the output oscillation frequency. The mismatch of the charge and discharge currents of the charge pump circuit in the phase-locked loop can affect the stability of the output voltage of the loop filter, so that the output voltage of the loop filter generates large ripples, which can seriously affect the output signal frequency of the voltage-controlled oscillator, thereby causing the increase of phase noise of the phase-locked loop and even the phase-locked loop cannot be locked to the set frequency. Therefore, it is increasingly important to reduce the charge and discharge loss of the charge pump circuit in the phase locked loop. Currently, in modern radio frequency communication systems, in order to reduce phase error and achieve fast locking, the pll should have a wide loop bandwidth. The traditional integer phase-locked loop has low loop bandwidth and extremely high frequency resolution, however, besides the problem of charge-discharge current mismatch of the charge pump circuit, the problem is that the charge pump circuit generates a plurality of fractional glitches, which is characterized in that a plurality of glitch frequencies are generated around a carrier frequency, thereby seriously influencing the signal-to-noise ratio of a radio frequency system.

Disclosure of Invention

Technical problem to be solved

The charge average compensation system for the charge pump circuit of the fractional phase-locked loop solves the problems that the traditional integer phase-locked loop has low loop bandwidth and extremely high frequency resolution, but the charge pump circuit has charge-discharge current mismatch, namely, the charge pump circuit generates a plurality of fractional burrs and is characterized by generating a plurality of burr frequencies around a carrier frequency, thereby seriously influencing the signal-to-noise ratio of a radio frequency system.

(II) technical scheme

In order to achieve the purpose, the invention is realized by the following technical scheme: a charge average compensation system for a fractional phase locked loop charge pump circuit includes a programmable divider, the output end of the programmable frequency divider is electrically connected with a charge pump and a locking detection circuit in sequence, the output end of the charge pump is electrically connected with a control voltage module, the output end of the control voltage module is electrically connected with a loop filter, the output end of the loop filter is electrically connected with a voltage-controlled oscillator, the output end of the voltage-controlled oscillator is electrically connected with a multi-modulus frequency divider, the interface of the multi-modulus frequency divider is electrically connected with a multi-bit digital decoder, the interface of the multi-bit digital decoder is electrically connected with the output end of the lock detection circuit, the input end of the multi-bit digital decoder is electrically connected with a Sigma delta modulator, the input end of the multi-bit digital decoder is electrically connected with a digital-to-analog converter, and the output end of the digital-to-analog converter is electrically connected with the output end of the control voltage module.

Preferably, the output end of the programmable frequency divider is respectively set to be an up pulse and a dn pulse, and the up pulse width and the dn pulse width of the output end of the programmable frequency divider are the same as the current pulse width.

Preferably, the interface of the multi-modulus frequency divider is feedback FCLK and is electrically connected with one input end of the programmable frequency divider.

Preferably, one input interface of the Sigma delta modulator is a reference FCLK and is electrically connected to the other input of the programmable frequency divider.

Preferably, the other input interface of the Sigma delta modulator is set to a K-bit input.

(III) advantageous effects

The invention provides a charge average compensation system for a fractional phase-locked loop charge pump circuit. The method has the following beneficial effects:

(1) the charge average compensation system for the small-fraction phase-locked loop charge pump circuit is characterized in that a charge pump and a lock detection circuit are sequentially and electrically connected through the output end of a programmable frequency divider, the output end of the charge pump is electrically connected with a control voltage module, the output end of the control voltage module is electrically connected with a loop filter, the output end of the loop filter is electrically connected with a voltage-controlled oscillator, the output end of the voltage-controlled oscillator is electrically connected with a multi-mode frequency divider, an interface of the multi-mode frequency divider is electrically connected with a multi-bit digital decoder, an interface of the multi-bit digital decoder is electrically connected with the output end of the lock detection circuit, the input end of the multi-bit digital decoder is electrically connected with a Sigma delta modulator, the input end of the multi-bit digital decoder is electrically connected with a digital, the method can realize perfect current matching of the charge pump, has wider loop bandwidth and extremely high frequency resolution, effectively reduces small fraction burrs and improves the signal-to-noise ratio of the whole radio frequency system.

Drawings

FIG. 1 is a diagram of a typical fractional phase-locked loop architecture;

fig. 2 is a schematic diagram of charge-averaging compensation of a charge pump circuit of a phase-locked loop.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1-2, the present invention provides a technical solution: a charge average compensation system for a small-fraction phase-locked loop charge pump circuit comprises a programmable frequency divider, wherein the output end of the programmable frequency divider is sequentially and electrically connected with a charge pump and a locking detection circuit, the output end of the programmable frequency divider is respectively provided with an up pulse and a dn pulse, the up pulse width and the dn pulse width of the output end of the programmable frequency divider are the same as the width of a current pulse, the output end of the charge pump is electrically connected with a control voltage module, the output end of the control voltage module is electrically connected with a loop filter, the output end of the loop filter is electrically connected with a voltage-controlled oscillator, the output end of the voltage-controlled oscillator is electrically connected with a multi-mode frequency divider, an interface of the multi-mode frequency divider is a feedback FCLK and is electrically connected with one input end of the programmable frequency divider, an interface of the multi-mode frequency divider is electrically connected, the input end of the multi-bit digital decoder is electrically connected with a Sigma delta modulator, one input interface of the Sigma delta modulator is a reference FCLK and is electrically connected with the other input end of the programmable frequency divider, the input end of the multi-bit digital decoder is electrically connected with a digital-to-analog converter, the other input interface of the Sigma delta modulator is set to be K-bit input, and the output end of the digital-to-analog converter is electrically connected with the output end of the control voltage module.

When in use, a multi-bit digital decoder and a digital-to-analog converter are added on the traditional fractional phase-locked loop framework, the output signal of a Sigma delta modulator is input into the multi-bit digital decoder, an output bit correction value is generated by a lock detection circuit and is also input into the multi-bit digital decoder, the output correction value is related to the phase error when pfd is input, after the correction value is input into the digital decoder, the digital decoder carries out coding and decoding control, the multi-bit digital decoder controls a divider in a feedback loop and synchronously applies the coded correction value to the current digital-to-analog converter, the digital-to-analog converter converts the output digital signal of the digital decoder into an analog current signal and synchronously injects current pulses into a charge pump, thereby playing a role of compensating the phase error, and the value and the direction of the selected current pulse of the digital-to-analog converter can change according to the output of, the width of the current pulse is the same as that of the up or dn pulse, so that the average charge-discharge current (charge) value is matched, thereby effectively smoothing burrs caused by the mismatch of the charge-discharge current.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation. The use of the phrase "comprising one of the elements does not exclude the presence of other like elements in the process, method, article, or apparatus that comprises the element.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.