阅读说明：本技术 具有非均匀刷新的存储器设备 (Memory device with non-uniform refresh ) 是由 T·沃吉尔桑 于 2019-06-25 设计创作，主要内容包括：一种集成电路存储器设备包括：存储单元阵列,被配置成多个存储体。每个存储体包括多个分段。寄存器存储装置存储表示逐分段刷新参数的逐分段值。刷新逻辑根据对应的逐分段值来刷新每个分段。(An integrated circuit memory device comprising: the memory device includes a memory cell array configured as a plurality of banks. Each memory bank includes a plurality of segments. The register storage stores segment-by-segment values representing segment-by-segment refresh parameters. The refresh logic refreshes each segment according to the corresponding segment-by-segment value.)

1. An Integrated Circuit (IC) memory device, comprising:

a memory cell array configured as a plurality of memory banks, each memory bank including a plurality of segments;

register storage means for storing segment-by-segment values representing a segment-by-segment refresh rate; and

refresh logic to refresh each segment according to the corresponding segment-by-segment value.

2. The IC memory device of claim 1, wherein the refresh logic refreshes each segment during a self-refresh operation.

3. The IC memory device of claim 1, wherein the array of memory cells comprises Dynamic Random Access Memory (DRAM) memory cells.

4. The IC memory device according to claim 3, wherein the register storage receives the segment-wise value from a memory controller.

5. The IC memory device of claim 4, wherein the segment-by-segment refresh rate represents a refresh rate relative to a nominal refresh rate.

6. The IC memory device of claim 1, further comprising:

a temperature compensated refresh circuit to cooperate with the refresh logic to refresh each segment based on temperature.

7. The IC memory device of claim 6, wherein the segment-by-segment refresh rate represents a multiplier value applied to a global temperature-based refresh rate determined by the temperature-compensated refresh circuit.

8. A method of operation in a memory device, the method comprising:

storing data in a memory cell array comprising a plurality of memory banks, each memory bank comprising a plurality of segments;

receiving a segment-by-segment value representing a segment-by-segment refresh rate;

loading the segment-by-segment value into register storage; and

refreshing each segment according to the corresponding segment-by-segment value.

9. The method of claim 8, wherein the refreshing comprises:

each segment is refreshed during a self-refresh operation.

10. The method of claim 8, wherein the refreshing comprises:

each segment is refreshed during an auto-refresh operation.

11. The method of claim 8, wherein the storing data is performed according to a Dynamic Random Access Memory (DRAM) protocol.

12. The method of claim 8, wherein receiving segment-by-segment values comprises: a segment-by-segment value is received from a memory controller.

13. The method of claim 8, wherein the segment-by-segment refresh rate represents a refresh rate relative to a nominal rate.

14. The method of claim 8, further comprising:

generating a temperature-based refresh rate to cooperate with the received segment-by-segment values to refresh each segment based on temperature.

15. The method of claim 14, wherein the segment-by-segment refresh rate represents a multiplier value applied to a temperature-based refresh parameter generated by the temperature-compensated refresh circuit.

16. The method of claim 15, wherein loading the segment-wise value into register storage comprises:

transmitting the segment-by-segment value to the register store in response to a Mode Register Write (MRW) command.

17. An Integrated Circuit (IC) Dynamic Random Access Memory (DRAM) device, comprising:

a memory cell array configured as a plurality of memory banks, each memory bank including at least a first segment and a second segment;

a mode register for storing a first value representing a first refresh rate for refreshing the first segment, the mode register for storing a second value representing a second refresh rate for refreshing the second segment; and

refresh logic to refresh each segment according to the corresponding segment-by-segment value.

18. The IC DRAM device of claim 17, wherein:

the first value and the second value may be freely different from each other.

19. The IC DRAM device of claim 17, wherein each of the first refresh rate and the second refresh rate represents an absolute refresh rate.

20. The IC DRAM device of claim 17, further comprising:

a temperature compensated refresh circuit to cooperate with the refresh logic to refresh each segment based on temperature; and is

Wherein each of the first refresh rate and the second refresh rate represents a multiplier value applied to a global temperature based refresh rate determined by the temperature compensated refresh circuit.

Technical Field

The disclosure herein relates to memory systems and, more particularly, to memory devices, controllers, and methods for changing refresh rates on a segment-by-segment basis.

Drawings

Embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

FIG. 1 illustrates one embodiment of a memory system employing non-uniform refresh.

FIG. 2 illustrates a flow diagram of one example of operations performed during operation of the memory system of FIG. 1.

FIG. 3 illustrates a code/decode table for one embodiment of mode refresh bit encoding/decoding for the memory system of FIG. 1.

Detailed Description

Embodiments of memory devices, controllers, associated methods, and integrated circuits are disclosed herein. One embodiment of a memory device includes a memory cell array configured into a plurality of memory banks. Each memory bank includes a plurality of segments. The register storage stores segment-by-segment values representing a segment-by-segment refresh rate. The refresh logic refreshes each segment according to the corresponding segment-by-segment value. By non-uniformly varying the segment-by-segment refresh rate based on the acceptable error rate associated with the data stored in each segment, a substantial power savings attributable to refresh operations may be realized.

Certain embodiments described herein provide an apparatus and method that varies a refresh rate on a segment-by-segment basis and according to pre-specified error criteria associated with data stored in each segment. The refresh rate can thus be increased or decreased in a manner that tightens or looses read data errors due to refresh operations to correspondingly refresh the memory cells.

Referring to FIG. 1, a memory system, generally designated 100, is shown to include a memory controller 102 coupled to a memory device 104 via a bus 106. For one embodiment, the memory controller is a DRAM controller, wherein the memory device is implemented as a Dynamic Random Access (DRAM) memory device. In some embodiments, the memory controller and the memory device may be embodied as an integrated circuit or chip. Other embodiments may use a memory controller as circuitry in a general purpose processor. Particular embodiments of DRAM memory controllers and memory devices may conform to various DRAM standards, including Double Data Rate (DDR) variants, low power consumption (LPDDR) versions, and Graphics (GDDR) types. Other embodiments may include, for example, multi-chip modules employing stacked memory dies or stacked packages. Such embodiments may be used with memory modules. Additional embodiments may stack the memory die and the logic die together in a common package or in separate packages that are stacked on top of each other.

With further reference to FIG. 1, the memory controller 102 includes a controller interface 107 for communicating data, command, and control signals between the memory controller and the memory device 104. Command generation circuitry 109 generates read/write and Mode Register Write (MRW) commands for transmission to the memory device. For one embodiment, as described below, command generation circuitry 109 generates an MRW command for storing a value associated with the segment-by-segment refresh rate into a mode register on the memory device. The physical memory allocator 112 determines the bank and segment addresses of the physical memory corresponding to the memory requested by the host/processor 114. The memory controller may also include auto-refresh logic 116 to generate refresh commands that are externally applied to the DRAM memory device during an auto-refresh operation. Auto-refresh occurs when the memory system is in an active state to support an actively operating electronic device.

With continued reference to FIG. 1, the host/processor 114 may take the form of a general purpose processor that is responsive to instructions generated by an Operating System (OS) 118. The OS, in turn, allocates logical memory in response to memory requested by a given application 120, and for one embodiment, will generate a tag for the allocated memory, as described more fully below.

With further reference to FIG. 1, memory device 104 includes an array of volatile memory cells, which in one embodiment are organized into banks 122 and 124. Each bank, in turn, is organized into a plurality of addressable segments 126. In one embodiment, each memory device includes eight memory banks, where each memory bank has eight segments. The memory device may include any memory Integrated Circuit (IC) chip having volatile memory cells that maintain a given charge state through periodic refresh operations.

With continued reference to FIG. 1, to perform refresh operations on a segment-by-segment basis, one embodiment of the memory device integrates refresh logic 128. Refresh logic 128 controls internal DRAM operations for self-refresh, auto-refresh, or both. In one embodiment, refresh logic 128 includes a refresh counter that tracks the next address to be refreshed. The mode register circuit 130 provides register storage for segment-by-segment refresh rate values based on an acceptable data error threshold or BER generated by the application 120 and the OS 118. When performing a non-uniform self-refresh operation segment-by-segment, the refresh logic 128 accesses register values.

With further reference to FIG. 1, the memory device 104 includes a memory interface 131, the memory interface 131 receiving data, command and control signals from the memory controller 102. As described above, for one embodiment, the controller interface 107 on the memory controller communicates each segment-by-segment refresh rate value for a given segment to the memory interface 131 using an accompanying Mode Register Write (MRW) command. In response to the MRW command, the segment-by-segment refresh rate value is loaded and stored in the mode register circuit 130.

For some embodiments, the memory device 104 may employ a temperature detection circuit 132, such as a temperature sensor, to operate consistent with temperature compensated self-refresh (TCSR) techniques to facilitate the segment-by-segment non-uniform self-refresh operations described herein. Other embodiments may employ temperature detection circuitry on the memory controller 102. For one embodiment, the global refresh rate for the memory device segments may be established via a TCSR method, where a segment-by-segment non-uniform refresh rate multiplier is stored in the mode register circuit 130 as a segment-by-segment refresh rate value that is selectively applied to the global refresh rate for finer refresh rate control.

In operation, in both the self-refresh and auto-refresh cases, a "segment-by-segment non-uniform refresh" operation is managed by the memory system of FIG. 1, although much of the discussion herein focuses on embodiments that vary the refresh rate on a segment-by-segment basis during self-refresh operations. Typically, auto-refresh occurs during active operation of an electronic device, while self-refresh occurs when the electronic device is in a "sleep" or inactive mode to reduce power consumption. Self-refresh is timed by the DRAM itself independent of the memory controller using, for example, a ring oscillator and a counter to generate row addresses on the chip. The controller triggers the auto-refresh on a command-by-command basis, where each auto-refresh command will instruct the DRAM to refresh one or more rows.

An electronic device utilizing the memory system of fig. 1 typically runs one or more applications for a user. Prior to actual operation, a pre-configuration process will be performed to initialize and optimize the memory system settings of the application. A given application may require different types of data to be loaded into the memory device 104, such as program code and/or bulk data utilized by the application. In some cases, it may be desirable to have a very low error threshold, such as a Bit Error Rate (BER), associated with the program code data to ensure proper program execution. On the other hand, in some cases, bulk data such as image or audio data may be managed at a higher error rate while still enabling acceptable use of the application.

Referring now to FIG. 2, in one embodiment, to manage the classification of different types of data using different acceptable BER parameters, the OS 118 and the application 120 cooperate to classify requested memory, such as BER, during memory allocation according to an acceptable data error threshold at 202, and to mark the requested memory according to the classification at 204. At 206, memory controller 102 receives allocation information from host/processor 114 and generates a physical memory allocation based on the bank and segment addresses. The memory controller also writes mode register bit information for the non-uniform refresh operation into the memory device mode register at 208. The memory controller also issues an auto-refresh command during operation at 210. In one embodiment, the memory controller issues the auto-refresh at the same rate as it would use if non-uniform refresh (NUR) was not used, and in another embodiment, the memory controller uses a different rate for issuing the auto-refresh commands when NUR is used.

FIG. 3 illustrates an exemplary mode register decoder diagram for mode register bits participating in a segment-by-segment refresh operation, according to one embodiment. The diagram is organized into rows (labeled S0-S7) representing eight segments and columns (labeled B0-B7) representing eight banks. Each bank and segment includes a set of mode bits to indicate a refresh parameter value, such as an absolute refresh rate, or a modifier value for modifying a global refresh rate. For one embodiment, the bank/segment bits are set according to the following code:

00: the bank or segment is refreshed at a nominal value (e.g., 64 ms).

01: the refresh of a bank or segment is 2 times longer (128 milliseconds) than the nominal value.

10: the refresh of a bank or segment is 4 times longer (256 milliseconds) than the nominal value.

11: the refresh of a bank or segment is 8 times (ls) longer than the nominal value.

In the case where both the bank and segment bits display code that specifies a refresh rate instead of a nominal rate, the bank code replaces the segment code. Although two-bit encoding is shown and described herein for one particular embodiment, additional bits may be provided to provide even finer granularity. For example, the additional bits may specify additional refresh rates/modifiers and/or specify separate segments.

With further reference to fig. 3, the first part of the figure shows, as an example, a segmentation code "11" for a fifth segment S4 at 302. At 304, the nominal code "00" for bank B0 specifies a refresh rate of 64ms for segments S0-S3 and S5-S7 of bank B0, while the refresh rate for segment S4 is specified as ls at 306. Code 01 for bank B1 replaces code 11 of segment S4 and thus specifies a refresh rate of 128ms (shown at 210) for all eight segments of bank B1. Although fig. 3 shows a decoder graph that specifies an absolute setting of a reference nominal value, the code may alternatively represent a segment-by-segment multiplier factor to apply to global refresh settings, such as settings associated with a temperature-compensated self-refresh scheme (TCSR).

In general, TCSR provides a way to reduce power consumption when a memory device is operating in a self-refresh condition. The temperature detection circuit 132 detects an ambient temperature of the memory device, wherein the global refresh rate change is performed in response to the detected temperature. The increase/decrease in the refresh rate typically compensates for the increased/decreased leakage rate in the volatile memory cells at different temperatures. In such embodiments, temperature detection circuit 132 detects the operating temperature of memory device 104, generates corresponding temperature information, and provides the temperature information to refresh logic 128. The refresh logic may then apply the appropriate global refresh rate setting (stored in mode register circuit 130) based on temperature and apply a segment-by-segment multiplier to the non-uniform refresh rate between segments based on the non-uniform bits stored in the mode register circuit.

In one embodiment, the memory controller issues auto-refresh commands at the same rate as when NURs are not used. When the refresh counter points to a row in a segment with a longer refresh time allocated by the NUR bit in the mode register, refresh logic on the DRAM may periodically skip the execution of a refresh. For example, when the assigned refresh rate for a segment is 128ms and the memory controller issues an auto-refresh command every 64ms, the refresh logic will skip every second refresh for that segment.

At the memory controller, the auto-refresh controller may take the alternative form of segment-by-segment refresh to perform the auto-refresh operation. As described above, auto-refresh typically occurs during active operation of an electronic device. Knowing the error rates acceptable for the different allocated memory regions, the variable segment-by-segment refresh rate can be performed by the auto-refresh controller on the memory controller by, for example, skipping the appropriate segments when issuing the external global refresh command.

The memory systems, devices, and methods described above provide for finer granularity, segment-by-segment non-uniform refresh, which allows for more efficient power savings that can be achieved by the memory system. The embodiments described herein are well suited for mobile device applications where power efficiency is a key concern.

When such data and/or instruction-based expressions of the above-described circuits are received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with the execution of one or more other computer programs, including but not limited to netlist generation programs, layout and routing programs, etc., to generate representations or images of physical representations of such circuits. This representation or image may then be used in device fabrication, for example, by enabling the generation of one or more masks used to form various components of the circuit during device fabrication.

In the foregoing description and in the drawings, specific terminology and reference symbols have been set forth to provide a thorough understanding of the invention. In certain instances, the terms and symbols may imply specific details that are not required to practice the invention. For example, any of the particular number of bits, signal path widths, signaling or operating frequencies, component circuits or devices, etc. may be different from those described above in alternative embodiments. Also, the interconnections between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single-conductor signal links may alternatively be multi-conductor signal links. Signals and signaling paths shown or described as being single-ended may also be differential, and vice versa. Similarly, in alternative embodiments, signals described or depicted as having a high logic level active or a low logic level active may have opposite logic levels. Component circuitry within an integrated circuit device may be implemented using Metal Oxide Semiconductor (MOS) technology, bipolar technology, or any other technology in which logic and analog circuitry may be implemented. With respect to terminology, a signal is said to be "asserted" when it is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Instead, a signal is "deasserted" to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or a floating state such as an open drain or open collector state that may occur when the signal driving circuit transitions to a high impedance state). A signal driving circuit is said to "output" a signal to a signal receiving circuit when the signal driving circuit asserts (or de-asserts if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving circuit and the signal receiving circuit. When the signal is on the signal lineA signal line is said to be "activated" when asserted, and "deactivated" when the signal is de-asserted. Additionally, the prefix "/" appended to the signal name indicates that the signal is an active-low signal (i.e., the asserted state is a logic low state). Transverse lines on the signal names (e.g. for

) And also to indicate an active low signal. The term "coupled" is used herein to mean directly connected as well as connected through one or more intermediate circuits or structures. Integrated circuit device "programming" can include, for example and without limitation, loading control values into registers or other storage circuits within the device in response to host instructions to control operational aspects of the device, to establish a device configuration, or to control operational aspects of the device through one-time programming operations (e.g., blowing fuses within configuration circuits during device production), and/or to connect one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operational aspect of the device. The term "exemplary" is used to mean exemplary, rather than preferences or requirements.