阅读说明：本技术 用于信号解调的方法和装置 (Method and apparatus for signal demodulation ) 是由 亚诺什·拉德万斯基 拜奈代克·科瓦奇 于 2018-03-01 设计创作，主要内容包括：本公开的实施例提供了用于解调接收信号的方法和装置。例如,用于解调输入信号的解调系统被提供。输入信号包括利用从多个候选复数符号值中选择的数据符号调制的载波。系统包括：输入端,用于接收待解调的输入信号；以及载波恢复模块,可操作以补偿载波的载波频率并输出解调的数据信号。载波恢复模块包括：第一复数信号转换模块,可操作以将输入信号转换成复值输入信号；压控振荡器；混合器,用于将压控振荡器的复值输入信号和复值输出信号混合,并生成混合器输出信号；低通滤波器,耦合到混合器、可操作以从混合器输出信号过滤载波频率,并输出与解调的数据信号相对应的信号；以及折叠模块,可操作以将折叠算法应用于低通滤波器的输出信号,以将多个候选复数符号值转换成单个值。根据折叠模块的输出来控制压控振荡器。(Embodiments of the present disclosure provide methods and apparatus for demodulating a received signal. For example, a demodulation system for demodulating an input signal is provided. The input signal includes a carrier modulated with a data symbol selected from a plurality of candidate complex symbol values. The system comprises: an input for receiving an input signal to be demodulated; and a carrier recovery module operable to compensate for a carrier frequency of the carrier and output a demodulated data signal. The carrier recovery module comprises: a first complex signal conversion module operable to convert an input signal into a complex-valued input signal; a voltage controlled oscillator; a mixer for mixing a complex-valued input signal and a complex-valued output signal of the voltage-controlled oscillator and generating a mixer output signal; a low pass filter coupled to the mixer, operable to filter the carrier frequency from the mixer output signal, and output a signal corresponding to the demodulated data signal; and a folding module operable to apply a folding algorithm to the output signal of the low-pass filter to convert the plurality of candidate complex symbol values into a single value. The voltage controlled oscillator is controlled in dependence on the output of the folding module.)

1. A demodulation system (104, 200, 300) for demodulating an input signal, the input signal comprising a carrier modulated with data symbols selected from a plurality of candidate complex symbol values, the system comprising:

an input (202) for receiving the input signal to be demodulated; and

a carrier recovery module operable to compensate for a carrier frequency of the carrier and output a demodulated data signal; and is

Wherein the carrier recovery module comprises:

a first complex signal conversion module (204, 302) operable to convert the input signal into a complex-valued input signal;

a voltage controlled oscillator (208, 314);

a mixer (206, 322) for mixing the complex-valued input signal and a complex-valued output signal of the voltage-controlled oscillator and generating a mixer output signal;

a low pass filter (212, 326, 328) coupled to the mixer, operable to filter the carrier frequency from the mixer output signal and output a signal corresponding to the demodulated data signal; and

a folding module (216, 330-342) operable to apply a folding algorithm to the output signal of the low-pass filter to transform the plurality of candidate complex symbol values into a single value,

wherein the voltage controlled oscillator (208, 314) is controlled in dependence on the output of the folding module.

2. The demodulation system of claim 1, further comprising: an averaging module (218, 344) arranged between the output of the folding module and a control input of the voltage controlled oscillator operable to average the output of the folding module over a limited time window.

3. The demodulation system of claim 1 or 2, wherein the first complex signal conversion module (204) comprises: a first quarter-wave phase shifter (302) operable to shift the phase of the input signal by a quarter-wave, and a first addition module (304) operable to combine the input signal and the phase-shifted input signal.

4. A demodulation system according to claim 3, wherein the quarter-wave phase shifter (302) comprises a hilbert filter or delay block.

5. The demodulation system of claim 3 or 4, wherein the first complex signal conversion module (204) further comprises: a normalization block (306-312) operable to normalize the combined amplitude of the input signal and the phase shifted input signal.

6. A demodulation system as claimed in any preceding claim, further comprising: a second complex signal conversion module (210, 316) operable to convert the output of the voltage controlled oscillator into the complex output signal of the voltage controlled oscillator.

7. The demodulation system of claim 6, wherein the second complex signal conversion module (210) comprises: a second quarter-wave phase shifter (316) operable to shift the phase of the output of the voltage controlled oscillator by a quarter-wave, and a second summing module (320) operable to combine the output of the voltage controlled oscillator and the phase shifted output of the voltage controlled oscillator.

8. Demodulation system according to claim 7, wherein the second quarter-wave phase shifter (316) comprises a Hilbert filter or a delay block.

9. A demodulation system according to claim 7 or 8, when dependent on claim 3, wherein the second quarter wave phase shifter (316) is operable to shift the phase of the output of the voltage controlled oscillator in an opposite direction to the phase shift applied in the first quarter wave phase shifter (302).

10. A demodulation system as claimed in any preceding claim, wherein the folding algorithm comprises one or more successive folds applied to a complex plane in which the plurality of candidate complex symbol values are defined to transform the plurality of candidate complex symbol values into a single value.

11. The demodulation system of claim 10, wherein the folding algorithm further applies one or more shifts to the complex plane.

12. Demodulation system according to any of the preceding claims, wherein the low-pass filter (212, 326, 328) has a cut-off frequency with a value between the modulation frequency of the input signal and twice the carrier frequency.

13. An apparatus (100) comprising:

an interface (102) for receiving a signal to be demodulated; and

the demodulation system (104, 200, 300) of any of the preceding claims.

14. A method for demodulating an input signal comprising a carrier modulated with data symbols selected from a plurality of candidate complex symbol values, the method comprising:

-converting (500) the input signal into a complex valued input signal;

mixing (502) the complex-valued input signal and a complex-valued output signal of a voltage-controlled oscillator, and generating a mixer output signal;

filtering (504) the carrier frequency from the mixer output signal with a low pass filter and outputting a signal corresponding to the demodulated data signal;

applying (506) a folding algorithm to the output signal of the low-pass filter with a folding module to transform the plurality of candidate complex symbol values into a single value; and

controlling (510) the voltage controlled oscillator according to an output of the folding module.

15. The method of claim 14, further comprising averaging (508) the output of the folding module over a limited time window and providing the averaged signal to a control input of the voltage controlled oscillator.

16. The method of claim 14 or 15, wherein converting the input signal into the complex-valued input signal comprises: shifting the phase of the input signal by a quarter wavelength and combining the input signal and the shifted input signal.

17. The method of any of claims 14 to 16, further comprising: converting an output of the voltage controlled oscillator into the complex valued output signal of the voltage controlled oscillator.

18. The method of claim 17, wherein converting the output of the voltage controlled oscillator to the complex valued output signal of the voltage controlled oscillator comprises: shifting the phase of the output of the voltage controlled oscillator by a quarter wavelength and combining the output of the voltage controlled oscillator and the phase shifted output of the voltage controlled oscillator.

19. A method according to claim 18 when dependent on claim 16, wherein the phase of the output of the voltage controlled oscillator is shifted in a direction opposite to the phase of the input signal.

20. The method of any of claims 14 to 19, wherein the folding algorithm comprises one or more successive folds applied to a complex plane in which the plurality of candidate complex symbol values are defined to convert the plurality of candidate complex symbol values to a single value.

21. The method of claim 20, wherein the folding algorithm further applies one or more shifts to the complex plane.

Technical Field

Embodiments of the present disclosure relate to signal demodulation, and in particular, to methods and apparatus for demodulating signals using phase-locked loop based circuits.

Background

Phase Locked Loops (PLLs) are well known circuits that are widely used in modern electronic devices for a variety of purposes. For example, in telecommunications, PLLs are used to demodulate a received signal, i.e. to extract the original information-bearing signal from a carrier wave. In this case, the phase and frequency of the local Voltage Controlled Oscillator (VCO) may be matched to the carrier frequency and phase of the received signal to be demodulated using a PLL.

The basic PLL structure for signal demodulation comprises a frequency mixer, a low pass filter, an oscillator (such as a VCO) and a feedback path. The frequency mixer receives an input signal and an output of the oscillator, and outputs a signal equal to a product of the two signals. If the frequency of the oscillator matches the carrier frequency of the input signal, the output of the frequency mixer will be equal to the information-bearing signal and the high frequency component of twice the carrier frequency. This latter component may then be filtered by a low pass filter in order to recover the information-bearing signal. The information-bearing signal may be integrated or otherwise averaged (e.g., by a loop filter) to provide stability to the loop response, and then fed back via a feedback path to control the oscillator.

Various modifications to this basic structure have been proposed. One known modification is called the Costas loop proposed by John Costas in the 50's of the 20 th century.

The costas loop differs from a conventional PLL in that the VCO provides quadrature outputs, i.e., two signals that differ in phase by pi/2. These respective quadrature outputs are provided to respective mixers, where they are each mixed with the input signal before being low-pass filtered. These filtered signals are combined in another mixer before being used to control the VCO. Thus, the costas loop comprises two independent branches: one for each of the quadrature outputs of the VCO.

One advantage of the costas loop over a conventional PLL is that at small deviations the error voltage of the costas loop varies with variations in sin (2 Δ θ) compared to sin (Δ θ), where Δ θ is the phase difference between the input signal and the oscillator output signal. Thus, the costas loop is more sensitive to frequency variations than a conventional PLL. However, in the presence of noise, the loop also faces relatively high symbol error rates. An alternative circuit that results in a lower symbol error rate would be beneficial.

Disclosure of Invention

Embodiments of the present disclosure seek to address these and other problems.

In one aspect, a demodulation system for demodulating an input signal is provided. The input signal includes a carrier modulated with a data symbol selected from a plurality of candidate complex symbol values. The system comprises: an input for receiving an input signal to be demodulated; and a carrier recovery module operable to compensate for a carrier frequency of the carrier and output a demodulated data signal. The carrier recovery module comprises: a first complex signal conversion module operable to convert an input signal into a complex-valued input signal; a voltage controlled oscillator; a mixer for mixing a complex-valued input signal and a complex-valued output signal of the voltage-controlled oscillator and generating a mixer output signal; a low pass filter coupled to the mixer, operable to filter the carrier frequency from the mixer output signal and output a signal corresponding to the demodulated data signal; and a folding module operable to apply a folding algorithm to the output signal of the low-pass filter to transform the plurality of candidate complex symbol values into a single value. The voltage controlled oscillator is controlled in dependence on the output of the folding module.

In another aspect, an apparatus is provided, comprising: an interface for receiving a signal to be demodulated; and a demodulation system as set out above.

Yet another aspect provides a method for demodulating an input signal. The input signal includes a carrier modulated with a data symbol selected from a plurality of candidate complex symbol values. The method comprises the following steps: converting the input signal into a complex-valued input signal; mixing a complex value input signal and a complex value output signal of a voltage-controlled oscillator and generating a mixer output signal; filtering the carrier frequency from the mixer output signal with a low pass filter and outputting a signal corresponding to the demodulated data signal; applying a folding algorithm to the output signal of the low-pass filter using a folding module to transform the plurality of candidate complex symbol values into a single value; and controls the voltage controlled oscillator according to the output of the folding module.

Accordingly, embodiments of the present disclosure provide a method and apparatus for demodulating a received signal that is robust to noise and achieves an excellent symbol error rate.

Drawings

For a better understanding of examples of the present disclosure, and to show more clearly how the examples may be carried into effect, reference will now be made, by way of example only, to the accompanying drawings in which:

fig. 1 is a schematic diagram of an apparatus according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a demodulation system according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of a demodulation system according to a further embodiment of the present disclosure;

4 a-4 g illustrate a folding algorithm according to an embodiment of the present disclosure; and

fig. 5 is a flow chart of a method according to an embodiment of the present disclosure.

Detailed Description

Specific details are set forth below, such as particular embodiments for purposes of explanation and not limitation. However, it will be understood by those skilled in the art that other embodiments may be employed apart from these specific details. In certain instances, detailed descriptions of well-known methods, nodes, interfaces, circuits, and devices are omitted so as not to obscure the description with unnecessary detail. Those skilled in the art will appreciate that the functions described may be implemented in one or more nodes using hardware circuitry (e.g., analog and/or discrete logic gates interconnected to perform a specialized function, ASICs, PLAs, etc.) and/or software programs and data used in conjunction with one or more digital microprocessors or general purpose computers, which are particularly adapted to perform the processes disclosed herein based on the execution of such programs. Moreover, the techniques may also be considered to be embodied entirely within any form of computer readable memory (e.g., solid-state memory, magnetic or optical disk containing an appropriate set of computer instructions that would cause a processor to perform the techniques described herein).

Hardware implementations may include or encompass, but are not limited to, Digital Signal Processor (DSP) hardware, reduced instruction set processors, hardware (e.g., digital or analog) circuits including, but not limited to, Application Specific Integrated Circuits (ASICs) and/or Field Programmable Gate Arrays (FPGAs), and state machines capable of performing such functions, where appropriate.

In terms of computer implementation, a computer is generally understood to include one or more processors, one or more processing modules, or one or more controllers, and the terms computer, processor, processing module, and controller may be used interchangeably. When provided by a computer, processor, or controller, the functions may be provided by a single dedicated computer or processor or controller, by a single shared computer or processor or controller, or by a plurality of individual computers or processors or controllers, some of which may be shared or distributed. Furthermore, the terms "processor" or "controller" also refer to other hardware capable of performing such functions and/or executing software, such as the example hardware set forth above.

Fig. 1 shows an apparatus 100 according to an embodiment of the present disclosure. In the illustrated embodiment, the apparatus 100 includes a wireless receiver operable to receive radio frequency signals transmitted by a radio frequency transmitter (not shown). Thus, in this case, the apparatus 100 may be implemented in a wireless device such as a mobile terminal device or user equipment or in a network node such as a base station, transmission point, eNodeB, gdnodeb or any equivalent node for a wireless communication network. The wireless transmitter may implement any wireless radio protocol; the present disclosure is not limited in this respect.

The apparatus 100 includes one or more antennas 102, a demodulation system 104, and processing circuitry 106. The one or more antennas 102 are operable to detect radio frequency signals transmitted by one or more radio frequency transmitters and deliver the radio frequency energy to the demodulation system 104 for demodulation.

Those skilled in the art will appreciate that a signal typically comprises a carrier wave modulated with an information-bearing signal. One well-known modulation technique is known as Quadrature Amplitude Modulation (QAM). According to this technique, data is transmitted in two digital bit streams by modulating the amplitude of two orthogonal components of a carrier wave (i.e., two components having the same carrier frequency and being out of phase by π/2). The in-phase component is referred to as the I component; the quadrature component is referred to as the Q component. The most common QAM scheme is square, with candidate symbol values distributed in a square grid pattern in the IQ plane. Higher order modulation schemes utilize a greater number of candidate symbol values in the trellis. For example, 16QAM, 64QAM, and 256QAM are commonly used for wireless communication. In one example, the signal may be modulated with only two bits (i.e., 4-QAM) or Quadrature Phase Shift Keying (QPSK). Higher order modulation schemes may be used for wireline applications where lower noise may be expected.

The demodulation system 104 acts on the radio frequency energy to recover the information-bearing signal from the modulated carrier wave. Further details regarding this aspect will be provided below with respect to fig. 2 and 3. The information-bearing signal is then passed from the demodulation system 104 to the processing circuitry 106 where it can be stored and/or acted upon as desired. Alternatively, the radio frequency energy may be mixed to a lower intermediate frequency prior to demodulation in the demodulation system.

Thus, fig. 1 shows an apparatus 100 in which a demodulation system 104 according to an embodiment of the present disclosure is used to demodulate wirelessly received signals. However, embodiments of the present disclosure are not limited to demodulation of wireless or radio signals. Rather, the concepts disclosed herein may be used to demodulate any modulated signal, particularly those modulated using QAM. Thus, in general, the apparatus 100 may comprise any suitable interface for receiving signals according to any transport mechanism. The interface may alternatively be wired, operable to receive an electronic signal, or electro-optical and operable to receive an optical signal.

Fig. 2 illustrates a demodulation system 200 according to an embodiment of the disclosure. For example, the demodulation system 200 may operate as the demodulation system 104 described above with respect to fig. 1.

The system 200 comprises an input 202 receiving an input signal to be demodulated. As mentioned above, the input signal typically comprises a carrier wave which is quadrature amplitude modulated with the information-bearing signal. The plurality of candidate symbol values in the input signal are arranged in a complex IQ plane and may be distributed in, for example, a grid pattern. The signal may be conveyed by any conveyance means, such as wireless, wired, or optical.

The remaining features of the demodulation system 200 shown in fig. 2 form a carrier recovery module that is operable to compensate for the carrier frequency of the carrier and output a demodulated data signal corresponding to the information-bearing signal used to modularize the carrier. As will be seen from the following description, the carrier recovery module is based on a phase locked loop.

The input signal received at input 202 is a single real-valued signal. According to an embodiment of the present disclosure, the real-valued signal is converted into a complex-valued signal by the first complex signal conversion module 204. There are various methods for converting a real-valued signal to a complex-valued signal. For example, the input signal may be phase shifted by π/2 (to generate the quadrature component) and then added to the original version to recover a complex-valued signal. If this method is followed, the resulting signal will have a larger amplitude than the original input signal. Normalization may be used to restore the original amplitude. The phase shift may be implemented in a number of different ways. For example, a Hilbert filter may be used to apply a phase shift of π/2 to all Fourier components of the signal. In a narrow-band approximation, the phase shift may be achieved by a T/4 delay (where T is the period of the carrier).

The complex-valued input signal (i.e., the output of the first complex signal conversion module 204) is passed to a phase detector or mixer 206. The mixer 206 also receives the output of a Voltage Controlled Oscillator (VCO) 208.

VCO 208 is controlled by the action of the phase locked loop and will be described in further detail below. As with the input signal, in the illustrated embodiment, the output of VCO 208 is a real value. The real-valued signal is passed to a second complex signal conversion module 210, the second complex signal conversion module 210 operable to convert the real-valued output of the VCO 208 into a complex-valued signal. The second complex signal conversion module 210 may operate in a substantially similar manner as the first complex signal conversion module 204. For example, the output signal of the VCO 208 may be phase shifted by pi/2 (to generate the quadrature component) and then added to the original version to recover the complex-valued signal. The phase shift may be implemented in a number of different ways. For example, a Hilbert filter may be used to apply a phase shift of π/2 to all Fourier components of the signal. In a narrow-band approximation, the phase shift may be achieved by a T/4 delay (where T is the period of the carrier).

According to an embodiment of the present disclosure, the phase shift implemented by the second complex signal conversion module 210 is in the opposite direction as the phase shift implemented by the first complex signal conversion module 204.

The second complex signal conversion module 210 may or may not have a normalization function to recover the original amplitude of the output signal of the VCO 208. In the latter case, for example, the normalization function may be avoided by controlling VCO 208 to output a signal having a lower amplitude than would be required without the complex signal conversion. For example, if the phase shift and combining process described above increases the amplitude by the square root of 2, the amplitude of the VCO signal may be divided by the square root of 2. It should also be understood that exact equivalence between the amplitudes of the input signal and the VCO signal is not necessary for the operation of the demodulation system 200 and the locking of the phase locked loop.

Thus, the mixer 206 receives a complex-valued input signal from the module 204 and also receives a complex-valued VCO output signal from the module 210. The mixer 206 may be implemented as a product detector operable to multiply two signals. In this case, particularly in steady state, once the output of VCO 208 is locked in phase and frequency with the carrier frequency of the input signal, the output of mixer 206 includes two components: equal to the component of the information-bearing signal (possibly with a DC offset); and a component with a frequency equal to twice the carrier frequency. When the VCO signal is phase shifted in the opposite direction to the input signal, the output of the mixer 206 is an upright (i.e., non-rotating) signal. In this manner, the demodulation system 200 is robust to noise.

The output signal is passed to a low pass filter 212, which low pass filter 212 is used to filter the high frequency components, thus removing the carrier from the signal and recovering the information-bearing signal (i.e., the demodulated data signal). For example, a low pass filter may achieve a cut-off frequency between the modulation frequency and twice the carrier frequency.

Therefore, the low-pass filter 212 outputs a signal equal to the demodulated data signal. The signal is provided as an output signal 214 of the demodulation system 200 (e.g., to the processing circuit 106).

The demodulated data signal is also used in a phase locked loop to control the VCO 208. Thus, in accordance with an embodiment of the present disclosure, the demodulated data signal is passed to a folding module 216, which folding module 216 is operable to apply a folding algorithm to the signal.

The folding algorithm is operable to apply one or more successive folds and/or one or more successive shifts to the complex plane of the signal to transform all possible candidate symbol values of the demodulated signal into a single value. The algorithm will be described in more detail with respect to fig. 3 and 4. However, by changing the signal so that all candidate symbol values have the same single value, the data component of the demodulated signal can be effectively removed. Thus, the output of the folding module 216 is a signal in which both the carrier and the information (through the action of the low pass filter 212) are removed. Therefore, the output should be small and equivalent to the instantaneous difference in the frequency of the VCO output signal and the carrier frequency of the input signal.

By effectively removing information from the demodulated data signal using a folding algorithm, the system 200 averages out noise. That is, each constellation point or candidate symbol value has its own contribution to the overall noise. These respective noise contributions can be summed and averaged (reduced) by folding the constellation diagram to superimpose all candidate symbol values at the same value. Thus, the folding algorithm is particularly robust to noise.

This signal can be used directly in a feedback loop to control the VCO in order to change its frequency and attempt to correct for this frequency difference. However, such cycling may be unstable. Thus, in the illustrated embodiment, the output of the collapse module 216 is passed to an averaging module 218, which averaging module 218 is operable to average the output of the collapse module 216 over a limited period of time or window. The averaging module 216 may be implemented as a low pass filter or other loop filter. This averaged signal (output of averaging module 218) may then be used to control VCO 208. The control of the VCO 208 is more stable since the output of the averaging module 218 can be expected to change less quickly than the output of the folding module 216.

The above described demodulation system 200 achieves a very low symbol error rate even in the presence of significant noise due to the use of complex-valued signals and folding algorithms to remove data components from the demodulated data signal. Based on simulations, the error rate is shown to be equal to 0.01 at-5 dB signal-to-noise ratio (i.e., one error per 100 bits).

Fig. 3 illustrates a demodulation system 300 according to further embodiments of the present disclosure. The demodulation system 300 is similar to the demodulation system 200 described above with respect to fig. 2, but provides further details regarding the operation of each module.

Therefore, the input signal is transmitted to the first complex signal conversion module. In the illustrated embodiment, the first complex signal conversion module includes a quarter wave phase shift element 302, the quarter wave phase shift element 302 phase shifting the input signal by pi/2. In the illustration, the phase shifting element is implemented with a delay line 302 that provides a delay equal to T/4 (where T is the period of the carrier wave). Alternatively, the phase shift section 302 may be implemented with a hilbert filter. The output of the phase shift component is provided to a combining module 304, which combining module 304 combines with the original input signal to generate a complex valued signal.

However, this signal will have a larger amplitude than the original input signal, and so in the illustrated embodiment, a normalization process is applied to restore the original amplitude. The normalization module 306 determines the square of the absolute value of the complex-valued signal, and the square root module 308 determines the square root of the value. The (real-valued) square root is converted to a complex value at a real-to-complex block 310 before passing to a division block 312, which division block 312 divides the output of the combination block 304 by the output of the real-to-complex block 310. Thus, the output of the division module 312 is a normalized complex-valued version of the input signal.

The demodulation system further includes a VCO 314, the VCO 314 being controlled to output an oscillation signal at a specific frequency. In a steady state, the quiescent frequency of the VCO is equal to the carrier frequency of the input signal when the feedback loop is locked to the frequency of the input signal.

The oscillating signal is passed to a second complex signal conversion module operable to convert the oscillating signal to a complex-valued signal. The second complex signal conversion block comprises a quarter-wave phase shift component 316, the quarter-wave phase shift component 316 phase shifting the VCO output signal by pi/2. In the illustrated embodiment, the phase shift component is implemented with a delay line 316, the delay line 316 providing a delay equal to T/4 (where T is the period of the carrier wave). Alternatively, the phase shift section 316 may be implemented with a hilbert filter. The output of the phase shift component is provided to a scaling module 318, which scaling module 318 changes the sign of the quadrature component (e.g., by effecting a multiplication by-1) such that the rotation applied by the second complex signal conversion module is in the opposite direction to the rotation applied by the first complex signal conversion module. The output of the scaling module 318 and the VCO output signal are provided to a combiner 320, which combiner 320 generates a complex-valued signal, wherein the VCO output signal is an in-phase component and the output of the scaling module 318 is a quadrature component.

The complex-valued signal outputs from the division module 312 and the combination module 320 are provided to a mixer 322, which mixer 322 is implemented in the illustrated embodiment as a complex product detector operable to multiply the two complex-valued signals together. The product signal is provided to a conversion module 324, which conversion module 324 outputs individual signals corresponding to the real and imaginary (I and Q) components of the product signal. These signals are provided to respective low pass filters 326 and 328, which low pass filters 326 and 328 filter the high frequency fourier components from each signal (corresponding to the carrier). For example, low pass filter 326 and low pass filter 328 may implement a cutoff frequency between the modulation frequency and twice the carrier frequency. The outputs of these low pass filters 326 and 328 correspond to the demodulated I and Q data components, the information-bearing component of the input signal, and are output from the demodulation system 300 (e.g., to the processing circuit 106).

As described above, the demodulated data signal is also subjected to a folding algorithm to convert all possible candidate symbol values into a single value. In the illustrated embodiment, the input signal is modulated with 4 QAM. Thus, the folding module is operable to implement two folds with respect to the I and Q axes to convert all four candidate symbol values to a single value. One or more shifts are also applied such that a single value equals zero. In higher order modulation schemes such as 16-QAM or higher, one or more shifts are also required between folding in order to transform all possible candidate symbol values into a single value. This aspect is illustrated in fig. 4 below.

The in-phase component output from the low pass filter 326 is passed to an absolute module 330, which absolute module 330 determines the absolute value of the component (thus achieving folding with respect to the I axis), and then shifts in a summing module 332. When the loop is fully locked to the carrier frequency, the output of the summing module 332 should be equal to zero regardless of the actual value of the I component in the demodulated data signal. Similar processing is performed on the Q component by respective absolute modules 336 and respective addition modules 338. The outputs of the summing modules 332, 338 are provided to a combining module 334, which combining module 334 converts the outputs to a complex-valued output signal.

The amplitude module 340 determines the amplitude of the complex-valued signal and the amplitude is further shifted in the addition module 342 so that the new constellation (after folding is achieved in modules 330 to 338) is symmetrical with respect to the origin.

Thus, the output of the summing module 342 is equivalent to the instantaneous difference in the frequency of the VCO output signal and the carrier frequency of the input signal. This signal can be used directly in a feedback loop to control the VCO 314 in order to change its frequency and attempt to correct for this frequency difference. However, as mentioned above, such a loop may be unstable.

In the illustrated embodiment, the output of the summing module 342 is averaged over a finite time window by the action of the modules 344 through 348. The output of the summing module 342 is passed to an integration module 344, which integration module 344 sums successive values of the signal to create an integrated value. This value is fed to the difference block 348 along with the version of the signal delayed by the delay block 346. The difference module 348 determines the difference between the two signals, providing an average of the outputs of the addition module 342. In the illustrated embodiment, the average value is scaled by a scaling factor in the scaling module 350 and delayed in the delay block 352 before being used as the control input voltage for the VCO 314. By delaying the signal with delay block 352, computational deadlocks may be avoided.

In a stable or locked state, the VCO input signal is a small constant value corresponding to the difference between the actual and ideal quiescent frequencies of the VCO 314.

The circuits described above with respect to fig. 2 and 3 illustrate the transmission of complex signals through a single electrical connection multiple times. In alternative embodiments, any of these complex signals may be transmitted over separate electrical connections for the real and imaginary components.

The example of fig. 3 shows demodulation of a QPSK or 4QAM signal, where the folding algorithm includes two folds (with respect to the I and Q axes) and corresponding shifts to bring the total value to zero. Those skilled in the art will appreciate that the folding algorithm may be applied to any square or rectangular QAM scheme. Fig. 4a to 4g show successive steps in one example of a folding algorithm applied to a 16QAM signal.

Fig. 4a shows a 16QAM constellation, where 16 candidate symbol values are distributed in a grid pattern on the IQ complex plane.

Fig. 4b shows the application of the first folding to the constellation diagram with respect to the I-axis. Thus, 8 candidate symbol values with negative Q values are superimposed on 8 candidate symbol values with positive Q values.

Fig. 4c shows the application of a second fold relative to the Q-axis. The remaining 4 candidate symbol values with negative I values are superimposed on the 4 candidate symbol values with positive I values.

Fig. 4d shows the application of a shift in the I and Q axes to center the remaining candidate symbol values with respect to the origin.

Fig. 4e shows the application of a third fold in relation to the I axis. Thus, two remaining candidate symbol values with negative Q values are superimposed on two candidate symbol values with positive Q values.

Fig. 4f shows the application of a fourth fold relative to the Q-axis. The remaining candidate symbol values with negative I values are superimposed on the remaining candidate symbol values with positive I values.

Fig. 4g shows the application of a second shift in the I and Q axes to center a single remaining candidate symbol value about the origin.

Such an algorithm can be implemented directly using absolute and additive blocks, as shown in 4-QAM in figure 3 above. Those skilled in the art will also appreciate that the order of the transformations shown in fig. 4 a-4 g may be changed without substantially affecting the overall algorithm, while alternative transformations may also be applied without substantially affecting the overall algorithm.

Fig. 5 is a flow chart of a method according to an embodiment of the present disclosure. For example, the method may be implemented in a circuit such as described above with respect to fig. 2 and 3.

The method starts in step 500 with the input signal being converted to a complex valued input signal in step 500. This may be performed, for example, using the first complex signal conversion module 204 or a combination of the above-described modules 302 to 312. Thus, a quarter-wave phase shift may be applied to the input signal before it is combined with its phase-shifted version. The combined signal may be normalized.

In step 502, the complex-valued input signal generated in step 500 is mixed with a complex-valued VCO output signal. The complex-valued VCO output signal may be generated as described above with respect to the second complex signal conversion module 210 or the combination of modules 316 to 320. Thus, a quarter-wavelength phase shift of 2 may be applied to the VCO output signal (in the opposite direction to that applied to the input signal in step 500) before the VCO output signal is combined with its phase-shifted version. The step of mixing may be performed by the mixer 206 or 322 described above.

In step 504, the mixer output signal generated in step 502 is filtered in a low pass filter (e.g., any of filters 212, 326, or 328 described above) to remove the high frequency carrier and leave only the demodulated data signal. The demodulated data signal may be provided as an output of the method.

The demodulated data signal is also subjected to a folding algorithm to convert a plurality of candidate complex symbol values associated with the input signal into a single value in step 506. The folding algorithm may also implement one or more shifts to reduce a single value to zero, and/or account for 16QAM and higher order modulation schemes. This step may be performed by the folding module 216 or a combination of the modules 330 to 342 described above.

In step 508, the output of the folding algorithm (which effectively removes data and carriers) is averaged over a finite period of time, or otherwise low pass filtered. This step may be performed by the averaging module 218 or a combination of the above modules 344 through 348.

In step 510, the VCO is controlled using the averaged signal output from step 508.

Accordingly, embodiments of the present disclosure provide apparatus and methods for demodulating an input signal. The apparatus and method comprises the steps of: the input signal is converted to a complex-valued signal before being mixed with the VCO output signal and a folding algorithm is applied to the demodulated data signal for use as feedback for controlling the VCO. By utilizing these two steps, embodiments of the present disclosure achieve an abnormal symbol error rate even in the presence of significant noise.

It should be understood that the detailed examples summarized above are only examples. In accordance with embodiments of the present disclosure, the steps of the method described in fig. 5 may be presented in a different order than that described herein. Furthermore, additional steps not explicitly recited above may be incorporated into the method. Additional circuits and modules may be incorporated in the apparatus shown in fig. 1 and the circuits shown in fig. 2 and 3.