Memory system capable of reducing read time
阅读说明:本技术 能够减少读取时间的存储系统 (Memory system capable of reducing read time ) 是由 陈纬荣 汤强 于 2019-04-30 设计创作,主要内容包括:一种偏置电路包括充电电流再现单元、单元电流再现单元、电流比较器以及位线偏置发生器。所述充电电流再现单元根据流经电压偏置晶体管的充电电流来生成充电参考电压。所述单元电流再现单元根据流经共源晶体管的单元电流来生成单元参考电压。所述电流比较器包括用于根据所述充电参考电压生成复制充电电流的第一电流发生器以及用于根据所述单元参考电压生成复制单元电流的第二电流发生器。所述位线偏置发生器根据所述复制充电电流和所述复制单元电流之间的差异生成位线偏置电压,以控制页缓冲器对位线进行充电。(A bias circuit includes a charge current reproducing unit, a cell current reproducing unit, a current comparator, and a bit line bias generator. The charging current reproducing unit generates a charging reference voltage according to a charging current flowing through a voltage bias transistor. The cell current reproduction unit generates a cell reference voltage according to a cell current flowing through the common-source transistor. The current comparator includes a first current generator for generating a replica charging current from the charging reference voltage and a second current generator for generating a replica cell current from the cell reference voltage. The bit line bias generator generates a bit line bias voltage according to a difference between the replica charge current and the replica cell current to control a page buffer to charge a bit line.)
1. A storage system, comprising:
a plurality of first memory cells coupled to a first bit line;
a voltage bias transistor having a first terminal configured to receive a first system voltage, a second terminal, and a control terminal;
a first page buffer coupled to the first bit line and the second terminal of the voltage bias transistor;
a common-source transistor having a first terminal coupled to the first bit line, a second terminal configured to receive a second system voltage, and a control terminal; and
a bias circuit, the bias circuit comprising:
a charging current reproduction unit coupled to the voltage bias transistor and configured to generate a charging reference voltage according to a charging current flowing through the voltage bias transistor;
a cell current reproduction unit coupled to the common-source transistor and configured to generate a cell reference voltage according to a cell current flowing through the common-source transistor;
a current comparator coupled to the charging current reproduction unit and the cell current reproduction unit; and
a bit line bias generator coupled to the current comparator and the first page buffer and configured to generate and adjust a bit line bias voltage according to a charge state of the first bit line.
2. The memory system of claim 1, wherein the current comparator comprises:
a first current generator configured to generate a first replica charging current from the charging reference voltage; and
a second current generator configured to generate a first replica cell current from the cell reference voltage.
3. The memory system of claim 2, wherein the bit line bias generator is configured to detect the charge state of the first bit line by a difference between the first replica charge current and the first replica cell current.
4. The storage system of claim 2, wherein:
the bit line bias generator increases the bit line bias voltage when the first replica charge current is greater than the first replica cell current; and is
The bit line bias generator maintains the bit line bias voltage when the first replica charge current is substantially equal to the first replica cell current.
5. The memory system according to claim 1, wherein the first page buffer comprises:
a first transistor having a first terminal coupled to the second terminal of the voltage bias transistor, a second terminal, and a control terminal configured to receive a precharge control signal;
a second transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal, and a control terminal configured to receive a clamping control signal;
a third transistor having a first terminal coupled to the second terminal of the second transistor, a second terminal coupled to the first bit line, and a control terminal configured to receive the bit line bias voltage;
a fourth transistor having a first terminal coupled to the second terminal of the second transistor, a second terminal coupled to a sense amplifier, and a control terminal configured to receive a sense control signal; and
a fifth transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the second terminal of the fourth transistor, and a control terminal configured to receive a precharge select signal.
6. The storage system according to claim 1, wherein the charging current reproducing unit includes:
a sixth transistor having a first terminal configured to receive the first system voltage, a second terminal, and a control terminal coupled to the control terminal of the voltage bias transistor;
a first operational amplifier having a positive input terminal coupled to the second terminal of the sixth transistor, a negative input terminal coupled to the second terminal of the voltage bias transistor, and an output terminal configured to output the charging reference voltage; and
a seventh transistor having a first terminal coupled to the second terminal of the sixth transistor, a second terminal configured to receive the second system voltage, and a control terminal coupled to the output terminal of the first operational amplifier.
7. The memory system according to claim 6, wherein the cell current reproduction unit includes:
an eighth transistor having a first terminal configured to receive the first system voltage, a second terminal, and a control terminal;
a second operational amplifier having a positive input terminal coupled to the second terminal of the eighth transistor, a negative input terminal coupled to the first bit line, and an output terminal coupled to the control terminal of the eighth transistor and configured to output the cell reference voltage; and
a ninth transistor having a first terminal coupled to the second terminal of the eighth transistor, a second terminal configured to receive the second system voltage, and a control terminal coupled to the control terminal of the common-source transistor.
8. The storage system of claim 7, wherein:
the first current generator comprises a tenth transistor having a first terminal, a second terminal configured to receive the second system voltage, and a control terminal configured to receive the charging reference voltage; and is
The second current generator includes an eleventh transistor having a first terminal configured to receive the first system voltage, a second terminal coupled to the first terminal of the tenth transistor, and a control terminal configured to receive the cell reference voltage.
9. The storage system of claim 8, wherein:
the tenth transistor and the seventh transistor are N-type transistors; and is
The eleventh transistor and the eighth transistor are P-type transistors.
10. The memory system of claim 8, wherein the bit line bias generator comprises:
a third operational amplifier having a positive input terminal configured to receive a second bias voltage, a negative input terminal coupled to the first terminal of the tenth transistor, and an output terminal configured to output the bit line bias voltage;
a twelfth transistor having a first terminal coupled to the output terminal of the third operational amplifier, a second terminal coupled to the negative input terminal of the third operational amplifier, and a control terminal coupled to the first terminal of the twelfth transistor; and
a resistor having a first terminal coupled to the second terminal of the twelfth transistor and a second terminal configured to receive the second system voltage.
11. The memory system of claim 2, wherein the current comparator further comprises:
a third current generator configured to generate a second replica charging current from the charging reference voltage;
a fourth current generator configured to generate a second replica cell current from the cell reference voltage; and
an inverter having input terminals coupled to the third and fourth current generators and an output terminal configured to output a sense indication signal according to a difference between the second replica charging current and the second replica cell current.
12. The storage system of claim 1, further comprising:
a plurality of second memory cells coupled to a second bit line; and
a second page buffer coupled to the second bit line, the second terminal of the voltage bias transistor, the first terminal of the common source transistor, and the bit line bias generator.
13. A bias circuit, comprising:
a charging current reproduction unit configured to be coupled to a voltage bias transistor and generate a charging reference voltage according to a charging current flowing through the voltage bias transistor;
a cell current reproduction unit configured to be coupled to a common-source transistor and generate a cell reference voltage according to a cell current flowing through the common-source transistor;
a current comparator coupled to the charging current reproduction unit and the cell current reproduction unit, the current comparator comprising:
a bit line bias generator coupled to the current comparator and configured to be coupled to a page buffer and to generate and adjust a bit line bias voltage according to a charging state of a bit line to control the page buffer to charge the bit line.
14. The bias circuit of claim 13, wherein the current comparator comprises:
a first current generator configured to generate a first replica charging current from the charging reference voltage; and
a second current generator configured to generate a first replica cell current from the cell reference voltage.
15. The biasing circuit of claim 14, wherein the bit line bias generator is configured to detect the charge state of the bit line by a difference between the first replica charge current and the first replica cell current.
16. The bias circuit of claim 14, wherein:
the bit line bias generator increases the bit line bias voltage when the first replica charge current is greater than the first replica cell current; and is
The bit line bias generator maintains the bit line bias voltage when the first replica charge current is substantially equal to the first replica cell current.
17. The bias circuit according to claim 13, wherein the charging current reproducing unit comprises:
a first transistor having a first terminal configured to receive a first system voltage, a second terminal, and a control terminal coupled to the control terminal of the voltage bias transistor;
a first operational amplifier having a positive input terminal coupled to the second terminal of the first transistor, a negative input terminal coupled to the second terminal of the voltage bias transistor, and an output terminal configured to output the charging reference voltage; and
a second transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal configured to receive a second system voltage, and a control terminal coupled to the output terminal of the first operational amplifier.
18. The bias circuit of claim 17, wherein the cell current reproducing unit comprises:
a third transistor having a first terminal configured to receive the first system voltage, a second terminal, and a control terminal;
a second operational amplifier having a positive input terminal coupled to the second terminal of the third transistor, a negative input terminal coupled to the bit line, and an output terminal coupled to the control terminal of the third transistor and configured to output the cell reference voltage; and
a fourth transistor having a first terminal coupled to the second terminal of the third transistor, a second terminal configured to receive the second system voltage, and a control terminal coupled to the control terminal of the common-source transistor.
19. The bias circuit of claim 18, wherein:
the first current generator comprises a fifth transistor having a first terminal, a second terminal configured to receive the second system voltage, and a control terminal configured to receive the charging reference voltage; and is
The second current generator includes a sixth transistor having a first terminal configured to receive the first system voltage, a second terminal coupled to the first terminal of the fifth transistor, and a control terminal configured to receive the cell reference voltage.
20. The bias circuit of claim 19, wherein:
the fifth transistor and the second transistor are N-type transistors; and is
The sixth transistor and the third transistor are P-type transistors.
21. The bias circuit of claim 20 wherein the bit line bias generator comprises:
a third operational amplifier having a positive input terminal configured to receive a second bias voltage, a negative input terminal coupled to the first terminal of the fifth transistor, and an output terminal configured to output the bit line bias voltage;
a seventh transistor having a first terminal coupled to the output terminal of the third operational amplifier, a second terminal coupled to the negative input terminal of the third operational amplifier, and a control terminal coupled to the first terminal of the seventh transistor; and
a resistor having a first terminal coupled to the second terminal of the seventh transistor and a second terminal configured to receive the second system voltage.
22. The biasing circuit of claim 14, wherein the current comparator further comprises:
a third current generator configured to generate a second replica charging current from the charging reference voltage;
a fourth current generator configured to generate a second replica cell current from the cell reference voltage; and
an inverter having input terminals coupled to the third and fourth current generators and an output terminal configured to output a sense indication signal according to a difference between the second replica charging current and the second replica cell current.
Technical Field
The present invention relates to a memory system, and more particularly, to a memory system capable of reducing a read time.
Background
In a memory system, data stored in a memory cell is typically read by sensing a data voltage on a bit line caused by the memory cell. For example, in a NAND memory read sequence, to read data stored in a memory cell, a bit line coupled to the memory cell may first be precharged to a predetermined level. After the voltage of the bit line has been established, the word line coupled to the memory cell may be raised to cause the memory cell to generate a current in accordance with the data stored in the memory cell. If the memory cell has not been programmed, the memory cell may generate a significant current that causes the voltage of the bit line to be pulled down. Otherwise, if the memory cell has been programmed, the memory cell will not generate any current or will only generate a negligible current, so that the voltage of the bit line will remain at a similar level. Accordingly, by sensing the voltage of the bit line, data stored in the memory cell can be read.
However, the setup time of the bit line will be a large fraction of the total read time, since the bit line is resistive and capacitive due to unavoidable parasitic resistors and capacitors. Furthermore, because the resistance and capacitance characteristics are unpredictable and process-dependent, the set-up times required for different memory cells are also different. Therefore, a worst-case settling time is always applied to ensure sensing accuracy. In addition, in the related art, the bit line is precharged using a master-slave transistor controlled by a predetermined voltage. In this case, as the voltage of the bit line approaches the desired level, the charging capability may decrease, which also increases the read time.
Disclosure of Invention
One embodiment of the invention discloses a storage system. The memory system includes a plurality of memory cells, a voltage bias transistor, a page buffer, a common source transistor, and a bias circuit.
The first memory cell is coupled to a bit line. The voltage bias transistor has a first terminal for receiving a first system voltage, a second terminal, and a control terminal for receiving a first bias voltage.
The page buffer is coupled to the bit line and a second terminal of the voltage bias transistor. The page buffer charges a first bit line to a first system voltage according to a bit line bias voltage during a precharge operation, and forms a sensing path from the first bit line to a sense amplifier during a sensing operation.
The common-source transistor has a first terminal coupled to the first bit line, a second terminal for receiving a second system voltage less than the first system voltage, and a control terminal for receiving a control signal.
The bias circuit includes a charging current reproducing unit, a cell current reproducing unit, a current comparator, and a bit line bias generator. The charging current reproduction unit is coupled to the voltage bias transistor. The charging current reproducing unit generates a charging reference voltage according to a charging current flowing through the voltage bias transistor. The cell current reproduction unit is coupled to the common source transistor. The unit current reproduction unit generates a unit reference voltage according to a unit current flowing through the common source transistor.
The current comparator is coupled to the charging current reproduction unit and the cell current reproduction unit. The current comparator includes a first current generator and a second current generator. The first current generator generates a replica charging current according to the charging reference voltage, and the second current generator generates a replica cell current according to the cell reference voltage.
The bit line bias generator is coupled to the current comparator and the first page buffer. The bit line bias generator generates the bit line bias voltage according to a difference between a first replica charge current and a first replica cell current.
Another embodiment of the invention discloses a bias circuit. The bias circuit includes a charging current reproducing unit, a cell current reproducing unit, a current comparator, and a bit line bias generator.
The charging current reproduction unit is coupled to a voltage bias transistor and generates a charging reference voltage according to a charging current flowing through the voltage bias transistor. The cell current reproduction unit is coupled to a common source transistor and generates a cell reference voltage according to a cell current flowing through the common source transistor.
The current comparator is coupled to the charging current reproduction unit and the cell current reproduction unit. The current comparator includes a first current generator and a second current generator. The first current generator generates a replica charging current according to the charging reference voltage, and the second current generator generates a replica cell current according to the cell reference voltage.
The bit line bias generator is coupled to the current comparator and a page buffer, and generates a bit line bias voltage to control the page buffer to charge a bit line according to a difference between the replica charge current and the replica cell current.
A plurality of first memory cells are coupled to the bit line, the voltage bias transistor having a first terminal for receiving a first system voltage, a second terminal, and a control terminal for receiving a first bias voltage. The page buffer is coupled to the bit line and a second terminal of the voltage bias transistor, and charges the bit line to a first system voltage according to the bit line bias voltage during a precharge operation. The common-source transistor has a first terminal coupled to the bit line, a second terminal for receiving a second system voltage less than the first system voltage, and a control terminal for receiving a control signal.
These and other objects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
Drawings
FIG. 1 illustrates a storage system according to one embodiment of the invention.
Fig. 2 shows a bias circuit according to an embodiment of the invention.
Detailed Description
FIG. 1 illustrates a storage system 100 according to one embodiment of the invention. The memory system 100 includes a plurality of memory cells MC (1,1) to MC (M, N), a
In fig. 1, memory cells MC (1,1) to MC (M, N) are arranged in an array. For example, memory cells MC (1,1) through MC (M,1) may be coupled to bit line BL1, and memory cells MC (1, N) through MC (M, N) may be coupled to bit line BLN. Further, the memory cells MC (1,1) to MC (1, N) may be coupled to the word line WL1, and the memory cells MC (M,1) to MC (M, N) may be coupled to the word line WLM.
The
The
In fig. 1, the
During the precharge operation, transistors M1 and M2 will be turned on, and transistor M3 will also be turned on to charge
Also, during the sensing operation, the transistors M1, M2, and M3 may be turned off, and the transistor M4 may be turned on, so that the voltage of the bit line BL may be sensed by the sense amplifier. Transistor M5 may be used to select the bit line to be precharged as desired.
The common-
During the precharge operation of the bit line BL1, the
Fig. 2 also shows a
The charging
The unit
The
The bit
In some embodiments, the charging current IchgMay flow to a parasitic capacitor on the bit lines BL 1-BLN at the beginning of the precharge operation, while the rest of the charging current IchgWill flow through
That is, at the start of the precharge operation, the charging current IchgWill be greater than the cell current IcellThus, the charging current I is reproducedrchg1Should be greater than the replica cell current Ircell1. In this case, the charging current I is replicatedrchg1And replica cell current Ircell1The difference between will cause the bit
Thereafter, when the parasitic capacitor is fully charged, the charging current I is replicatedrchg1Will be substantially equal to the replica cell current Ircell1. In this case, it may mean that the bit line BL1 has been charged, and therefore the bit
In some embodiments, the
Since the bit
In fig. 2, a charging current reproducing
In this case, the operational amplifier OP1 can ensure that the transistor M6 is biased under the same conditions as the
Similarly, the cell
In this case, the operational amplifier OP2 may ensure that the transistor M9 and the
In fig. 2, the first
In addition, in fig. 2, the transistors M7 and M10 are N-type transistors, and the transistors M8 and M11 are P-type transistors. In this case, the charging reference voltage V is usedref1Transistor M10 will be biased under the same conditions as transistor M7, so that transistor M10 can generate the replica charging current I by mirroring the current flowing through transistor M7rchg1. Similarly, using cell reference voltage Vref2The transistor M11 biases the transistor M8 under the same conditions, so that the transistor M11 can generate the replica cell current I by mirroring the current flowing through the transistor M8rcell1。
In fig. 2, the bit
In this case, when the charging current I is copiedrchg1Greater than replica cell current Ircell1Time, differential current IdiffWill be fed to the bit
In some embodiments, the size ratio of transistors M7 and M10 may be selected to adjust the replica charging current I according to system requirementsrchg1. However, the size ratio of the transistors M8 and M11 should be compared to that of the transistors M7 and M10The size ratio is the same.
Similarly, the size ratio of transistor M6 and
Further, in fig. 2, the charging
Also, in fig. 1, the bit lines BL1 through BLN may be precharged at the same time, but in some other embodiments, the bit lines BL1 through BLN may be precharged independently of the
In summary, the memory system and the bias circuit provided by the embodiment of the invention can immediately adjust the bit line bias voltage according to the charging state of the bit line, so that the strong charging capability can be maintained during the precharge operation. Also, since the charged state of the bit line can be detected by copying the difference between the charge current and the copy cell current, the precharge time can be optimized and the precharge operation can be controlled without being affected by process variations.
Those skilled in the art will readily observe that numerous modifications and alterations of the apparatus and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the scope and metes of the following claims.
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