Dynamic testing method and device for Flash Nand Flash, electronic equipment and storage medium
阅读说明：本技术 闪存Nand Flash的动态测试方法、装置、电子设备及存储介质 (Dynamic testing method and device for Flash Nand Flash, electronic equipment and storage medium ) 是由 殷中云 朱晓锐 邓玉良 方晓伟 杨彬 庄伟坚 于 2020-07-03 设计创作，主要内容包括：本发明公开了一种闪存Nand Flash的动态测试方法,包括：当编辑次数匹配到动态测试条件时,根据预设的动态控制指令列表中的温度控制指令控制Nand Flash芯片在第一目标温度下进行数据编程,得到第一数据文件；分别根据动态控制指令列表中不同的温度控制指令读取Nand Flash芯片在第二目标温度下的数据,得到第二目标温度对应的多个第二数据文件；分别根据多个第二数据文件及第一数据文件判定Nand Flash芯片在第二目标温度下的误码率。本方案通过读取Nand Flash芯片在第一目标温度下编程后的第一数据文件,并读取Nand Flash芯片在不同的第二目标温度下的多个第二数据文件,利用多个第二数据文件及第一数据文件确定不同温度下Nand Flash芯片的误码率,实现全面动态测试Nand Flash芯片的误码率。(The invention discloses a dynamic testing method of a Flash Nand Flash, which comprises the following steps: when the editing times are matched with the dynamic test conditions, controlling a Nand Flash chip to perform data programming at a first target temperature according to a temperature control instruction in a preset dynamic control instruction list to obtain a first data file; reading data of the Nand Flash chip at a second target temperature according to different temperature control instructions in the dynamic control instruction list respectively to obtain a plurality of second data files corresponding to the second target temperature; and respectively judging the error rate of the Nand Flash chip at the second target temperature according to the plurality of second data files and the first data file. According to the scheme, the error rate of the Nand Flash chip at different temperatures is determined by reading the first data file of the Nand Flash chip programmed at the first target temperature, reading the plurality of second data files of the Nand Flash chip at different second target temperatures and utilizing the plurality of second data files and the first data file, so that the error rate of the Nand Flash chip is comprehensively and dynamically tested.)
1. A dynamic test method for Flash Nand Flash is characterized by comprising the following steps:
when a test instruction is received, matching a dynamic test condition in a preset dynamic test condition list by using the editing times of the obtained Nand Flash chip, wherein the dynamic test condition list comprises corresponding relations between different editing time values and the dynamic test condition;
when the editing times are matched with the dynamic test conditions, controlling the Nand Flash chip to perform data programming at a first target temperature according to a temperature control instruction in a preset dynamic control instruction list to obtain a first data file, wherein the first target temperature is the temperature corresponding to the temperature control instruction;
at intervals of unit time, respectively reading data of the NandFlash chip at a second target temperature according to different temperature control instructions in the dynamic control instruction list to obtain a plurality of second data files corresponding to different second target temperatures, wherein the second target temperatures comprise different temperatures corresponding to the temperature control instructions;
and respectively judging the error rate of the Nand Flash chip at the second target temperature according to the plurality of second data files and the first data file.
2. The dynamic test method of Flash Nand Flash as claimed in claim 1, wherein the step of matching the dynamic test conditions in the preset dynamic test condition list by using the editing times of the obtained Nand Flash chip comprises:
acquiring the editing times of the Nand Flash chip;
searching the editing times value in a preset dynamic test condition list by using the editing times;
and when the editing times are equal to the editing time value, judging that the editing times are matched with the dynamic test conditions.
3. The dynamic test method of the Flash Nand Flash as claimed in claim 1, wherein the step of controlling the Nand Flash chip to program data at a first target temperature according to the temperature control instruction in the preset dynamic control instruction list to obtain a first data file comprises:
determining the first target temperature according to a temperature control instruction in a preset dynamic control instruction list, and generating a data programming instruction corresponding to the first target temperature;
controlling the Nand Flash chip to perform data programming at the first target temperature according to the data programming instruction;
and reading the data programmed by the Nand Flash chip, and storing the programmed data as the first data file.
4. The dynamic testing method of the Flash Nand Flash as claimed in claim 1, wherein the step of reading the data of the Nand Flash chip at the second target temperature according to different temperature control instructions in the dynamic control instruction list at intervals of unit time to obtain a plurality of second data files corresponding to the second target temperature comprises:
determining the second target temperature according to different temperature control instructions in the dynamic control instruction list and generating a plurality of data reading instructions corresponding to the second target temperature at intervals of unit time;
reading the data of the Nand Flash chip at the second target temperature according to the plurality of data reading instructions respectively;
and respectively generating the second target temperature corresponding to the second data file by using the read data.
5. The dynamic testing method of the Flash Nand Flash as claimed in claim 1, wherein the determining the bit error rate of the Nand Flash chip at the second target temperature according to the plurality of second data files and the first data file comprises:
respectively extracting second data in the plurality of second data files and extracting first data in the first data file;
comparing a plurality of second data with the first data respectively, and determining the number of error bits corresponding to the second data;
and determining the error rate of the Nand Flash chip at different temperatures according to the error bit number.
6. The dynamic testing method of Flash Nand Flash as claimed in claim 1, wherein the step of determining the error rate of the Nand Flash chip at the second target temperature according to the plurality of second data files and the first data file comprises the following steps:
and generating a bit error rate dynamic curve graph between the second target temperature and the bit error rate corresponding to the editing times according to the second target temperature and the corresponding bit error rate.
7. A dynamic testing device for Nand Flash of a Flash memory is characterized by comprising:
the device comprises an acquisition module, a test module and a test module, wherein the acquisition module is used for matching dynamic test conditions in a preset dynamic test condition list by using the editing times of an acquired Nand Flash chip when receiving a test instruction, and the dynamic test condition list comprises corresponding relations between different editing time values and the dynamic test conditions;
the programming module is used for controlling the Nand Flash chip to perform data programming at a first target temperature according to a temperature control instruction in a preset dynamic control instruction list when the editing times are matched with the dynamic test conditions, so as to obtain a first data file, wherein the first target temperature is the temperature corresponding to the temperature control instruction;
the reading module is used for reading data of the Nand Flash chip at a second target temperature at intervals according to different temperature control instructions in the dynamic control instruction list respectively to obtain a plurality of second data files corresponding to the different second target temperatures, wherein the second target temperatures comprise different temperatures corresponding to the temperature control instructions;
and the judging module is used for judging the error rate of the NandFlash chip at the second target temperature according to the plurality of second data files and the first data file respectively.
8. An electronic device, comprising: the dynamic testing method of the Flash Nand Flash is characterized in that a computer program is stored on the memory, and when the computer program is executed by the processor, each step in the dynamic testing method of the Flash Nand Flash is realized according to any one of claims 1 to 6.
9. A storage medium which is a computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps in the dynamic testing method of Flash memory Nand Flash according to any one of claims 1 to 6.
Technical Field
The invention relates to the technical field of Nand Flash data, in particular to a dynamic testing method and device of a Nand Flash, electronic equipment and a storage medium.
Background
A Nand Flash (Flash memory) chip designed vertically in 3D (Three dimensional) has gradually implemented a structural design of vertical stacking on a silicon chip, and Nand Flash has developed a multi-bit storage technology. When the Nand Flash is subjected to editing operations such as programming/erasing, the editing operations are transmitted in the thin oxide layer of the Nand Flash unit through charges and are tunneled in and out of the storage layer, and the editing operations are realized. However, in the practical application of the Nand Flash storage unit, the error rate of the Nand Flash is affected by the editing times of the Nand Flash and the ambient temperature pressure, which reduces the reliability of the Nand Flash. Therefore, the error rate of the Nand Flash chip in the extreme temperature environment needs to be tested.
In order to solve the problems, the related technology is to test the Nand Flash chip by a static temperature test mode, for example, the Nand Flash is edited under a high temperature condition, and the error rate of the Nand Flash after editing is detected; however, the static temperature test method does not consider the influence of the ambient temperature change under the editing times of the Nand Flash on the error rate of the Nand Flash chip, which results in that the static temperature test method cannot comprehensively test the error rate of the Nand Flash chip.
Therefore, it is necessary to provide a new testing technology for Nand Flash.
Disclosure of Invention
The application provides a dynamic testing method and device for Nand Flash, electronic equipment and a storage medium, which can solve the technical problem that the error rate of a Nand Flash chip cannot be comprehensively tested.
The first aspect of the invention provides a dynamic test method for a Nand Flash of a Flash memory, which comprises the following steps:
when a test instruction is received, matching a dynamic test condition in a preset dynamic test condition list by using the editing times of the obtained Nand Flash chip, wherein the dynamic test condition list comprises corresponding relations between different editing time values and the dynamic test condition;
when the editing times are matched with the dynamic test conditions, controlling the Nand Flash chip to perform data programming at a first target temperature according to a temperature control instruction in a preset dynamic control instruction list to obtain a first data file, wherein the first target temperature is the temperature corresponding to the temperature control instruction;
at intervals of unit time, respectively reading data of the Nand Flash chip at a second target temperature according to different temperature control instructions in the dynamic control instruction list to obtain a plurality of second data files corresponding to different second target temperatures, wherein the second target temperatures comprise different temperatures corresponding to the temperature control instructions;
and respectively judging the error rate of the Nand Flash chip at the second target temperature according to the plurality of second data files and the first data file.
Optionally, the step of matching the editing times of the obtained Nand Flash chip with the dynamic test conditions in the preset dynamic test condition list includes:
acquiring the editing times of the Nand Flash chip;
searching the editing times value in a preset dynamic test condition list by using the editing times;
and when the editing times are equal to the editing time value, judging that the editing times are matched with the dynamic test conditions.
Optionally, the step of controlling the NandFlash chip to perform data programming at a first target temperature according to a temperature control instruction in a preset dynamic control instruction list to obtain a first data file includes:
determining the first target temperature according to a temperature control instruction in a preset dynamic control instruction list, and generating a data programming instruction corresponding to the first target temperature;
controlling the Nand Flash chip to perform data programming at the first target temperature according to the data programming instruction;
and reading the data programmed by the Nand Flash chip, and storing the programmed data as the first data file.
Optionally, the step of reading data of the Nand Flash chip at a second target temperature according to different temperature control instructions in the dynamic control instruction list at intervals of unit time to obtain a plurality of second data files corresponding to the second target temperature includes:
determining the second target temperature according to different temperature control instructions in the dynamic control instruction list and generating a plurality of data reading instructions corresponding to the second target temperature at intervals of unit time;
reading the data of the Nand Flash chip at the second target temperature according to the plurality of data reading instructions respectively;
and respectively generating the second target temperature corresponding to the second data file by using the read data.
Optionally, the determining, according to the plurality of second data files and the first data file, the error rate of the NandFlash chip at the second target temperature includes:
respectively extracting second data in the plurality of second data files and extracting first data in the first data file;
comparing a plurality of second data with the first data respectively, and determining the number of error bits corresponding to the second data;
and determining the error rate of the Nand Flash chip at different temperatures according to the error bit number.
Optionally, after the step of determining the error rate of the NandFlash chip at the second target temperature according to the plurality of second data files and the first data file, respectively, the method includes:
and generating a bit error rate dynamic curve graph between the second target temperature and the bit error rate corresponding to the editing times according to the second target temperature and the corresponding bit error rate.
The second aspect of the present invention provides a dynamic testing apparatus for Nand Flash, which comprises:
the device comprises an acquisition module, a test module and a test module, wherein the acquisition module is used for matching dynamic test conditions in a preset dynamic test condition list by using the editing times of an acquired Nand Flash chip when receiving a test instruction, and the dynamic test condition list comprises corresponding relations between different editing time values and the dynamic test conditions;
the programming module is used for controlling the Nand Flash chip to perform data programming at a first target temperature according to a temperature control instruction in a preset dynamic control instruction list when the editing times are matched with the dynamic test conditions, so as to obtain a first data file, wherein the first target temperature is the temperature corresponding to the temperature control instruction;
the reading module is used for reading data of the Nand Flash chip at a second target temperature at intervals according to different temperature control instructions in the dynamic control instruction list respectively to obtain a plurality of second data files corresponding to the different second target temperatures, wherein the second target temperatures comprise different temperatures corresponding to the temperature control instructions;
and the judging module is used for judging the error rate of the Nand Flash chip at the second target temperature according to the plurality of second data files and the first data file respectively.
A third aspect of the present invention provides an electronic device comprising: the dynamic testing method of the NandFlash comprises a memory, a processor and a communication bus, wherein the communication bus is respectively in communication connection with the memory and the processor, the memory is stored with a computer program, and the processor executes the computer program to realize each step in the dynamic testing method of the NandFlash.
A fourth aspect of the present invention provides a storage medium, where the storage medium is a computer-readable storage medium, and a computer program is stored on the computer-readable storage medium, where the computer program, when executed by a processor, implements each step in the dynamic test method for Flash Nand Flash in the first aspect.
The dynamic testing method of the Flash Nand Flash provided by the invention comprises the following steps: when a test instruction is received, matching the editing times of the obtained Nand Flash chip with the dynamic test conditions in a preset dynamic test condition list, wherein the dynamic test condition list comprises corresponding relations between different editing times and the dynamic test conditions; when the editing times are matched with dynamic test conditions, controlling a Nand Flash chip to perform data programming at a first target temperature according to a temperature control instruction in a preset dynamic control instruction list to obtain a first data file, wherein the first target temperature is the temperature corresponding to the temperature control instruction; at intervals of unit time, reading data of the Nand Flash chip at a second target temperature according to different temperature control instructions in the dynamic control instruction list respectively to obtain a plurality of second data files corresponding to different second target temperatures, wherein the second target temperatures comprise temperatures corresponding to different temperature control instructions; and respectively judging the error rate of the Nand Flash chip at the second target temperature according to the plurality of second data files and the first data file. By implementing the scheme, when the editing times are matched with the dynamic test conditions, the error rate of the Nand Flash chip at different temperatures is determined by reading the first data file of the Nand Flash chip programmed at the first target temperature, reading the plurality of second data files of the Nand Flash chip at different second target temperatures and using the plurality of second data files and the first data file, so that the error rate of the Nand Flash chip is comprehensively tested.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a diagram of a dynamic test system for Nand Flash in a Flash memory according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating steps of a dynamic testing method for Nand Flash in a Flash memory according to an embodiment of the present invention;
FIG. 3 is a flowchart of another step of the dynamic testing method for Nand Flash in the Flash memory according to the embodiment of the present invention;
FIG. 4 is a block diagram of a dynamic testing apparatus for Nand Flash in a Flash memory according to an embodiment of the present invention;
fig. 5 is an architecture diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, features and advantages of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The technical problem that the error rate of the Nand Flash chip cannot be comprehensively tested in the prior art is solved.
In order to solve the technical problems, the invention provides a dynamic testing method and device of a Flash Nand Flash, electronic equipment and a storage medium.
Please refer to fig. 1, which is a system diagram of dynamic testing of Nand Flash in Flash memory according to an embodiment of the present invention. The embodiment of the invention provides a dynamic test system of a Flash Nand Flash, which comprises: the device comprises a
The
Referring to fig. 2, a flowchart of steps of a dynamic testing method for Nand Flash in a Flash memory according to an embodiment of the present invention is shown. The embodiment provides a dynamic test method of a Nand Flash, which is applied to a
step S201: when a test instruction is received, matching the editing times of the obtained Nand Flash chip with the dynamic test conditions in a preset dynamic test condition list, wherein the dynamic test condition list comprises corresponding relations between different editing times and the dynamic test conditions.
In step S201, the test instruction may be a manually input test start instruction, or a manually triggered test start instruction, and the test instruction is received by a processor, where the processor is a computer processor having data operation, data processing, and control functions, or a NandFlash controller or a data processing unit specially used for data programming/erasing/reading of a Nand Flash chip. When a processor receives a test instruction, acquiring the editing times of a Nand Flash chip, wherein the editing times are the times of the Nand Flash chip after data programming and data erasing, determining whether to start dynamic testing of the error rate of the Nand Flash chip or not through the editing times, specifically, matching the dynamic testing conditions in a preset dynamic testing condition list through the editing times, wherein the dynamic testing condition list comprises different corresponding relations between editing times and the dynamic testing conditions, when the editing times are the same as or matched with one of a plurality of editing times in the dynamic testing condition list, determining that the editing times reach the starting of the dynamic testing conditions, and the dynamic testing conditions are successfully matched, for example, when the editing times of the Nand Flash chip reach 100, 1000, 2000 and 3000, and if the starting dynamic test condition is met, starting the dynamic test of the error rate of the Nand Flash chip. It should be noted that the edit time value of the preset dynamic test condition list can also be manually set to other values, and by executing the step, the Nand Flash chip can be selected to perform dynamic test when the corresponding edit time is performed according to the characteristics of the Nand Flash chip, so as to realize that the Nand Flash chip performs dynamic test on the error rate under the corresponding edit time.
Step S202: and when the editing times are matched with the dynamic test conditions, controlling the Nand Flash chip to perform data programming at a first target temperature according to a temperature control instruction in a preset dynamic control instruction list to obtain a first data file, wherein the first target temperature is the temperature corresponding to the temperature control instruction.
Specifically, the preset dynamic control instruction list comprises a plurality of temperature control instructions, and the temperature control instructions are used for adjusting the temperature around the Nand Flash chip and controlling the Nand Flash chip to perform data programming at the temperature. When the editing times are the same as or matched with one of a plurality of editing times in the dynamic test condition list, determining that the editing times are matched with the dynamic test condition, and controlling the Nand Flash chip to perform data programming at a corresponding temperature by the Nand Flash controller according to a temperature control instruction in a preset dynamic control instruction list, wherein the corresponding temperature is regulated by the temperature control instruction, corresponds to the temperature control instruction, and is taken as a first target temperature. It should be noted that the dynamic control instruction list includes a plurality of temperature control instructions, and the temperature values around the Nand Flash chip adjusted by each temperature control instruction are different, that is, when different temperature control instructions in the dynamic control instruction list are selected, the temperature values corresponding to the first target temperatures around the Nand Flash chip are adjusted to be different, so that the Nand Flash chip can be controlled to perform programming of the same data at different first target temperatures, and then the programmed data are read, because the temperature pressure can affect the error rate of the Nand Flash chip, when the Nand Flash chip performs programming of the same data at different first target temperatures, different error rates can be caused; it is worth noting that when the Nand Flash chip is controlled to perform the programming of the same data at different first target temperatures, the data after the data programming at the first target temperature is performed at the previous time needs to be erased. By implementing the step, the Nand Flash chip with the editing times as the target editing times can be controlled to perform data programming at the corresponding first target temperature so as to obtain a first data file after the Nand Flash chip with the target editing times performs data programming at the first target temperature.
Step S203: and at intervals of unit time, reading data of the Nand Flash chip at a second target temperature according to different temperature control instructions in the dynamic control instruction list respectively to obtain a plurality of second data files corresponding to different second target temperatures, wherein the second target temperatures comprise temperatures corresponding to different temperature control instructions.
Specifically, the dynamic control instruction list includes a plurality of different temperature control instructions, the temperature control instructions are used for adjusting the temperature around the Nand Flash chip, and the temperature control instructions are also used for controlling the Nand Flash chip to read the data programmed in step S202 at the temperature. After a first data file of the Nand Flash chip after data programming at a first target temperature is obtained, controlling the temperature around the Nand Flash chip according to different temperature control instructions in the dynamic control instruction list at intervals of unit time, namely adjusting the temperature around the Nand Flash chip to be different by the different temperature control instructions, wherein each temperature control instruction corresponds to the adjusted temperature value, and the value of the second target temperature comprises the temperature corresponding to the different temperature control instructions. And further, reading data of the Nand Flash chip at the corresponding temperature, storing the data as a second data file, and reading the data of the Nand Flash chip at a second target temperature according to different temperature control instructions to obtain a plurality of second data files corresponding to different second target temperatures. By implementing the step, the temperature around the Nand Flash chip can be dynamically adjusted by utilizing different temperature control instructions in the dynamic control instruction list, and the data in the Nand Flash chip is read and stored as a second data file after the temperature around the Nand Flash chip is adjusted by the temperature control instructions each time, so that the second data files at different temperatures or at temperatures corresponding to different temperature control instructions can be obtained. It should be noted that, the data reading at the target temperature can be realized by setting or changing the temperature control command of the dynamic control command list.
Step S204: and respectively judging the error rate of the Nand Flash chip at the second target temperature according to the plurality of second data files and the first data file.
In order to judge that the error rate exists when the Nand Flash chip completes programming and reading operations at different temperatures, after data is programmed at a target temperature, the data is read and stored as a data file, data in the Nand Flash chip is read at another target temperature after unit time interval, the data is stored as another data file, the data in the two data files are compared, the number of error bits existing between the two data files is calculated, and then the error rate is calculated according to the number of error bits and the data in the second data file. It can be understood that, in this step, the number of the acquired second data files is multiple, specifically, the second data files are data files read by the user at various temperatures, the number of the second data files is equal to the number of the temperature control instructions in the preset dynamic control instruction list, and the data of the Nand Flash chip can be read at corresponding temperatures according to the temperature control instructions by setting corresponding temperature control instructions at different temperatures and stored as the second data files; furthermore, the second data files are respectively compared with the first data files to obtain the error rates between the first data files programmed at the first target temperature and the second data files read at the second target temperature, so that the error rates of the Nand Flash chip in the editing and reading operations at different temperatures can be judged, and the influence of the temperature change on the programming/reading of the Nand Flash chip can be obtained according to the error rates.
The dynamic testing method of the Flash Nand Flash provided by the invention comprises the following steps: when a test instruction is received, matching the editing times of the obtained Nand Flash chip with the dynamic test conditions in a preset dynamic test condition list, wherein the dynamic test condition list comprises corresponding relations between different editing times and the dynamic test conditions; when the editing times are matched with dynamic test conditions, controlling a Nand Flash chip to perform data programming at a first target temperature according to a temperature control instruction in a preset dynamic control instruction list to obtain a first data file, wherein the first target temperature is the temperature corresponding to the temperature control instruction; at intervals of unit time, reading data of the Nand Flash chip at a second target temperature according to different temperature control instructions in the dynamic control instruction list respectively to obtain a plurality of second data files corresponding to different second target temperatures, wherein the second target temperatures comprise temperatures corresponding to different temperature control instructions; and respectively judging the error rate of the Nand Flash chip at the second target temperature according to the plurality of second data files and the first data file. By implementing the scheme, when the editing times are matched with the dynamic test conditions, the error rate of the Nand Flash chip at different temperatures is determined by reading the first data file of the Nand Flash chip programmed at the first target temperature, reading the plurality of second data files of the Nand Flash chip at different second target temperatures and using the plurality of second data files and the first data file, so that the error rate of the Nand Flash chip is comprehensively tested.
Referring to fig. 3, a flowchart of another step of the dynamic testing method for Nand Flash in the Flash memory according to the embodiment of the present invention is shown, where the method includes the following steps:
step S301: when a test instruction is received, matching the editing times of the obtained Nand Flash chip with the dynamic test conditions in a preset dynamic test condition list, wherein the dynamic test condition list comprises corresponding relations between different editing times and the dynamic test conditions.
Step S302: and when the editing times are matched with the dynamic test conditions, controlling the Nand Flash chip to perform data programming at a first target temperature according to a temperature control instruction in a preset dynamic control instruction list to obtain a first data file, wherein the first target temperature is the temperature corresponding to the temperature control instruction.
Step S303: and at intervals of unit time, reading data of the Nand Flash chip at a second target temperature according to different temperature control instructions in the dynamic control instruction list respectively to obtain a plurality of second data files corresponding to different second target temperatures, wherein the second target temperatures comprise temperatures corresponding to different temperature control instructions.
Step S304: and respectively judging the error rate of the Nand Flash chip at the second target temperature according to the plurality of second data files and the first data file.
Steps S301 to S304 are similar to or the same as steps S201 to S204 in the dynamic testing method for Flash Nand Flash, and the description of steps S301 to S304 in this embodiment is similar to that of steps S201 to S204 in the foregoing steps, which is not further described in this embodiment.
Step S305: and generating a bit error rate dynamic curve graph between the second target temperature and the bit error rate corresponding to the editing times according to the second target temperature and the corresponding bit error rate.
Specifically, after data editing is performed at a specific first target temperature, reading a first data file, and reading second data files at a plurality of different second target temperatures respectively to obtain a plurality of target error rates of the data programmed at the first target temperature at each second target temperature, where the target error rates are the error rates in this step; further, an error rate dynamic curve graph is generated according to different second target temperatures and error rates corresponding to the second target temperatures. By executing the step, the error rate of the Nand Flash chip in the editing and reading operations at different temperatures can be quickly known, so that the influence of the temperature change on the programming/reading of the Nand Flash chip can be quickly known.
Step S306: and erasing the programming data in the Nand Flash chip, wherein the programming data is the data corresponding to the first data file.
In order to test the error rate when the Nand Flash chip is subjected to data programming at different temperatures, the Nand Flash chip is controlled to perform data programming according to different temperature control instructions in a preset dynamic control instruction list so as to read a first data file of data after the Nand Flash chip is programmed at different first target temperatures; however, when testing the Nand Flash chip, the data programming of the Nand Flash chip at the first target temperature is to perform the data programming of all blocks (storage physical blocks) in the Nand Flash chip, so that before controlling the Nand Flash chip to perform the data programming according to different temperature control instructions in the dynamic control instruction list, the data programmed to the Nand Flash chip in the previous dynamic test process needs to be erased, and the previous dynamic test process can be a process of controlling the Nand Flash chip to perform the data programming according to the temperature control instructions in the preset dynamic control instruction list; it can be understood that the programmed data in the Nand Flash chip can be erased after the dynamic test of the Nand Flash chip is completed each time. The influence of data in the original Nand Flash chip on the data programming data of the Nand Flash chip in the dynamic test can be avoided through the erasing operation, the error rate is inaccurate, and the Nand Flash chip can have an independent data programming space through the erasing.
Further, step S301 includes:
acquiring the editing times of the Nand Flash chip;
searching an editing number value in a preset dynamic test condition list by using the editing number;
and when the editing times are equal to the editing time value, judging that the editing times are matched with the dynamic test conditions.
Specifically, accessing a redundant area of a Nand Flash chip, extracting the editing times stored in the redundant area of the Nand Flash chip, searching a dynamic test condition in a preset dynamic test condition list through the editing times, wherein the dynamic test condition list comprises different corresponding relations between editing time values and the dynamic test condition, and when the editing times are equal to one of a plurality of editing time values in the dynamic test condition list, determining that the editing times reach the dynamic test starting condition, and successfully matching the dynamic test condition.
Further, step S302 includes:
when the editing times are matched with the dynamic test conditions, determining a first target temperature according to a temperature control instruction in a preset dynamic control instruction list, and generating a data programming instruction corresponding to the first target temperature;
controlling the Nand Flash chip to perform data programming at a first target temperature according to the data programming instruction;
and reading the data programmed by the Nand Flash chip, and storing the programmed data as a first data file.
Specifically, in step S302, when the number of edits is the same as or matches a certain number of edits in the dynamic test condition list, it is determined that the number of edits matches the dynamic test condition, at this time, the Nand Flash controller determines a first target temperature according to a temperature control instruction in a preset dynamic control instruction list, adjusts a temperature value around the Nand Flash chip according to the determined first target temperature, and generates a data programming instruction corresponding to the first target temperature, controls the Nand Flash chip to perform data programming at the first target temperature according to the data programming instruction, so as to implement data programming of the Nand Flash chip at the first target temperature, and reads data programmed to the Nand Flash chip after programming as a first data file, which can also be used for testing the error rate of programming operation at the first target temperature, for example, by obtaining the number of error bits of the data in the first data file, the error rate is calculated according to the number of error bits. It should be noted that the dynamic control instruction list includes a plurality of temperature control instructions, and the temperature values around the Nand Flash chip adjusted by each temperature control instruction are different, that is, when different temperature control instructions in the dynamic control instruction list are selected, the temperature values corresponding to the first target temperatures around the Nand Flash chip are adjusted to be different, so that the Nand Flash chip can be controlled to perform programming of the same data at different first target temperatures, and then the programmed data are read, because the temperature pressure can affect the error rate of the Nand Flash chip, when the Nand Flash chip performs programming of the same data at different first target temperatures, different error rates can occur; by implementing the step, the Nand Flash chip with the editing times as the target editing times can be controlled to perform data programming at the corresponding first target temperature so as to obtain a first data file after the Nand Flash chip with the target editing times performs data programming at the first target temperature.
Further, step S303 includes:
determining a second target temperature according to different temperature control instructions in the dynamic control instruction list and generating a plurality of data reading instructions corresponding to the second target temperature at intervals of unit time;
reading data of the Nand Flash chip at a second target temperature according to the plurality of data reading instructions;
and respectively generating a second data file corresponding to the second target temperature by using the read data.
In step S303, after obtaining a first data file of the Nand Flash chip after data programming at a first target temperature, controlling the temperature around the Nand Flash chip according to different temperature control instructions in the dynamic control instruction list at intervals, that is, adjusting the temperature around the Nand Flash chip to be different by the different temperature control instructions, where each temperature control instruction corresponds to an adjusted temperature value thereof, and a value of the second target temperature includes temperatures corresponding to the different temperature control instructions; further, reading data of the Nand Flash chip at the corresponding temperature, storing the data as a second data file, and reading the data of the Nand Flash chip at a second target temperature according to different temperature control instructions to obtain a plurality of second data files corresponding to different second target temperatures; and when the temperature control instructions in the preset dynamic control instruction list are completed through traversal, reading second data files at a second target temperature corresponding to all the temperature control instructions in the dynamic control instruction list. By implementing the step, different second target temperatures can be determined by using different temperature control instructions in the dynamic control instruction list, the temperature around the Nand Flash chip can be dynamically adjusted through temperature adjustment, data reading instructions corresponding to the different second target temperatures are generated, data in the Nand Flash chip are read at the corresponding second target temperatures according to the data reading instructions and stored as second data files, and therefore the second data files at different temperatures or at temperatures corresponding to the different temperature control instructions can be obtained.
Further, step S304 includes:
respectively extracting second data in the plurality of second data files and extracting first data in the first data file;
comparing the plurality of second data with the first data respectively, and determining the error bit number corresponding to the second data;
and respectively determining the error rates of the Nand Flash chips at different temperatures according to the error bit number.
In step S304, second data in the plurality of second data files are respectively extracted, first data in the first data file is extracted, the number of error bits corresponding to the second data is determined by matching the second data with the first data, and the error rate of the second data file is determined according to the number of error bits, which can be understood as the error rate of the Nand Flash chip, and is the error rate generated when the Nand Flash chip is programmed at a first target temperature and reads data at a second target temperature. Further, second data at different second target temperatures are compared with the first data at the first target temperature, so that the error rates at different second target temperatures can be respectively obtained according to a preset dynamic control instruction list. By executing the step, the error rates of the Nand Flash chip in the editing and reading operations at different temperatures can be judged, and the influence of the temperature change on the programming/reading of the Nand Flash chip can be obtained according to the error rates.
Referring to fig. 4, a block diagram of a dynamic testing apparatus module of a Flash Nand Flash according to an embodiment of the present invention is provided; the embodiment of the invention provides a dynamic testing device for Nand Flash of a Flash memory, wherein the device 400 comprises:
the obtaining module 401 is configured to match a preset dynamic test condition in a dynamic test condition list by using the editing times of the obtained Nand Flash chip when receiving the test instruction, where the dynamic test condition list includes corresponding relationships between different values of the editing times and the dynamic test condition.
And the programming module 402 is configured to, when the number of editing times is matched with the dynamic test condition, control the Nand Flash chip to perform data programming at a first target temperature according to a temperature control instruction in a preset dynamic control instruction list, so as to obtain a first data file, where the first target temperature is a temperature corresponding to the temperature control instruction.
The reading module 403 is configured to read data of the Nand Flash chip at a second target temperature at intervals of unit time according to different temperature control instructions in the dynamic control instruction list, respectively, to obtain a plurality of second data files corresponding to different second target temperatures, where the second target temperatures include temperatures corresponding to different temperature control instructions.
And the determining module 404 is configured to determine an error code of the NandFlash chip at the second target temperature according to the plurality of second data files and the first data file, respectively.
The invention provides a dynamic testing device of Flash Nand Flash, which comprises: an acquisition module 401, a programming module 402, a reading module 403, and a decision module 404. When a test instruction is received, the obtaining module 401 is used for obtaining the dynamic test conditions in the NandFlash chip, wherein the editing times of the NandFlash chip are matched with the dynamic test conditions in a preset dynamic test condition list, and the dynamic test condition list comprises corresponding relations between different editing times and the dynamic test conditions; when the editing times are matched with the dynamic test conditions, controlling a Nand Flash chip to perform data programming at a first target temperature through a programming module 402 according to a temperature control instruction in a preset dynamic control instruction list to obtain a first data file, wherein the first target temperature is the temperature corresponding to the temperature control instruction; at intervals of unit time, reading data of the Nand Flash chip at a second target temperature through the reading module 403 according to different temperature control instructions in the dynamic control instruction list respectively to obtain a plurality of second data files corresponding to different second target temperatures, wherein the second target temperatures include temperatures corresponding to different temperature control instructions; and the error rate of the Nand Flash chip at the second target temperature is judged by the judging module 404 according to the plurality of second data files and the first data file respectively. By implementing the scheme, when the editing times are matched with the dynamic test conditions, the error rate of the Nand Flash chip at different temperatures is determined by reading the first data file of the Nand Flash chip programmed at the first target temperature, reading the plurality of second data files of the Nand Flash chip at different second target temperatures and using the plurality of second data files and the first data file, so that the error rate of the Nand Flash chip is comprehensively tested.
Further, the apparatus 400 further comprises: a drawing module 405 and an erasing module 406.
And the drawing module 405 is configured to generate a bit error rate dynamic curve graph between the second target temperature and the bit error rate corresponding to the editing times according to the second target temperature and the corresponding bit error rate.
The drawing module 405 in the device 400 can generate a bit error rate dynamic curve graph between the second target temperature and the bit error rate corresponding to the editing times according to the second target temperature and the corresponding bit error rate, so as to quickly know the bit error rates of the Nand Flash chip during the editing and reading operations at different temperatures, and quickly learn the influence of temperature change on the programming/reading of the Nand Flash chip.
And the erasing module 406 is used for erasing the programming data in the Nand Flash chip, wherein the programming data is data corresponding to the first data file.
The erasing module 406 in the device 400 can erase the programming data in the Nand Flash chip, the programming data is the data corresponding to the first data file, the influence of the data in the original Nand Flash chip on the data programming data of the Nand Flash chip in the dynamic test can be avoided, the error rate is not accurate, and the Nand Flash chip can have an independent data programming space by erasing.
The present invention provides an electronic device, please refer to fig. 5, which is an architecture diagram of the electronic device according to an embodiment of the present invention, and the electronic device includes: the dynamic testing method of the Flash Nand Flash comprises a memory 501, a processor 502 and a communication bus 503, wherein the communication bus 503 is respectively connected with the memory 501 and the processor 502 in a communication mode, the memory 501 is coupled with the processor 502, a computer program is stored on the memory 501, and when the processor 502 executes the computer program, each step in the dynamic testing method of the Flash Nand Flash of any one of the embodiments is realized.
Illustratively, the computer program of the dynamic testing method for Flash Nand Flash mainly comprises: when a test instruction is received, matching the editing times of the obtained Nand Flash chip with the dynamic test conditions in a preset dynamic test condition list, wherein the dynamic test condition list comprises corresponding relations between different editing times and the dynamic test conditions; when the editing times are matched with the dynamic test conditions, controlling the NandFlash chip to perform data programming at a first target temperature according to a temperature control instruction in a preset dynamic control instruction list to obtain a first data file, wherein the first target temperature is the temperature corresponding to the temperature control instruction; at intervals of unit time, reading data of the NandFlash chip at a second target temperature according to different temperature control instructions in the dynamic control instruction list respectively to obtain a plurality of second data files corresponding to different second target temperatures, wherein the second target temperatures comprise temperatures corresponding to different temperature control instructions; and respectively judging the error rate of the Nand Flash chip at the second target temperature according to the plurality of second data files and the first data file. In addition, the computer program may also be divided into one or more modules, which are stored in the memory and executed by the processor to accomplish the present invention. One or more of the modules may be a series of computer program instruction segments capable of performing certain functions, the instruction segments being used to describe the execution of a computer program in a computing device. For example, the computer program may be divided into an acquisition module 401, a programming module 402, a reading module 403, and a determination module 404 as shown in FIG. 4.
The Processor 502 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The invention further provides a storage medium, the storage medium is a computer-readable storage medium, a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps in the dynamic test method for the Flash Nand Flash in any embodiment are realized.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is merely a logical division, and in actual implementation, there may be other divisions, for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present invention is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the above description, for a person skilled in the art, according to the idea of the embodiment of the present invention, there are changes in the specific implementation and application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
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