阅读说明：本技术 一种半导体结构及其制备方法 (Semiconductor structure and preparation method thereof ) 是由 安重镒 金成基 熊文娟 崔恒玮 蒋浩杰 李亭亭 于 2020-06-05 设计创作，主要内容包括：本发明涉及一种半导体结构及其制备方法。一种半导体结构,包括半导体衬底,所述半导体衬底上沉积有多层物质,该多层物质形成有多重界面的表面,所述多重界面的表面上依次沉积有等离子氮化层和Si<Sub>3</Sub>N<Sub>4</Sub>层。一种半导体结构的制备方法,包括下列步骤：在具有多重界面的半导体载体上进行等离子体氮化(Plasma Nitridation,PN)处理,然后沉积Si<Sub>3</Sub>N<Sub>4</Sub>。本发明解决了湿清洁半导体结构时多晶硅被刻蚀引发器件不良的问题。(The invention relates to a semiconductor structure and a preparation method thereof. A semiconductor structure comprises a semiconductor substrate having a multilayer material deposited thereon, the multilayer material forming a surface of multiple interfaces, the multiple interfaces having sequentially deposited thereonIon nitrided layer and Si 3 N 4 And (3) a layer. A method of fabricating a semiconductor structure, comprising the steps of: plasma Nitridation (PN) treatment is performed on a semiconductor carrier with multiple interfaces, followed by deposition of Si 3 N 4 . The invention solves the problem of poor device caused by etching of polycrystalline silicon when wet cleaning of the semiconductor structure.)

1. A semiconductor structure, comprising a semiconductor substrate,

the semiconductor substrate is deposited with a multilayer substance forming a surface of multiple interfaces on which a plasma nitrided layer and Si are sequentially deposited₃N₄And (3) a layer.

2. The semiconductor structure of claim 1, wherein the semiconductor structure is a structure comprising a BL bit line.

3. The semiconductor structure of claim 1, wherein the semiconductor structure is a memory structure or a logic device structure.

4. The semiconductor structure of claim 3, wherein the semiconductor structure is a DRAM, a 2D NAND, a 3D NAND, or an LCD.

5. The semiconductor structure of claim 1, wherein the multilayer substance comprises at least two of: polysilicon, metal, and nitride.

6. A method for fabricating a semiconductor structure, comprising the steps of:

plasma nitridation treatment on a semiconductor carrier with multiple interfaces followed by deposition of Si₃N₄。

7. The method of claim 6, wherein the semiconductor carrier with multiple interfaces is a memory structure or a logic device structure.

8. The method of claim 6, wherein the plasma nitridation is performed by a bias method or a non-bias method.

9. The method according to claim 8, wherein a process gas used in the plasma nitridation treatment is at least one of: NH (NH)₃、N₂And Ar.

10. The method according to any one of claims 6 to 9, wherein the plasma nitriding treatment is performed by a cluster type apparatus, a furnace type apparatus or a rotary type apparatus (Merry-go-round).

11. The method of any one of claims 6-9, wherein the semiconductor structure is a DRAM, 2DNAND, 3D NAND, or LCD.

12. The production method according to any one of claims 6 to 9, wherein the multiple interface is an interface formed by at least two of the following: polysilicon, metal, and nitride.

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor structure and a preparation method thereof.

Background

Si plating is often required in semiconductor devices₃N₄The film acts as an insulating layer and is bonded to Si in the device structure₃N₄Adjacent to the membrane is typically a multiple interface (interface) configuration, such as Gate arrays (gates) in memory and logic devices. Taking BL Bit lines (Bit lines) in a memory as an example, the manufacturing process is as follows: multiple materials (such as polysilicon (Poly Si), Tungsten (W), titanium strontium nitride (TINCN), etc.) are evaporated on a semiconductor substrate, a structure with two interfaces at selected parts is shown in figure 1, and Si is evaporated after patterning and etching₃N₄And (3) a membrane. In the deposition of Si₃N₄In the case of membranes, the incubation times of different interfaces differ due to the presence of multiple interfaces, which leads to Si at the interfaces of different substances₃N₄The film thickness is not uniform, and as shown in fig. 2, the difference in film thickness causes the following problems in the subsequent wet cleaning: thin Si₃N₄Pinholes (pin holes) are generated in the film, which in turn causes the underlying polysilicon to be etched. The polysilicon etching causes device defects, especially when Air Gap Spacer (Air Gap Spacer) is used, the etchant flows into Si again to remove oxide impurities on BL bit lines₃N₄Between the films, the failure becomes more serious. However, no better solution has been found in the prior artThe above problems.

Disclosure of Invention

A first objective of the present invention is to provide a semiconductor structure that solves the problem of device defects caused by etching of polysilicon (or other functional interface material) during wet cleaning of the semiconductor structure.

The second purpose of the present invention is to provide a method for manufacturing a semiconductor structure, which solves the problem that the existing manufacturing method is easy to cause device defects.

In order to achieve the above purpose, the invention provides the following technical scheme:

a semiconductor structure includes a semiconductor substrate,

the semiconductor substrate is deposited with a multilayer substance forming a surface of multiple interfaces on which a plasma nitrided layer and Si are sequentially deposited₃N₄And (3) a layer.

In the semiconductor structure, the plasma nitrided layer added on multiple interfaces can cover the defects of different properties of the multiple interfaces and different incubation times when the same substance is deposited, namely the properties of the multiple interfaces are uniformized through modification, the incubation times when other substances are deposited are the same, and further the Si deposited on the upper layer is enabled to be the same₃N₄Can have a uniform film thickness, even if there are etching problems during subsequent wet cleaning, not as thin Si₃N₄Is completely etched away and thus into the material of the multiple interfaces.

Wherein the configuration of the "multilayer substance" deposited on the semiconductor substrate may be: different substances are stacked one on top of the other with "end-to-end" relationship on the surface, or not stacked one on top of the other, with only end-to-end relationship on the exposed surface. The present invention is not limited in this regard as long as the exposed surface has multiple interfaces.

The "plasma nitrided layer" refers to a plasma nitrided layer formed by a plasma nitriding technique.

A method of fabricating a semiconductor structure, comprising the steps of:

plasma Nitridation (PN) treatment is performed on a semiconductor carrier with multiple interfaces, followed by deposition of Si₃N₄。

The method also solves the problem that polysilicon (or other functional interface substances) is etched to cause poor devices when the semiconductor structure is cleaned in a wet mode according to the principle.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.

FIG. 1 is a semiconductor structure having a double interface;

FIG. 2 is a schematic diagram of the direct deposition of Si on the multiple interfaces of FIG. 1₃N₄Morphology after filming;

FIG. 3 is a schematic representation of the direct deposition of Si at the triple interface containing polysilicon, tungsten and nitride₃N₄Morphology after filming;

FIG. 4 is a topography of the structure of FIG. 3 after wet cleaning;

FIG. 5 is a schematic representation of Si deposition using the method of the present invention on a triple interface containing polysilicon, tungsten and nitride₃N₄Morphology after filming;

FIG. 6 is a topography of the structure of FIG. 5 after wet cleaning;

FIG. 7 is a graph of post plasma nitridation processing topography at a dual interface comprising polysilicon and tungsten;

FIG. 8 is a deposition of Si on the structure of FIG. 7₃N₄Morphology after filming.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It is to be understood that such description is merely illustrative and not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.

Various structural schematics according to embodiments of the present invention are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present invention, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.