阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 蒋鑫 杨志勇 于 2019-04-10 设计创作，主要内容包括：一种半导体结构及其形成方法,形成方法包括：提供基底,基底上形成有伪栅结构和位于其顶部的硬掩膜层；形成保形覆盖硬掩膜层顶部和侧壁、伪栅结构侧壁、以及伪栅结构所露出基底的刻蚀停止层；在伪栅结构露出的基底上形成介质材料层；以刻蚀停止层顶部最高处为停止位置对介质材料层进行第一平坦化处理；进行第一平坦化处理后,对刻蚀停止层和介质材料层进行刻蚀处理,去除高于硬掩膜层顶部的刻蚀停止层和介质材料层；进行刻蚀处理后,以伪栅结构顶部为停止位置对介质材料层和硬掩膜层进行第二平坦化处理,剩余介质材料层作为层间介质层。本发明实施例有利于提高层间介质层顶面的平坦度,且降低所述栅极结构受损的概率。(A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein a pseudo gate structure and a hard mask layer positioned on the top of the pseudo gate structure are formed on the substrate; forming an etching stop layer which conformally covers the top and the side wall of the hard mask layer, the side wall of the pseudo gate structure and the substrate exposed by the pseudo gate structure; forming a dielectric material layer on the substrate exposed out of the pseudo gate structure; performing first planarization treatment on the dielectric material layer by taking the highest position at the top of the etching stop layer as a stop position; after the first planarization treatment, etching the etching stop layer and the medium material layer, and removing the etching stop layer and the medium material layer which are higher than the top of the hard mask layer; and after etching treatment, performing second planarization treatment on the dielectric material layer and the hard mask layer by taking the top of the pseudo-gate structure as a stop position, and taking the residual dielectric material layer as an interlayer dielectric layer. The embodiment of the invention is beneficial to improving the flatness of the top surface of the interlayer dielectric layer and reducing the damage probability of the grid structure.)

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein a pseudo gate structure is formed on the substrate, and a hard mask layer is formed on the top of the pseudo gate structure;

forming an etching stop layer which conformally covers the top and the side wall of the hard mask layer, the side wall of the pseudo gate structure and the substrate exposed by the pseudo gate structure;

forming a dielectric material layer on the substrate exposed out of the pseudo gate structure, wherein the dielectric material layer covers the etching stop layer positioned on the hard mask layer;

taking the highest position at the top of the etching stop layer as a stop position, and performing first planarization treatment on the dielectric material layer;

after the first planarization treatment, etching the etching stop layer and the dielectric material layer to remove the etching stop layer and the dielectric material layer which are higher than the top of the hard mask layer;

and after the etching treatment, performing second planarization treatment on the dielectric material layer and the hard mask layer by taking the top of the pseudo-gate structure as a stop position, and taking the residual dielectric material layer as an interlayer dielectric layer.

2. The method of claim 1, wherein said first planarization process is performed using a chemical mechanical polishing process.

3. The method of forming a semiconductor structure of claim 1, wherein the etching process is performed using a dry etching process.

4. The method of forming a semiconductor structure of claim 1, wherein said etching is performed using a Siconi process.

5. The method of claim 1, wherein the step of performing the etching process has a difference in height of the top surface of the dielectric material layer of less than 10nm for each region.

6. The method of claim 1, wherein said second planarization process is performed using a chemical mechanical polishing process.

7. The method of forming a semiconductor structure of claim 1, wherein after the etching process and before the second planarizing process, further comprising: cutting off the dummy gate structure by an etching process, and forming openings exposing the substrate in the dielectric material layer, wherein the openings are distributed in the extending direction of the dummy gate structure; forming an isolation material layer filled in the opening, wherein the isolation material layer also covers the medium material layer and the hard mask layer; taking the top of the hard mask layer as a stop position, and carrying out third planarization treatment on the isolation material layer and the medium material layer;

and in the step of performing second planarization treatment, second planarization treatment is also performed on the isolation material layer, and the residual isolation material layer after the second planarization treatment is used as an isolation structure.

8. The method for forming a semiconductor structure according to claim 7, wherein the hard mask layer comprises a bottom hard mask layer and a top hard mask layer located on the bottom hard mask layer, the bottom hard mask layer is made of silicon nitride, and the top hard mask layer is made of silicon oxide;

in the step of etching the etching stop layer and the dielectric material layer, removing the etching stop layer and the dielectric material layer which are higher than the top of the top hard mask layer;

and in the third planarization treatment step, the bottom hard mask layer is taken as a stop position.

9. The method of claim 7, wherein said third planarization process is performed using a chemical mechanical polishing process.

10. The method of forming a semiconductor structure of claim 7, wherein after forming the opening and before forming the layer of isolation material, further comprising: and forming a protective layer on the side wall of the opening.

11. The method of claim 10, wherein in the step of forming the protective layer, the protective layer is formed of silicon nitride.

12. The method of forming a semiconductor structure of claim 10, wherein the process of forming the protective layer comprises an atomic layer deposition process.

13. The method of forming a semiconductor structure of claim 10, wherein forming the protective layer comprises: forming a protective material layer conformally covering the bottom and the side wall of the opening and the top of the hard mask layer and the dielectric material layer;

and removing the protective material layers positioned at the tops of the hard mask layer and the dielectric material layer and at the bottom of the opening by adopting an anisotropic etching process, and reserving the residual protective material layer on the side wall of the opening as the protective layer.

14. A semiconductor structure formed using the method of any of claims 1-13.

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

With the development of high integration of semiconductor devices, the gate length of Metal Oxide Semiconductor (MOS) devices is being scaled down to smaller dimensions, and accordingly, the fabrication process of semiconductor devices is also being improved to meet the requirements of people on device performance.

Depending on the type and function of the semiconductor device, there may be caused a difference in the number of wiring layers of the semiconductor device to be manufactured. A semiconductor device generally includes a device Layer on and within a semiconductor substrate, an interlayer Dielectric (ILD) Layer on the device Layer, and a wiring structure within the ILD Layer for connecting active and passive devices within the device Layer. The interlayer dielectric layer is generally made of an insulating material, and short circuits between the active or passive devices and the wires constituting the wiring structure can be prevented.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a pseudo gate structure is formed on the substrate, and a hard mask layer is formed on the top of the pseudo gate structure; forming an etching stop layer which conformally covers the top and the side wall of the hard mask layer, the side wall of the pseudo gate structure and the substrate exposed by the pseudo gate structure; forming a dielectric material layer on the substrate exposed out of the pseudo gate structure, wherein the dielectric material layer covers the etching stop layer positioned on the hard mask layer; taking the highest position at the top of the etching stop layer as a stop position, and performing first planarization treatment on the dielectric material layer; after the first planarization treatment, etching the etching stop layer and the dielectric material layer to remove the etching stop layer and the dielectric material layer which are higher than the top of the hard mask layer; and after the etching treatment, performing second planarization treatment on the dielectric material layer and the hard mask layer by taking the top of the pseudo-gate structure as a stop position, and taking the residual dielectric material layer as an interlayer dielectric layer.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: the semiconductor structure formed by the forming method.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the embodiment of the invention, the highest position at the top of the etching stop layer is taken as a stop position, and the dielectric material layer is subjected to the first planarization treatment, so that in the step of the first planarization treatment, only the dielectric material layer is subjected to the first planarization treatment without contacting other film layer structures, the problem of grinding amount difference caused by different pattern densities of all regions or different heights of the top surfaces of all the film layer structures is favorably prevented, the probability of dishing (deforming) at the top of the dielectric material layer is reduced, the height consistency of the top of the dielectric material layer after the first planarization treatment is better, meanwhile, the thickness of the dielectric material layer to be removed in the subsequent etching treatment can be reduced, the process time required by the etching treatment is shorter, and different materials are easily removed in the same step at similar etching rates by adopting an anisotropic etching process, the method is favorable for reducing the difference of the etching amount of the dielectric material layer in different pattern density areas by the etching treatment, so that the top of the residual dielectric material layer has better height consistency after the etching treatment is finished, and the method is also favorable for reducing the probability of the loss problem of the etching stop layer on the side wall of the pseudo gate structure caused by the difference of the etching amount of the dielectric material layer, thereby ensuring the protective effect of the etching stop layer on the side wall of the formed gate structure in the subsequent process and preventing the loss of the side wall of the gate structure; in summary, the embodiment of the invention combines the first planarization treatment and the etching treatment, and can reduce the probability of damage to the gate structure while improving the flatness of the top surface of the interlayer dielectric layer, thereby improving the performance of the semiconductor structure.

Drawings

Fig. 1 to 7 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;

FIG. 8 is an electron microscope scan of a semiconductor structure;

fig. 9 to 19 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

In the semiconductor field, the step of forming an interlayer dielectric layer generally includes: forming a dielectric material layer on the substrate exposed out of the pseudo gate structure, wherein the dielectric material layer covers the top of the pseudo gate structure; and flattening the top of the dielectric material layer, wherein the residual dielectric material layer is used as an interlayer dielectric layer, and the interlayer dielectric layer is exposed out of the top of the pseudo gate structure.

In the semiconductor field, the pattern density of different areas on the substrate is usually different according to the design requirements of the integrated circuit, for example: the substrate generally comprises a graph dense area and a graph sparse area, compared with the graph dense area, the number of the pseudo gate structures on the graph sparse area is small, the distance between the adjacent pseudo gate structures is long, and the size of an opening formed by the adjacent pseudo gate structures and the substrate is large.

Due to the loading effect, the larger the size of the opening, the faster the rate of being planarized, and the more removed in the same time. Therefore, in the step of performing planarization treatment on the top of the dielectric material layer, the planarization treatment rate of the dielectric material layer in the pattern sparse region is high, which easily causes poor height consistency of the top surface of the interlayer dielectric layer and high probability of the top surface of the interlayer dielectric layer having a recess problem.

To solve the above problems, a method for forming a semiconductor structure is proposed. Referring to fig. 1 to 7, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.

Referring to fig. 1, a substrate 1 is provided, a dummy gate structure 2 is formed on the substrate 1, a hard mask layer 3 is formed on the top of the dummy gate structure 2, and a first etching stop layer 4 conformally covering the top and side walls of the hard mask layer 3, the side walls of the dummy gate structure 2, and the substrate 1 exposed by the dummy gate structure 2 is further formed on the substrate 1.

Referring to fig. 2, a bottom dielectric material layer 5 is formed on the substrate 1 exposed by the dummy gate structure 2, and the bottom dielectric material layer 5 covers the first etching stop layer 4 on the hard mask layer 3.

Referring to fig. 3, the bottom dielectric material layer 5 is etched by a certain thickness, and part of the sidewall of the dummy gate structure 2 is exposed by the remaining bottom dielectric material layer 5.

Referring to fig. 4, a dummy gate structure 2 exposed to the remaining bottom dielectric material layer 5 and a second etch stop layer 6 remaining the bottom dielectric material layer 5 are conformally covered.

Referring to fig. 5 and 6, a top dielectric material layer 7 is formed on the second etch stop layer 6; and flattening the top dielectric material layer 7 by taking the top of the second etching stop layer 6 positioned on the pseudo gate structure 2 as a stop position.

Referring to fig. 7, after the top dielectric material layer 7 is planarized, with the top of the hard mask layer 3 as a stop position, the top dielectric material layer 7, the second etching stop layer 6 and the first etching stop layer 4 higher than the hard mask layer 3 are removed by grinding, and the remaining top dielectric material layer 7, the second etching stop layer 6 and the bottom dielectric material layer 5 located between adjacent dummy gate structures 2 are used as interlayer dielectric layers (not labeled).

In the forming method, the second etching stop layer 6 is formed on the residual bottom dielectric material layer 5, and the second etching stop layer 6 can define the position of planarization treatment in the subsequent step of planarizing the top dielectric material layer 7, so that the problem of planarization treatment rate difference caused by different pattern densities of all areas is reduced, and the flatness and the height consistency of the top of the interlayer dielectric layer are improved.

However, in the step of etching the bottom dielectric material layer 5 with a certain thickness, the first etching stop layer 4 located on the sidewall of the dummy gate structure 2 is easily damaged, so that it is difficult to ensure the protective effect of the first etching stop layer 4 on the gate structure formed subsequently in the subsequent process, the probability of damage to the gate structure is high, and the performance of the formed semiconductor structure is poor.

Referring to fig. 8, an electron microscope scanning image of a semiconductor structure is shown, and it can be seen that the first etch stop layer 4 suffers from large loss, so that it is difficult to protect the sidewalls of the gate structure, and the formed semiconductor structure is not well formed.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a pseudo gate structure is formed on the substrate, and a hard mask layer is formed on the top of the pseudo gate structure; forming an etching stop layer which conformally covers the top and the side wall of the hard mask layer, the side wall of the pseudo gate structure and the substrate exposed by the pseudo gate structure; forming a dielectric material layer on the substrate exposed out of the pseudo gate structure, wherein the dielectric material layer covers the etching stop layer positioned on the hard mask layer; taking the highest position at the top of the etching stop layer as a stop position, and performing first planarization treatment on the dielectric material layer; after the first planarization treatment, etching the etching stop layer and the dielectric material layer to remove the etching stop layer and the dielectric material layer which are higher than the top of the hard mask layer; and after the etching treatment, performing second planarization treatment on the dielectric material layer and the hard mask layer by taking the top of the pseudo-gate structure as a stop position, and taking the residual dielectric material layer as an interlayer dielectric layer.

In the embodiment of the invention, the highest position at the top of the etching stop layer is taken as a stop position, and the medium material layer is subjected to the first planarization treatment, so that in the step of the first planarization treatment, only the medium material layer is subjected to the first planarization treatment without contacting other film layer structures, the problem of grinding amount difference caused by different pattern densities of all regions or different heights of the top surfaces of all the film layer structures is favorably prevented, the probability of the dishing problem at the top of the medium material layer is reduced, the height consistency of the top of the medium material layer after the first planarization treatment is better, the thickness of the medium material layer required to be removed in the subsequent etching treatment can be reduced, the process time required by the etching treatment is shorter, and different materials are easily removed in the same step at similar etching rates by adopting an anisotropic etching process, the method is favorable for reducing the difference of the etching amount of the etching treatment on the dielectric material layers in different pattern density areas, so that the top parts of the residual dielectric material layers are better in height consistency after the etching treatment is finished, and the method is also favorable for reducing the probability of the loss problem of the etching stop layer on the side wall of the pseudo gate structure caused by the difference of the etching amount of the dielectric material layers, thereby ensuring the protective effect of the etching stop layer on the side wall of the formed gate structure in the subsequent process and preventing the loss of the side wall of the gate structure; in summary, the embodiment of the invention combines the first planarization treatment and the etching treatment, and can reduce the probability of damage to the gate structure while improving the flatness of the top surface of the interlayer dielectric layer, thereby improving the performance of the semiconductor structure.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 9 to 19 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 9, a substrate 100 is provided, a dummy gate structure 101 is formed on the substrate 100, and a hard mask layer 102 is formed on the top of the dummy gate structure 101.

The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.

In this embodiment, the substrate 100 is used for forming a planar transistor, and the substrate 100 only includes a substrate (not shown). In other embodiments, when the base is used for forming a finfet, the base comprises a substrate and a fin protruding from the substrate.

In this embodiment, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.

The dummy gate structure 101 is used for occupying a space position for a subsequently formed gate structure.

In this embodiment, the dummy gate structure 101 is a polysilicon gate structure, and the dummy gate structure 101 correspondingly includes a dummy gate oxide layer 1011 located on the substrate 100 and a dummy gate layer 1012 located on the dummy gate oxide layer 1011.

The material of the dummy gate layer 1012 may be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. The material of the dummy gate oxide layer 1011 may be silicon oxide or silicon oxynitride. In this embodiment, the material of the dummy gate layer 1012 is polysilicon. The material of the dummy gate oxide layer 1011 is silicon oxide.

In other embodiments, the dummy gate structure may further include only a dummy gate layer.

In this embodiment, a sidewall 103 is further formed on the sidewall of the dummy gate structure 101. The side wall 103 is used for protecting the side wall of the pseudo gate structure 101, and the side wall 103 is also used for defining a formation region of a source-drain doped layer.

The material of the sidewall 103 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, boron nitride, and boron carbonitride.

The sidewall spacers 103 may have a single-layer structure or a stacked structure. In this embodiment, the sidewall spacer 103 has a stacked structure.

Specifically, the sidewall 103 is an Oxide Nitride Oxide (ONO) structure, and the sidewall 103 includes a first sidewall (not shown) located on a sidewall of the dummy gate structure 101, a second sidewall (not shown) located on the first sidewall, and a third sidewall (not shown) located on the second sidewall. Correspondingly, the first side wall is made of silicon oxide, the second side wall is made of silicon nitride, and the third side wall is made of silicon oxide.

It should be noted that in the integrated circuit design, different film structures may be formed on the sidewalls and the top surface of the dummy gate structure 101 of different devices according to the design requirements. For example: in this embodiment, the substrate 100 includes an NMOS device region (not labeled) and a PMOS device region (not labeled), and a low dielectric constant layer 1051 and an N/P interface layer 1052 on the top surface and the sidewall of the dummy gate structure 101 on the substrate at the interface between the NMOS device region and the PMOS device region are further formed on the top surface and the sidewall of the dummy gate structure, respectively. Wherein the low k layer 1051 is used to reduce the leakage current of the device, and the N/P interface layer 1052 is used to define the boundary between the NMOS device region and the PMOS device region.

The hard mask layer 102 is used as an etching mask for forming the dummy gate structure 101, and the hard mask layer 102 is also used for protecting the top of the dummy gate structure 101 in a subsequent process.

The subsequent process further comprises: forming an etching stop layer which conformally covers the top and the side wall of the hard mask layer 102, the side wall of the pseudo gate structure 101 and the substrate 100 exposed by the pseudo gate structure 101; forming a dielectric material layer on the substrate 100 exposed by the pseudo gate structure 101, wherein the dielectric material layer covers the etching stop layer on the hard mask layer 102; taking the highest position at the top of the etching stop layer as a stop position, and performing first planarization treatment on the dielectric material layer; and after the first planarization treatment, etching the etching stop layer and the dielectric material layer by adopting an anisotropic etching process to remove the etching stop layer and the dielectric material layer which are higher than the top of the hard mask layer 102.

The hard mask layer 102 is used for defining an etching stop position in a subsequent step of performing etching processing on the etching stop layer and the dielectric material layer.

In this embodiment, the hard mask layer 102 includes a bottom hard mask layer 1021 and a top hard mask layer 1022 located on the bottom hard mask layer 1021, where the bottom hard mask layer 1021 is made of silicon nitride, and the top hard mask layer 1022 is made of silicon oxide.

In the subsequent step of etching the etch stop layer and the dielectric material layer 107, the top surface of the top hard mask layer 1022 is used to define the etch stop location. The top hard mask layer 1022 is made of silicon oxide, and the silicon oxide has good adhesion with other material films, so that the subsequent film layer can be formed conveniently.

The method further includes a step of performing a third planarization process, wherein the bottom hard mask layer 1021 is used for defining a stop position of the third planarization process, so as to improve the flatness of the top surface of the material layer to be polished after the third planarization process. The bottom hard mask layer 1021 is made of silicon nitride, the density and hardness of the silicon nitride are high, and the function of defining a stop position of the third planarization treatment is obvious.

In this embodiment, an active drain doping layer 104 is further formed in the substrate 100 on both sides of the dummy gate structure 101. Specifically, the source-drain doping layer 104 is located in the substrate 100 at two sides of the dummy gate structure 101.

When an NMOS transistor is formed, the source-drain doped layer 104 comprises a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, and therefore carrier mobility of the NMOS transistor is improved, wherein the N-type ions are P ions, As ions or Sb ions; when a PMOS transistor is formed, the source-drain doping layer 104 comprises a stress layer doped with P-type ions, the stress layer is made of Si or SiGe, and the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, so that the carrier mobility of the PMOS transistor is improved, wherein the P-type ions are B ions, Ga ions or In ions.

Referring to fig. 10, an etch stop layer 106 is formed to conformally cover the top and sidewalls of the hard mask layer 102, the sidewalls of the dummy gate structure 101, and the substrate 100 exposed by the dummy gate structure 101. Specifically, the etch stop layer 106 conformally covers the top and the sidewall of the hard mask layer 102, the sidewall of the dummy gate structure 101, and the source-drain doping layer 104.

The Etch Stop Layer 106 is a Contact Etch Stop Layer (CESL). The etching stop layer 106 located on the top surface of the source-drain doping layer 104 is used for defining an etching stop position in a subsequent contact hole etching process, so that the damage of the contact hole etching process to the source-drain doping layer 104 is reduced; the etching stop layer 106 located on the sidewall of the dummy gate structure 101 is used for protecting the dummy gate structure 101 in a subsequent process, and after a gate structure is formed at the dummy gate structure 101 in a subsequent process, the etching stop layer 106 is also used for protecting the gate structure in the subsequent process.

In this embodiment, the material of the etch stop layer 106 is silicon nitride. The silicon nitride material has a relatively high density and a relatively high hardness, so that the etching stop layer 106 can be ensured to have the function of defining the etching stop position and the corresponding protection function.

In this embodiment, the etch stop Layer 106 is formed by an Atomic Layer Deposition (ALD) process. The atomic layer deposition process has better step coverage capability, and is favorable for enabling the etching stop layer 106 to conformally cover the top and the side wall of the hard mask layer 102, the side wall of the pseudo gate structure 101 and the substrate 100 exposed by the pseudo gate structure 101; furthermore, the atomic layer deposition process includes multiple atomic layer deposition cycles to form a thin film with a desired thickness, which is beneficial to improving the thickness uniformity and compactness of the etch stop layer 106.

It should be noted that, in this embodiment, the low dielectric constant layer 1051 and the N/P interface layer 1052 located on the top surface and the sidewall of the dummy gate structure 101 at the boundary between the first device region and the second device region are formed, so in the step of forming the etch stop layer 106, the etch stop layer 106 also conformally covers the N/P interface layer 1052. After the etch stop layer 106 is formed, the top surface of the etch stop layer 106 has different heights.

Referring to fig. 11, a dielectric material layer 107 is formed on the substrate 100 exposed by the dummy gate structure 101, and the dielectric material layer 107 covers the etch stop layer 106 on the hard mask layer 102.

The dielectric material layer 107 is used for forming an interlayer dielectric layer subsequently, so that isolation between adjacent devices is realized.

Therefore, the material of the dielectric material layer 107 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the dielectric material layer 107 has a single-layer structure, and the material of the dielectric material layer 107 is silicon oxide.

In this embodiment, the dielectric material layer 107 is formed by a Flowable Chemical Vapor Deposition (FCVD) process. The flowable chemical vapor deposition process has good filling capacity, is suitable for filling openings with high aspect ratios, is favorable for reducing the probability of defects such as cavities and the like in the dielectric material layer 107, and is correspondingly favorable for improving the film quality of a subsequent interlayer dielectric layer.

Referring to fig. 12, a first planarization process is performed on the dielectric material layer 107 with the highest position on the top of the etch stop layer 106 as a stop position.

It should be noted that the top surface of the etch stop layer 106 has different heights, and the highest position of the top of the etch stop layer 106 refers to the farthest distance from the top surface of the etch stop layer 106 to the surface of the substrate 100 along the direction perpendicular to the surface of the substrate 100.

By taking the highest position at the top of the etching stop layer 106 as a stop position, the dielectric material layer 107 is subjected to the first planarization treatment, so that in the first planarization treatment step, only the dielectric material layer 107 is subjected to the first planarization treatment without contacting other film layer structures, the problem of grinding amount difference caused by different pattern densities of all regions or different heights of the top surfaces of all the film layer structures is favorably prevented, the probability of the top of the residual dielectric material layer 107 having a sinking problem is reduced, the height consistency of the top of the dielectric material layer 107 subjected to the first planarization treatment is better, and the height consistency of the top of the subsequent interlayer dielectric layer is favorably improved correspondingly.

And the following process also comprises the step of etching the etching stop layer 106 and the dielectric material layer 107 to remove the etching stop layer 106 and the dielectric material layer 107 which are higher than the top of the hard mask layer 102, compared with the scheme of directly etching the dielectric material layer without the first planarization treatment, the thickness of the dielectric material layer 107 to be removed in the following etching treatment is reduced through the first planarization treatment, so that the process time required by the etching treatment is shorter, the difference of the etching treatment on the etching amount of the dielectric material layer 107 in different pattern density areas is favorably reduced, the height consistency of the top of the following interlayer dielectric layer is favorably improved, the probability of the loss problem of the etching stop layer 106 on the side wall of the pseudo gate structure 101 caused by the difference of the etching amount of the dielectric material layer 107 is favorably reduced, and the protection effect of the etching stop layer 106 on the side wall of the formed gate structure 101 in the following process is ensured, and the etching stop layer 106 has the protection effect on the side wall of the formed gate structure And the side wall of the gate structure 101 is prevented from being lost, so that the performance of the semiconductor structure is improved.

In this embodiment, a low dielectric constant layer 1051 and an N/P interface layer 1052 located on the top surface and the sidewall of the dummy gate structure 101 at the boundary between the first device region and the second device region are formed, and therefore, the highest position on the top of the etch stop layer 106 refers to the top of the etch stop layer 106 located on the top of the N/P interface layer 1052.

In this embodiment, the first planarization process is performed by a chemical-mechanical Polishing (CMP) process. By adopting the chemical mechanical polishing process, the highest position at the top of the etching stop layer 106 is favorably and accurately positioned, so that the stop position of the first planarization treatment is accurately controlled, the process difficulty of the first planarization treatment is reduced, and the flatness of the top surface of the dielectric material layer 107 after the first planarization treatment is further favorably improved.

Specifically, in the process of performing the first planarization treatment by using a chemical mechanical polishing process, an End Point Detection (EPD) mode is used, and the highest position on the top of the etch stop layer 106 is used as a polishing stop position.

In other embodiments, the first planarization process may further include performing an etchback (etchback) and a chemical mechanical polishing (cmp) process in sequence.

Referring to fig. 13, after the first planarization treatment, the etching stop layer 106 and the dielectric material layer 107 are etched, and the etching stop layer 106 and the dielectric material layer 107 higher than the top of the hard mask layer 102 are removed.

By adopting the etching treatment mode, different materials can be easily removed in the same step at similar etching rates, and the difference of etching treatment on the etching amount of the dielectric material layer 107 in different pattern density areas is favorably reduced, so that after the etching treatment is finished, the height consistency of the top of the residual dielectric material layer 107 is better, the probability of the loss problem of the etching stop layer 106 on the side wall of the pseudo gate structure 101 caused by the etching amount difference of the dielectric material layer 107 is favorably reduced, the protection effect of the etching stop layer 106 on the side wall of the formed gate structure in the subsequent process is ensured, and the loss of the side wall of the gate structure is prevented.

In this embodiment, the etch stop layer 106 and the dielectric material layer 107 above the top of the top hard mask layer 1022 are removed. The top hard mask layer 1022 is used for defining an etching stop position in the step of performing etching processing on the etching stop layer 106 and the dielectric material layer 107, so as to improve the height consistency of the top of the dielectric material layer 107 after the etching processing.

Moreover, the top hard mask layer 1022 is made of silicon oxide, and the silicon oxide layer has high adhesion with other film layers, so that other film layers can be formed on the top hard mask layer 1022 and the dielectric material layer 107 in a subsequent step, and accordingly, the quality of the subsequent formed film layer can be improved.

In this embodiment, the etching process is performed by using a Siconi process. The Siconi process, as a low-intensity high-precision chemical etching method, generally comprises the steps of: firstly, generating etching gas; etching the material layer to be etched by the etching gas to form a byproduct; carrying out an annealing process to sublimate and decompose the by-product into a gaseous product; and removing the gaseous product by air suction.

In this embodiment, the etching of the Siconi processThe etching gas comprises C_xF_yGas and C_xH_yF_zA gas.

The adoption of the Siconi process is easy to enable the etching treatment to be relatively close to the etching rates of the silicon nitride material and the silicon oxide material, so that the etching stop layer 106 and the medium material layer 107 which are higher than the top of the hard mask layer 102 can be removed in the same step, and the adoption of the Siconi process is also beneficial to improving the etching load effect of the etching treatment, so that the height consistency of the top surface of the medium material layer 107 after the etching treatment is further improved; in addition, the Siconi process is easy to obtain higher etching selection ratio, and is beneficial to reducing the probability of damage of other film structures in the step of etching treatment.

In other embodiments, the etching process may be performed by a dry etching process according to actual process requirements.

The bias voltage of the Siconi process is not too small and not too large. If the bias voltage is too small, the plasma concentration of the etching treatment is easily reduced, so that the etching rate is reduced; if the bias voltage is too large, the uniformity of the etching rate is easily reduced, thereby reducing the uniformity of the height of the top surface of the dielectric material layer 107 after the etching process. For this reason, in the present embodiment, the bias voltage of the Siconi process is 15 to 25 volts.

In this embodiment, in the step of performing the etching treatment, by reasonably setting process parameters of the etching treatment, the height difference of the top surfaces of the dielectric material layers 107 in each region after the etching treatment is performed is smaller than 10nm, so as to improve the height consistency of the top surfaces of the dielectric material layers 107.

In this embodiment, in the step of removing the etching stop layer 106 and the dielectric material layer 107 above the top of the hard mask layer 102, the N/P interface layer 1052 and the low dielectric constant layer 1051 above the top of the hard mask layer 102 are also removed.

In this embodiment, after the etching, the method further includes:

referring to fig. 14, a cross-sectional view of the semiconductor structure along the extending direction of the dummy gate structure 101 is shown, and in this embodiment, after the etching process, the method further includes: and cutting off the dummy gate structure 101 by an etching process, and forming openings 200 exposing the substrate 100 in the dielectric material layer 107, wherein the openings 200 are distributed in the extending direction of the dummy gate structure 101.

By performing the cutting-off processing on the dummy gate structure 101, the unnecessary dummy gate structure 101 is removed, so that the layout of the dummy gate structure 101 meets the design requirement of the integrated circuit.

In this embodiment, the step of forming the opening 200 includes: forming a mask pattern layer 108 on the hard mask layer 102; and cutting off the pseudo gate structure 101 by using the mask pattern layer 108 as a mask and adopting a dry etching process, and forming an opening 200 exposing the substrate 100 in the dielectric material layer 107.

In this embodiment, the mask pattern layer 108 is made of silicon oxide, the mask pattern layer 108 is formed on the top hard mask layer 1022, and the adhesion between the mask pattern layer 108 and the top hard mask layer 1022 is good, which is beneficial to improving the process effect of pattern transfer.

The dry etching process has anisotropic etching characteristics, and is beneficial to improving the precision of pattern transfer and enabling the profile of the opening 200 to meet the process requirements.

Referring to fig. 15 to 17, an isolation material layer 111 (as shown in fig. 17) is formed to fill the opening 200, and the isolation material layer 111 further covers the dielectric material layer 107 and the hard mask layer 102.

By filling the isolating material layer 111 in the opening 200, the remaining dummy gate structures 101 are isolated from each other in the extending direction of the dummy gate structure 101, and after a gate structure is formed at the position of the dummy gate structure 101, the isolating material layer 111 in the opening 200 can also electrically isolate the gate structures at two sides of the opening 200.

Therefore, the material of the isolation material layer 111 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the isolation material layer 111 has a single-layer structure, and the isolation material layer 111 is made of silicon oxide.

In this embodiment, the isolation material layer 111 is formed by a flowable chemical vapor deposition process, which is beneficial to reducing the probability of defects such as voids formed in the isolation material layer 111.

Specifically, the isolation material layer 111 covers the mask pattern layer 108.

In this embodiment, with reference to fig. 15 to fig. 16, after forming the opening 200 and before forming the isolation material layer 111, the method further includes: a protective layer 110 is formed on the sidewalls of the opening 200.

After the dielectric material layer 107 higher than the top of the dummy gate structure 101 is subsequently removed to form an interlayer dielectric layer, the method further includes: removing the dummy gate structure 101, and forming a gate opening in the dielectric material layer 107; and forming a gate structure in the gate opening. The protection layer 110 is used to protect the isolation material layer 111 located in the opening 200 during the step of forming the gate opening, so as to reduce the probability of damage to the isolation material layer 111 located in the opening 200.

In this embodiment, the material of the protection layer 110 is silicon nitride. The silicon nitride has high density and hardness, which is beneficial to ensuring the protective effect of the protective layer 110 on the isolation material layer 111.

Specifically, the step of forming the protective layer 110 includes: forming a protective material layer 109 conformally covering the bottom and sidewalls of the opening 200 and the top of the hard mask layer 102 and the dielectric material layer 107 (as shown in fig. 15); and removing the protective material layer 109 at the tops of the hard mask layer 102 and the dielectric material layer 107 and at the bottom of the opening 200 by using an anisotropic etching process, and reserving the residual protective material layer 109 on the side wall of the opening 200 as the protective layer 110.

By conformally covering the bottom and the side walls of the opening 200 and the tops of the hard mask layer 102 and the dielectric material layer 107 by the protective material layer 109, the protective material layer 109 on the tops of the hard mask layer 102 and the dielectric material layer 107 and on the bottom of the opening 200 can be removed by a maskless etching process, so that a photomask is not required in the process for forming the protective layer 110, and the process cost is reduced.

In this embodiment, the protective material layer 109 is formed by an atomic layer deposition process. The atomic layer deposition process is favorable for improving the conformal covering capability of the protective material layer 109, so that the protective material layer can be formed on the side wall of the opening 200, and the atomic layer deposition process is also favorable for improving the thickness uniformity and density of the protective material layer 109, so as to be favorable for ensuring the protective effect of the protective material layer 109 on the isolation material layer 111 located in the opening 200.

The anisotropic etching process in this embodiment is a dry etching process. The dry etching process is easy to implement anisotropic etching, and is beneficial to reducing damage to the protective material layer 109 on the sidewall of the opening 200, so that the protective layer 110 can have a corresponding protective effect.

Referring to fig. 18, a third planarization process is performed on the isolation material layer 111 and the dielectric material layer 107 with the top of the hard mask layer 102 as a stop position.

In this embodiment, the isolation material layer 111 and the bottom hard mask layer 1021 are made of different materials, so that in the step of the third planarization process, the bottom hard mask layer 1021 is used as a stop position, which is beneficial to improving the top height uniformity of the isolation material layer 111 after the third planarization process.

In this embodiment, the third planarization process is performed by using a chemical mechanical polishing process.

Specifically, the top of the bottom hard mask layer 1021 is used as a polishing stop by End Point Detection (EPD).

Referring to fig. 19, after the etching process is performed, with the top of the dummy gate structure 101 as a stop position, a second planarization process is performed on the dielectric material layer 107 and the hard mask layer 102, and the remaining dielectric material layer 107 is used as an interlayer dielectric layer 120.

As can be seen from the foregoing, the top height of the dielectric material layer 107 after the first planarization treatment and the etching treatment has good uniformity, so that the uniformity of the polishing rate in the step of performing the second planarization treatment is good, and after the interlayer dielectric layer 120 is formed, the top height uniformity of the interlayer dielectric layer 120 is improved.

Moreover, the second planarization process has a better polishing rate uniformity, and is also beneficial to reducing the probability of damage to the etching stop layer 106 on the side wall of the dummy gate structure 101 in the second planarization process, so that after a gate structure is formed at the position of the dummy gate structure 101 in the following process, the etching stop layer 106 can play a corresponding protection effect on the gate structure in the following process, the probability of loss to the side wall of the gate structure is reduced, and the performance of the semiconductor structure is improved.

In this embodiment, the second planarization treatment is performed by a chemical mechanical polishing process. The chemical mechanical polishing process is favorable for accurately positioning the stop position of the second planarization treatment, reducing the process difficulty of the second planarization treatment and further improving the flatness of the top surface of the interlayer dielectric layer 120.

Specifically, in the process of performing the second planarization treatment by using a chemical mechanical polishing process, an end point detection mode is adopted, and the top of the dummy gate structure 101 is used as a polishing stop position.

In this embodiment, an isolation material layer 111 (as shown in fig. 18) is further formed on the substrate 100 and located in the opening 200 (as shown in fig. 18), and the top of the isolation material layer 111 is higher than the top of the dummy gate structure 101, so that in the step of performing the second planarization process, the isolation material layer 111 is further subjected to the second planarization process, and the remaining isolation material layer 111 after the second planarization process is used as an isolation structure (not shown).

After the gate structures are formed at the positions of the dummy gate structures 101, the isolation structures are used for realizing electrical isolation between adjacent gate structures along the extension direction of the gate structures.

Correspondingly, the invention also provides a semiconductor structure formed by adopting the method.

Therefore, the top height consistency of the interlayer dielectric layer formed by the method is good, and the etching stop layer on the dummy gate structure is less in loss, so that the protection effect of the etching stop layer on the side wall of the subsequent gate structure is favorably ensured, and the probability of loss of the side wall of the gate structure in the subsequent process is reduced. In summary, the performance of the semiconductor structure formed by the method is improved.

The semiconductor structure may be formed by using the formation method described in the foregoing embodiment. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.