阅读说明：本技术 电容阵列电路、充放电电路及rc振荡电路 (Capacitor array circuit, charging and discharging circuit and RC oscillation circuit ) 是由 杨江 华超 凌秋蝉 于 2020-09-02 设计创作，主要内容包括：本申请公开了一种电容阵列电路,包括N个电容及与N个电容一一对应的N个MOS管,每个MOS管的漏极通过不同的金属线与对应的电容的一端连接,每个MOS管的源极接地,每个MOS管的栅极用于接收控制信号以分别控制每个MOS管的导通和截止；N个电容的另一端连接至一公共端；N个电容中的第n-1个电容的容值Cn-1为第n个电容的容值Cn的a倍；N个MOS管中的第n-1个MOS管的导通电阻和第n-1个电容与第n-1个MOS管之间的金属线的电阻之和为第n个MOS管的导通电阻和第n个电容与第n个MOS管之间的金属线的电阻之和的a倍。(The application discloses a capacitor array circuit, which comprises N capacitors and N MOS tubes in one-to-one correspondence with the N capacitors, wherein the drain electrode of each MOS tube is connected with one end of the corresponding capacitor through different metal wires, the source electrode of each MOS tube is grounded, and the grid electrode of each MOS tube is used for receiving a control signal to respectively control the conduction and the cut-off of each MOS tube; the other ends of the N capacitors are connected to a common end; the capacitance value Cn-1 of the (N-1) th capacitor in the N capacitors is a times of the capacitance value Cn of the nth capacitor; the sum of the on-resistance of the (N-1) th MOS tube in the N MOS tubes and the resistance of the metal wire between the (N-1) th capacitor and the (N-1) th MOS tube is a times of the sum of the on-resistance of the N-th MOS tube and the resistance of the metal wire between the N-th capacitor and the N-1 th MOS tube.)

1. A capacitive array circuit, comprising:

n capacitors;

the N MOS tubes correspond to the N capacitors one by one, wherein the drain electrode of each MOS tube in the N MOS tubes is connected with one end of the corresponding capacitor through different metal wires, the source electrode of each MOS tube is grounded, and the grid electrode of each MOS tube is used for receiving a control signal to respectively control the conduction and the cut-off of each MOS tube;

the other ends of the N capacitors are connected to a common end, and the common end is used as a capacitor output end;

the capacitance value of the (N-1) th capacitor in the N capacitors is Cn-1, the capacitance value of the nth capacitor is Cn, and Cn = aCn-1;

the on-resistance of the (N-1) th MOS tube in the N MOS tubes is R_onn-1The on-resistance of the nth MOS transistor is R_onn；

The resistance of the metal wire between the (n-1) th capacitor and the (n-1) th MOS tube is R_netn-1The resistance of the metal wire between the nth capacitor and the nth MOS tube is R_netn；

Wherein R is_netn-1And R_onn-1The sum is greater than or equal to R_netnAnd R_onnA times of the sum, wherein a is greater than 1, N is an integer greater than or equal to 2, N = [2, N =]。

2. The capacitor array circuit of claim 1, wherein a ratio of a width to a length of the n-1 th MOS transistor is Mn-1, a ratio of a width to a length of the n-th MOS transistor is Mn, a ratio of a width to a length of the n-th MOS transistor Mn is b times the ratio of a width to a length of the n-1 th MOS transistor Mn-1, b = a, and a resistance R of the metal line between the n-1 th capacitor and the n-1 th MOS transistor_netn-1Greater than or equal to the resistance R of the metal wire between the nth capacitor and the nth MOS tube_netnA times of.

3. The capacitive array circuit of claim 2, wherein a = b =2, and the resistance R of the metal line between the (n-1) th capacitor and the (n-1) th MOS transistor_netn-1Greater than or equal to the resistance R of the metal wire between the nth capacitor and the nth MOS tube_netn2 times of the total weight of the powder.

4. The capacitor array circuit of claim 1, wherein the metal line between the nth capacitor and the nth MOS transistor is a^n-1Each capacitor is connected with the metal wire between the corresponding MOS tube in parallel; wherein a is an integer greater than 1.

5. The capacitor array circuit of claim 1, wherein the number of metal lines between the (n-1) th capacitor and the (n-1) th MOS transistor is 1 andthe resistance of the metal wire is R_netn-1The number of metal wires between the nth capacitor and the nth MOS transistor is 1, and the resistance of the metal wire is R_netnResistance R of metal wire between n-1 th capacitor and n-1 th MOS tube_netn-1Is the resistance R of the metal wire between the nth capacitor and the nth MOS tube_netnA times of.

6. The capacitive array circuit of claim 1, wherein the control signal is a pulsed signal.

7. A capacitor charging and discharging circuit, comprising the capacitor array circuit of any one of claims 1-6, a power source, a first electronic switch, a first resistor, and a second electronic switch; the first end of the first electronic switch is connected with the power supply, the second end of the first electronic switch is respectively connected with the first end of the second electronic switch and the capacitor output end through the resistor, the second end of the second electronic switch is grounded, the control end of the first electronic switch and the control end of the second electronic switch are respectively used for receiving a clock signal, and the first electronic switch and the second electronic switch are switched on and off based on the clock signal.

8. The capacitor charging and discharging circuit of claim 7, wherein the first electronic switch is a PMOS transistor and the second electronic switch is an NMOS transistor.

9. An RC oscillation circuit, characterized by comprising a first charge-discharge circuit, a second charge-discharge circuit, a first comparator, a second comparator, a reference voltage unit, a logic unit and a control unit, wherein the first charge-discharge circuit and the second charge-discharge circuit are respectively the capacitor charge-discharge circuit as claimed in any one of claims 7 to 8; a first input end of the first comparator is connected with a capacitor output end of the first charge-discharge circuit, and a second input end of the first comparator is connected with the reference voltage unit; a first input end of the second comparator is connected with a capacitor output end of the second charge-discharge circuit, and a second input end of the second comparator is connected with the reference voltage unit; the output end of the first comparator and the output end of the second comparator are both connected with the input end of the logic unit, and the output end of the logic unit is respectively connected with the control end of the first electronic switch and the control end of the second electronic switch; the control unit is respectively connected with the grid electrode of each MOS tube;

the reference voltage unit is used for generating a reference voltage;

the first charging and discharging circuit is used for transmitting a first charging voltage or a first discharging voltage to the first comparator;

the first comparator is used for comparing the first charging voltage with the reference voltage or comparing the first discharging voltage with the reference voltage and outputting a first comparison result to the logic unit;

the second charging and discharging circuit is used for transmitting a second charging voltage or a second discharging voltage to the second comparator;

the second comparator is used for comparing the second charging voltage with the reference voltage or comparing the second discharging voltage with the reference voltage and outputting a second comparison result to the logic unit;

the logic unit is used for outputting a clock signal according to the first comparison result and the second comparison result;

the first charge-discharge circuit and the second charge-discharge circuit are used for charging and discharging according to the clock signal;

the control unit is used for controlling the on and off of the MOS tube through a control signal so as to adjust the total capacitance of the capacitor array circuit.

10. The RC oscillation circuit of claim 9, wherein the logic cell is an RS flip-flop.

Technical Field

The present disclosure relates to integrated circuits, and particularly to a capacitor array circuit, a charging/discharging circuit, and an RC oscillation circuit.

Background

Electronic devices typically employ an oscillator to generate the required clock signal. Oscillators are of various types, and RC oscillators have been widely used because of their advantages of low cost, low power consumption, adjustable frequency, etc. However, the RC oscillator is sensitive to parasitic parameters, which are related to layout design, process and temperature of the RC oscillator, and thus, the output frequency error of the RC oscillator is large.

The RC oscillator generally adopts a capacitor array circuit to adjust the output frequency, but the conventional capacitor array circuit often ignores the influence of parasitic resistance on the total capacitance of the capacitor array circuit, so that the adjustment of the capacitor array circuit on the output frequency of the RC oscillator is non-monotonicity, and the output frequency error of the RC oscillator is large.

Disclosure of Invention

In order to overcome the problems in the prior art, the present application provides a capacitor array circuit, a charge/discharge circuit, and an RC oscillation circuit, which can achieve monotonicity adjustment of an output frequency of an RC oscillator, thereby improving accuracy of the output frequency of the RC oscillator.

In order to achieve the above purpose, the following technical solutions are specifically adopted in the present application:

the application provides a capacitive array circuit, including:

n capacitors;

the N MOS tubes correspond to the N capacitors one by one, wherein the drain electrode of each MOS tube in the N MOS tubes is connected with one end of the corresponding capacitor through different metal wires, the source electrode of each MOS tube is grounded, and the grid electrode of each MOS tube is used for receiving a control signal to respectively control the conduction and the cut-off of each MOS tube;

the other ends of the N capacitors are connected to a common end, and the common end is used as a capacitor output end;

the capacitance value of the (N-1) th capacitor in the N capacitors is Cn-1, the capacitance value of the nth capacitor is Cn, and Cn = aCn-1;

the on-resistance of the (N-1) th MOS tube in the N MOS tubes is R_onn-1The on-resistance of the nth MOS transistor is R_onn；

The resistance of the metal wire between the (n-1) th capacitor and the (n-1) th MOS tube is R_netn-1The resistance of the metal wire between the nth capacitor and the nth MOS tube is R_netn；

Wherein R is_netn-1And R_onn-1The sum is greater than or equal to R_netnAnd R_onnA times of the sum, wherein a is greater than 1, N is an integer greater than or equal to 2, N = [2, N =]。

Preferably, the ratio of the width to the length of the n-1 th MOS tube is Mn-1, the ratio of the width to the length of the n-th MOS tube is Mn, the ratio of the width to the length of the n-th MOS tube Mn is b times of the ratio of the width to the length of the n-1 th MOS tube Mn-1, b = a, and the resistance R of the metal wire between the n-1 st capacitor and the n-1 st MOS tube_netn-1Greater than or equal to the resistance R of the metal wire between the nth capacitor and the nth MOS tube_netnA times of.

Preferably, a = b =2, resistance R of the metal line between the (n-1) th capacitor and the (n-1) th MOS transistor_netn-1Greater than or equal to the resistance R of the metal wire between the nth capacitor and the nth MOS tube_netn2 times of the total weight of the powder.

Preferably, the metal line between the nth capacitor and the nth MOS tube is a^n-1Each capacitor is connected with the metal wire between the corresponding MOS tube in parallel; wherein a is an integer greater than 1.

Preferably, the number of metal wires between the (n-1) th capacitor and the (n-1) th MOS transistor is 1, and the resistance of the metal wire is R_netn-1The number of metal wires between the nth capacitor and the nth MOS transistor is 1, and the resistance of the metal wire is R_netnResistance R of metal wire between n-1 th capacitor and n-1 th MOS tube_netn-1Is the resistance R of the metal wire between the nth capacitor and the nth MOS tube_netnA times of.

Preferably, the control signal is a binary signal.

The application also provides a capacitor charging and discharging circuit, which comprises the capacitor array circuit, a power supply, a first electronic switch, a first resistor and a second electronic switch; the first end of the first electronic switch is connected with the power supply, the second end of the first electronic switch is respectively connected with the first end of the second electronic switch and the capacitor output end through the resistor, the second end of the second electronic switch is grounded, the control end of the first electronic switch and the control end of the second electronic switch are respectively used for receiving a clock signal, and the first electronic switch and the second electronic switch are switched on and off based on the clock signal.

Preferably, the first electronic switch is a PMOS transistor, and the second electronic switch is an NMOS transistor.

The application provides an RC oscillation circuit, which comprises a first charging and discharging circuit, a second charging and discharging circuit, a first comparator, a second comparator, a reference voltage unit, a logic unit and a control unit, wherein the first charging and discharging circuit and the second charging and discharging circuit are the capacitor charging and discharging circuits respectively; a first input end of the first comparator is connected with a capacitor output end of the first charge-discharge circuit, and a second input end of the first comparator is connected with the reference voltage unit; a first input end of the second comparator is connected with a capacitor output end of the second charge-discharge circuit, and a second input end of the second comparator is connected with the reference voltage unit; the output end of the first comparator and the output end of the second comparator are both connected with the input end of the logic unit, and the output end of the logic unit is respectively connected with the control end of the first electronic switch and the control end of the second electronic switch; the control unit is respectively connected with the grid electrode of each MOS tube;

the reference voltage unit is used for generating a reference voltage;

the first charging and discharging circuit is used for transmitting a first charging voltage or a first discharging voltage to the first comparator;

the first comparator is used for comparing the first charging voltage with the reference voltage or comparing the first discharging voltage with the reference voltage and outputting a first comparison result to the logic unit;

the second charging and discharging circuit is used for transmitting a second charging voltage or a second discharging voltage to the second comparator;

the second comparator is used for comparing the second charging voltage with the reference voltage or comparing the second discharging voltage with the reference voltage and outputting a second comparison result to the logic unit;

the logic unit is used for outputting a clock signal according to the first comparison result and the second comparison result;

the first charge-discharge circuit and the second charge-discharge circuit are used for charging and discharging according to the clock signal;

the control unit is used for controlling the on and off of the MOS tube through a control signal so as to adjust the total capacitance of the capacitor array circuit.

Preferably, the logic unit is an RS flip-flop.

Compared with the prior art, the capacitor array circuit, the charge and discharge circuit and the RC oscillation circuit can enable the total capacitance output by the capacitor array circuit to be monotonously changed, and improve the precision of the output frequency of the RC oscillation circuit.

Drawings

For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a schematic block diagram of an RC oscillation circuit according to an embodiment of the present application;

fig. 2 is a schematic block diagram of an RC oscillating circuit according to another embodiment of the present application;

fig. 3 is a circuit diagram of a charging/discharging circuit according to an embodiment of the present disclosure;

FIG. 4 is a circuit diagram of a capacitor array circuit according to an embodiment of the present application;

fig. 5 is a schematic diagram illustrating a connection between a capacitor and a MOS transistor according to an embodiment of the present application;

fig. 6 is a schematic diagram illustrating a connection between a capacitor and a MOS transistor according to another embodiment of the present application;

fig. 7 is a schematic diagram illustrating a connection between a capacitor and a MOS transistor according to yet another embodiment of the present application;

fig. 8 is a schematic diagram illustrating a connection between a capacitor and a MOS transistor according to yet another embodiment of the present application;

fig. 9 is a circuit diagram of an RC oscillating circuit according to an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

In the description of the present application, unless explicitly stated or limited otherwise, the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; the term "plurality" means two or more unless specified or indicated otherwise; the terms "connected," "fixed," and the like are to be construed broadly and may, for example, be fixedly connected, detachably connected, integrally connected, or electrically connected; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

Referring to fig. 1, a conventional RC oscillating circuit generally includes a reference voltage module 11, a charging/discharging module 12, a comparing module 13 and a logic module 14. The input end of the comparison module 13 is connected to the reference voltage module 11 and the charge and discharge module 12, the output end of the comparison module 13 is connected to the input end of the logic module 14, and the output end of the logic module 14 is connected to the charge and discharge module 12. The reference voltage module 11 is used for generating a reference voltage. The charge-discharge module 12 is configured to transmit a charge-discharge voltage to the comparison module 13. The comparison module 13 is configured to compare the reference voltage and the charging/discharging voltage, and output a comparison result to the logic module 14. The logic module 14 is configured to output a clock signal according to the comparison result. The logic module 14 is further configured to feed back a clock signal to the charge and discharge module 12, and the charge and discharge module 12 is configured to perform charging and discharging according to the clock signal. The logic module 14 feeds back the clock signal to the charge and discharge module 12, so that the charge and discharge module 12 is switched from the charge state to the discharge state or from the discharge state to the charge state, and the charge and discharge module 12 performs cyclic charge and discharge, so that the RC oscillation circuit continuously outputs the clock signal.

The charging and discharging module 12 generally includes a capacitor array circuit, and the RC oscillating circuit adjusts the charging and discharging frequency of the charging and discharging module 12 by adjusting the total capacitance of the capacitor array circuit, so as to adjust the frequency of the clock signal output by the RC oscillating circuit. The total capacitance of the capacitor array circuit is the sum of the capacitances of the capacitor array circuit, which are accessed to the charge-discharge module 12 and participate in charge and discharge, and the total capacitance of the capacitor array circuit can be adjusted through the switch. The influence of parasitic resistance on the total capacitance of the capacitor array circuit connected to the charging and discharging module 12 is often ignored in the adjustment of the total capacitance of the conventional capacitor array circuit, so that the adjustment of the frequency of the clock signal output by the RC oscillation circuit is non-monotonicity.

Referring to fig. 2, an embodiment of the present invention provides an RC oscillating circuit, which includes a capacitor charging/discharging circuit 20, a first comparator I1, a second comparator I2, a reference voltage unit 30, a logic unit 40, and a control unit 50. The capacitance charge and discharge circuit 20 includes a first charge and discharge circuit 21 and a second charge and discharge circuit 22. A first input end of the first comparator I1 is connected with a capacitance output end of the first charge-discharge circuit 21, and a second input end of the first comparator I1 is connected with the reference voltage unit 30; a first input end of the second comparator I2 is connected with a capacitance output end of the second charge-discharge circuit 22, and a second input end of the second comparator I2 is connected with the reference voltage unit 30; the output of the first comparator I1 and the output of the second comparator I2 are both connected to the input of the logic unit 40. The output end of the logic unit 40 is connected to the input end of the charging and discharging circuit 20, and specifically, the output end of the logic unit 40 is connected to the input end of the first charging and discharging circuit 21 and the input end of the second charging and discharging circuit 22, respectively.

The reference voltage unit 30 is used to generate a reference voltage. The first charging/discharging circuit 21 is configured to transmit a first charging voltage or a first discharging voltage to the first comparator I1. The clock signal includes a plurality of clock cycles, each clock cycle includes a first half cycle and a second half cycle, the first charging voltage is a voltage output by the first charging and discharging circuit 21 in the first half cycle of each clock cycle, and the first discharging voltage is a voltage output by the first charging and discharging circuit 21 in the second half cycle of each clock cycle. The first comparator I1 is used for comparing the first charging voltage with the reference voltage, or comparing the first discharging voltage with the reference voltage, and outputting the first comparison result to the logic unit 40. The second charging/discharging circuit 22 is configured to transmit a second charging voltage or a second discharging voltage to the second comparator I2. The second discharge voltage is a voltage output by the second charge and discharge circuit 22 in the first half period of each clock cycle, and the second charge voltage is a voltage output by the second charge and discharge circuit 22 in the second half period of each clock cycle. The second comparator I2 is used for comparing the second charging voltage with the reference voltage, or comparing the second discharging voltage with the reference voltage, and outputting the second comparison result to the logic unit 40. The logic unit 40 is configured to output a clock signal according to the first comparison result and the second comparison result. The logic unit 40 is further configured to feed back a clock signal to the first charge/discharge circuit 21 and the second charge/discharge circuit 22, respectively, and the first charge/discharge circuit 21 and the second charge/discharge circuit 22 perform charging and discharging according to the clock signal. The logic unit 40 feeds back the clock signal to the charge and discharge module 12, so that the first charge and discharge circuit 21 and the second charge and discharge circuit 22 are switched from the charge state to the discharge state or from the discharge state to the charge state, and the first charge and discharge circuit 21 and the second charge and discharge circuit 22 perform cyclic charge and discharge, so that the RC oscillation circuit continuously outputs the clock signal.

Referring to fig. 3, as an example, the charging and discharging circuit 20 (such as the charging and discharging module 12 in fig. 1 or the first and second charging and discharging circuits 21 and 22 in fig. 2) includes a capacitor array circuit C, a power source V, a first electronic switch Q1, a first resistor R, and a second electronic switch Q2.

The clock signal includes a plurality of clock cycles, each clock cycle including a first half cycle and a second half cycle. In the first half period of each clock period, the input of the input terminal VIN is at a high level, the first electronic switch Q1 is turned off, the second electronic switch Q2 is turned on, and the charging and discharging circuit 20 discharges; in the second half period of each clock cycle, the input of the input terminal VIN is low, the first electronic switch Q1 is turned on, the second electronic switch Q2 is turned off, and the charging and discharging circuit 20 charges. The level input from the input terminal VIN is changed according to the clock period, so that the charging and discharging circuit 20 alternately charges and discharges.

Referring to fig. 4, as an example, a capacitor array circuit C (such as the capacitor array circuit C in fig. 3) includes N capacitors and N MOS transistors. The N MOS tubes are in one-to-one correspondence with the N capacitors, wherein the drain electrode of each MOS tube in the N MOS tubes is connected with one end of the corresponding capacitor through different metal wires, the source electrode of each MOS tube is grounded, and the grid electrode of each MOS tube is used for receiving a control signal to respectively control the conduction and the cut-off of each MOS tube. The other end of the N capacitors is connected to a common terminal, which is used as the capacitor output terminal Cout of the capacitor array circuit C. Every MOS pipe in the N MOS pipe constitutes a capacitance branch with the electric capacity that corresponds, for example, the 1 st MOS pipe in the N MOS pipe constitutes 1 st capacitance branch with 1 st electric capacity, the 2 nd MOS pipe constitutes 2 nd capacitance branch with 2 nd electric capacity, the N th MOS pipe constitutes N capacitance branch with N th electric capacity, …, analogize with this, and the nth MOS pipe constitutes N capacitance branch with N capacitance promptly. Each MOS tube is controlled by a control signal to conduct and stop, so that whether a capacitor branch where the MOS tube is located is connected to the capacitor array circuit C or not is controlled. Specifically, when the nth MOS transistor is turned on under the control of the control signal, an nth capacitor branch composed of the nth MOS transistor and the nth capacitor is connected in parallel with other capacitor branches, that is, the nth capacitor branch is connected to the capacitor array circuit C. Wherein N is an integer greater than or equal to 2.

The capacitance value of the 1 st capacitor is C1, the capacitance value of the 2 nd capacitor is C2, the capacitance value of the 3 rd capacitor is C3.

The on-resistance of the 1 st MOS tube is R_on1The on-resistance of the 2 nd MOS transistor is R_on2The on-resistance of the 3 rd MOS transistor is R_on3,., the on-resistance of the n-1 MOS transistor is R_onn-1The on-resistance of the nth MOS transistor is R_onn。

The resistance of the metal wire between the 1 st capacitor and the 1 st MOS tube is R_net1The resistance of the metal wire between the 2 nd capacitor and the 2 nd MOS tube is R_net2The resistance of the metal wire between the 3 rd capacitor and the 3 rd MOS tube is R_net3,., the resistance of the metal wire between the (n-1) th capacitor and the (n-1) th MOS tube is R_netn-1The resistance of the metal wire between the nth capacitor and the nth MOS tube is R_netn。

The conventional RC oscillation circuit usually ignores the resistance of the N MOS transistors during conduction and ignores the resistance of the metal line between the capacitor and the MOS transistor, that is, the resistance of the N MOS transistors during conduction and the resistance of the metal line between the capacitor and the MOS transistor are treated as 0 ohm, however, each MOS transistor has a certain on-resistance during conduction, the metal line between the capacitor and the MOS transistor also has a certain resistance, and the parasitic resistance of the RC oscillation circuit includes the on-resistance of each MOS transistor and the resistance of the metal line between each capacitor and the corresponding MOS transistor. The on-resistance of the MOS tube and the resistance of the metal wire between the capacitor and the MOS tube influence the monotonicity of the total capacitance adjustment of the capacitor array circuit C, thereby influencing the monotonicity of the frequency adjustment of the clock signal output by the RC oscillation circuit and causing the frequency error of the clock signal output by the RC oscillation circuit to be larger.

After considering the influence of the parasitic resistance on the total capacitance of the capacitor array circuit C, when the MOS transistors of the N capacitor branches are all turned on, the equivalent capacitances C1 ', C2', C3 ', …, and Cn' of the N capacitor branches are:

and so on,

where f is half the frequency of the clock signal. The capacitance values of the N capacitors in the capacitor array circuit C are usually set in a certain ratio, and when C2= aC1, C3= aC2, C4= aC3, …, Cn-1= aCn-2, and Cn = aCn-1, i.e., C1: c2: c3: c4: …: cn-1: cn = a⁰：a¹：a²：a³：a⁴：…：a^n-2：a^n-1，，

，，…，，That is, after considering the influence of the parasitic resistance on the total capacitance of the capacitor array circuit C, the equivalent capacitances C1 ', C2', C3 ', …, Cn' of the N capacitor branches conform to，，，…，，Time, capacitor array circuit C outputThe total capacitance of (2) is monotonously changed. Wherein a is greater than 1.

When in use

，

，，…，

，

When it is, then

，

，

，…，。

In one embodiment, if the influence of the on-resistance of each MOS transistor in the N MOS transistors on the total capacitance of the capacitor array circuit C is considered, the influence of the resistance of the metal line between each capacitor in the N capacitors and the corresponding MOS transistor on the total capacitance of the capacitor array circuit C is ignored, that is, R is used_net1、R_net2、R_net3、...、R_netn-1、R_netnAll the values of (1) are treated as 0, then

，

，，…，

That is, the capacitance Cn of the nth capacitor is a times of the capacitance Cn-1 of the (n-1) th capacitor, and the on-resistance R of the (n-1) th MOS tube_onn-1On-resistance R of the n-th MOS transistor or more_onnA times higher, the monotonicity of the total capacitance adjustment of the capacitive array circuit C can be improved. Wherein N = [2, N =]。

In one embodiment, if the influence of the resistance of the metal wire between each of the N capacitors and the corresponding MOS transistor on the total capacitance of the capacitor array circuit C is considered, the influence of the on-resistance of each of the N MOS transistors on the total capacitance of the capacitor array circuit C is ignored, that is, R is set_on1、R_on2、R_on3、...、R_onn-1、R_onnAll the values of (1) are treated as 0, then，，，…，That is, the capacitance Cn of the nth capacitor is a times of the capacitance Cn-1 of the nth-1 capacitor, and the resistance R of the metal wire between the nth-1 capacitor and the nth-1 MOS tube_netn-1Greater than or equal to the resistance R of the metal wire between the nth capacitor and the nth MOS tube_netnA times higher, the monotonicity of the total capacitance adjustment of the capacitive array circuit C can be improved. Wherein N = [2, N =]。

In one embodiment, the resistance of a metal wire between each capacitor in the N capacitors and the corresponding MOS tube and the on-resistance of each MOS tube in the N MOS tubes are simultaneously considered to the total capacitance of the capacitor array circuit CInfluence of (A) R_net1、R_net2、R_net3、...、R_netn-1、R_netnAnd R_on1、R_on2、R_on3、...、R_onn-1、R_onnAre not all equal to 0 and,，，

，…，that is, the capacitance Cn of the nth capacitor is a times of the capacitance Cn-1 of the nth-1 capacitor, and the resistance R of the metal wire between the capacitor of the nth-1 capacitor branch and the MOS tube_netn-1And the on-resistance R of the MOS tube_onn-1The sum of the resistance values is larger than or equal to the resistance R of the metal wire between the capacitor of the nth capacitor branch and the MOS tube_netnAnd the on-resistance R of the MOS tube_onnThe sum is a times, so that the total capacitance adjustment of the capacitance array circuit C can be monotonously changed. Wherein N = [2, N =]。

The on-resistance of the MOS tube is inversely proportional to the ratio of the width to the length of the MOS tube, for example, if the ratio of the width to the length of the MOS tube is doubled, the on-resistance of the MOS tube is reduced by half. The ratio of the width to the length of the 1 st MOS tube is M1, the ratio of the width to the length of the 2 nd MOS tube is M2, the ratio of the width to the length of the 3 rd MOS tube is M3. The ratio of the width to the length of the MOS tube is the ratio of the width of a conductive channel of the MOS tube to the length of the conductive channel.

When M1: m2: m3: ...: mn-1: mn = b⁰：b¹：b²：...：b^n-2：b^n-1That is, M2= bM1, M3= bM2, M4= bM3, …, Mn-1= bMn-2, Mn = bMn-1, R is a linear average of the values of M, M_on1：R_on2：R_on3：...：R_onn-1：R_onn=b^n-1：b^n-2：...：b²：b¹：b⁰That is, when the ratio Mn of the width to the length of the nth MOS tube is b times of the ratio Mn-1 of the width to the length of the (n-1) th MOS tube, the on-resistance R of the nth MOS tube_onnIs the on-resistance R of the (n-1) th MOS transistor_onn-11/b times of the total weight of the product.

Further, when b = a, is selected from，，，…，Obtaining:

，

，

，...，i.e. by

That is, the resistance R of the metal line between the (n-1) th capacitor and the (n-1) th MOS transistor_netn-1Greater than or equal to the resistance R of the metal wire between the nth capacitor and the nth MOS tube_netnA times of.

The ratio of the capacitance value of the 1 st capacitor to the capacitance value of the nth capacitor in the N capacitors and the width and length of the 1 st MOS tube in the N MOS tubesThe ratio from the ratio of (n) th MOS tube to the ratio of the width to the length of the nth MOS tube is the same, and the resistance R of the metal wire between the (n-1) th capacitor and the (n-1) th MOS tube_netn-1Greater than or equal to the resistance R of the metal wire between the nth capacitor and the nth MOS tube_netnThe total capacitance adjustment of the capacitor array circuit C can be made monotonous.

The control unit 50 is provided with binary signals trim <1>, trim <2>, trim <3>, …, trim < N-1> and trim < N > corresponding to the N MOS transistors, when the values corresponding to trim <1>, trim <2>, trim <3>, …, trim < N-1> and trim < N > are monotonously changed, the total capacitance output by the capacitor array circuit C is monotonous, and the frequency of the clock signal output by the RC oscillation circuit is monotonously changed. For example, when the value corresponding to trim <1>, trim <2>, trim <3>, …, trim < n-1> and trim < n > is increased, the total capacitance output by the capacitor array circuit C is increased, and the frequency of the clock signal output by the RC oscillation circuit is decreased. The control unit 50 also converts the binary signals trim <1>, trim <2>, trim <3>, …, trim < n-1>, trim < n > into pulse signals respectively, and transmits the pulse signals to a corresponding one of the MOS transistors, and the MOS transistors are turned on or off under the action of the pulse signals.

When a = b =2, C2=2C1, C3=2C2, …, Cn-1=2Cn-2, Cn =2Cn-1, i.e., C1: c2: c3: c4: …: cn-1: cn =2⁰：2¹：2²：2³：2⁴：…：2^n-2：2^n-1，，

，，…，，

Then, then

，，，，

That is, the resistance R of the metal line between the capacitor of the (n-1) th capacitor branch and the MOS transistor_netn-1And the on-resistance R of the MOS tube_onn-1The sum of the resistance values is larger than or equal to the resistance R of the metal wire between the capacitor of the nth capacitor branch and the MOS tube_netnAnd the on-resistance R of the MOS tube_onn2 times the sum.

M1：M2：M3：...：Mn-1：Mn=2⁰：2¹：2²：...：2^n-2：2^n-1，R_on1：R_on2：R_on3：...：R_onn-1：R_onn=2^{n -1}：2^n-2：...：2²：2¹：2⁰That is, when the ratio Mn of the width to the length of the nth MOS transistor is 2 times of the ratio Mn-1 of the width to the length of the (n-1) th MOS transistor, the on-resistance R of the nth MOS transistor_onnIs the on-resistance R of the (n-1) th MOS transistor_onn-11/2 times of, then:

，，，...，i.e. byThat is, the resistance R of the metal line between the (n-1) th capacitor and the (n-1) th MOS transistor_netn-1Greater than or equal to the resistance R of the metal wire between the nth capacitor and the nth MOS tube_netn2 times of the total weight of the powder.

When the binary control signals trim <1>, trim <2>, trim <3>, …, trim < N-1> of the 1 st to nth MOS transistors in the N MOS transistors set by the control unit 50 are monotonously changed, the frequency of the clock signal output by the RC oscillation circuit is monotonously changed, and the steps of the frequency change of the clock signal output by the RC oscillation circuit are equal.

When a = b =2, the step of the total capacitance adjustment of the capacitive array circuit C may be an integer multiple of C1, and the minimum step of the total capacitance adjustment of the capacitive array circuit C is C1.

In one embodiment, the number of metal lines between the 1 st capacitor and the 1 st MOS transistor is 1, the number of metal lines between the 2 nd capacitor and the 2 nd MOS transistor is a, and the number of metal lines between the 3 rd capacitor and the 3 rd MOS transistor is a²A, a metal wire between the n-1 th capacitor and the n-1 th MOS tube is a^n-2The metal wire between the nth capacitor and the nth MOS tube is a^{n -1}And each capacitor is connected with the metal wire between the corresponding MOS tube in parallel. Wherein a is an integer greater than 1.

Referring to fig. 5, when a =2, the number of metal lines between the 1 st capacitor and the 1 st MOS transistor is 1, the number of metal lines between the 2 nd capacitor and the 2 nd MOS transistor is 2, the number of metal lines between the 3 rd capacitor and the 3 rd MOS transistor is 4, and the number of metal lines between the n-1 st capacitor and the n-1 st MOS transistor is 2^n-2The metal wire between the nth capacitor and the nth MOS tube is 2^{n -1}And (3) strips.

By arranging a between the nth capacitor and the nth MOS tube^n-1The metal wires are connected in parallel and have the same resistance value, so that the monotonicity of the adjustment of the total capacitance of the capacitor array circuit C can be realized without arranging extra resistors, and the cost is low.

In one embodiment, the number of metal lines between the 1 st capacitor and the 1 st MOS transistor is 1 and the resistance of the metal line is R_net1The number of the metal lines between the 2 nd capacitor and the 2 nd MOS transistor is 1 and the resistance of the metal line is R_net2The number of the metal lines between the 3 rd capacitor and the 3 rd MOS transistor is 1 and the resistance of the metal line is R_net3,., the number of metal lines between the n-1 th capacitor and the n-1 th MOS transistor is 1 and the resistance of the metal line is R_netn-1The number of metal wires between the nth capacitor and the nth MOS transistor is 1, and the resistance of the metal wire is R_netn，R_net1：R_net2：R_net3：...：R_netn-2：R_netn-1：R_netn=a^n-1：a^n-2：a^n-3：...：a²：a¹：a⁰. When a =2, R_net1：R_net2：R_net3：...：R_netn-2：R_netn-1：R_netn=2^n-1：2^n-2：2^n-3：...：2²：2¹：2⁰。

In the embodiment, only one metal wire is arranged between the capacitor and one corresponding MOS tube, so that the occupied area of the metal wire is further reduced, and the wiring operation is simpler.

In integrated circuit fabrication, the resistance of a metal line is generally defined by R = pl/W, where p is the resistance per square resistor, L is the length of the metal line, W is the width of the metal line, and L/W is the number of square resistors.

Please refer to fig. 6, when

If the capacitor is connected with a corresponding MOS tube by a metal wire with the same resistance value of each square of resistorThe square resistance of the metal line between the 1 st capacitor and the 1 st MOS transistor is a^n-1The number of the square resistances of the metal wire between the 2 nd capacitor and the 2 nd MOS transistor is a^n-2The number of the square resistances of the metal wire between the 3 rd capacitor and the 3 rd MOS transistor is a^n-3,., the square resistance number of the metal wire between the n-1 th capacitor and the n-1 th MOS tube is a, and the square resistance number of the metal wire between the n-1 th capacitor and the n-1 th MOS tube is 1.

Preferably, the 1 st capacitor is connected with the 1 st MOS tube in series a^n-1A metal wire of^n-1Each square resistor of the metal wire has the same resistance value, and the 2 nd capacitor is connected with the 2 nd MOS tube in series^n-2A metal wire of^n-2Each square resistor of the metal wire has the same resistance value, and the 3 rd capacitor is connected with the 3 rd MOS tube in series^n-3A metal wire of^n-3The resistance values of all square resistors of metal wires are the same, wherein a metal wires are connected in series between an n-1 th capacitor and an n-1 th MOS tube, the resistance values of all square resistors of the a metal wires are the same, 1 metal wire is connected in series between the nth capacitor and the nth MOS tube, and the resistance value of each square resistor of the metal wire of each capacitor branch circuit is equal to that of the metal wire of other capacitor branch circuits. The series connected metal lines of each capacitive branch may be arranged at the same layer of the circuit board. Wherein a is an integer greater than 1.

Referring to fig. 7, when a =2, the 1 st capacitor is connected in series with the 1 st MOS transistor by 2^n-1A metal wire 2^n-1Each square resistor of the metal wire has the same resistance value, and the 2 nd capacitor is connected with the 2 nd MOS tube in series by 2^n-2A metal wire 2^n-2Each square resistor of the metal wire has the same resistance value, and the 3 rd capacitor is connected with the 3 rd MOS tube in series by 2^n-3A metal wire 2^n-3The resistance values of each square of the metal wires are the same, 2 metal wires are connected in series between the n-1 th capacitor and the n-1 th MOS tube, the resistance values of each square of the 2 metal wires are the same, 1 metal wire is connected in series between the nth capacitor and the nth MOS tube, and the resistance value of each square of the metal wire of each capacitor branch circuit is equal to that of the metal wire of other capacitor branch circuits. Each capacitorThe series connected metal lines of the branches may be arranged at the same layer of the circuit board.

Preferably, the number of the metal wires between the 1 st capacitor and the 1 st MOS transistor is 1, a metal wires are connected in parallel between the 2 nd capacitor and the 2 nd MOS transistor, the resistance values of each square resistor of the a metal wires are the same, and a is connected in parallel between the 3 rd capacitor and the 3 rd MOS transistor²A metal wire of²The resistance values of each square of resistors of the metal wire are the same, and an n-1 capacitor and an n-1 MOS tube are connected in parallel^n-2A metal wire of^n-2The resistance values of each square of resistors of the metal wire are the same, and the n capacitor and the n MOS tube are connected in parallel by a^n-1A metal wire of^n-1The resistance values of each square of the resistors of the metal wires of the strip metal wires are the same, and the resistance value of each square of the resistors of the metal wires of each capacitor branch circuit is equal to the resistance value of each square of the resistors of the metal wires of other capacitor branch circuits. The parallel metal lines of each capacitive branch may be arranged on different layers of the circuit board. Wherein a is an integer greater than 1.

Referring to fig. 8, when a =2, the number of metal lines between the 1 st capacitor and the 1 st MOS transistor is 1, 2 metal lines are connected in parallel between the 2 nd capacitor and the 2 nd MOS transistor, and the resistance of each block of the 2 metal lines is the same, 4 metal lines are connected in parallel between the 3 rd capacitor and the 3 rd MOS transistor, and the resistance of each block of the 4 metal lines is the same, as that of the n-1 th capacitor and the n-1 th MOS transistor are connected in parallel by 2^n-2A metal wire 2^n-2Each square resistor of the metal wire has the same resistance value, and the nth capacitor and the nth MOS tube are connected in parallel 2^n-1A metal wire 2^n-1The resistance values of each square of the resistors of the metal wires of the strip metal wires are the same, and the resistance value of each square of the resistors of the metal wires of each capacitor branch circuit is equal to the resistance value of each square of the resistors of the metal wires of other capacitor branch circuits. The parallel metal lines of each capacitive branch may be arranged on different layers of the circuit board.

One or more layers of metal wires connected in parallel or in series can be arranged between the capacitor of each capacitor branch and the MOS tube, so that the monotonicity change of the resistance of the metal wires between the capacitors of the plurality of capacitor branches of the capacitor array circuit and the MOS tubes is realized.

Referring to fig. 3 again, a first terminal of the first electronic switch Q1 is connected to the power source V, a second terminal of the first electronic switch Q1 is connected to a first terminal of the second electronic switch Q2 and the output terminal of the capacitor through a resistor R, a second terminal of the second electronic switch Q2 is grounded, a control terminal of the first electronic switch Q1 and a control terminal of the second electronic switch Q2 are respectively configured to receive a clock signal, and the first electronic switch Q1 and the second electronic switch Q2 are turned on and off based on the clock signal. The output terminal of the logic unit 40 is connected to the control terminal of the first electronic switch Q1 and the control terminal of the second electronic switch Q2, respectively. In the figure, the control terminal of the first electronic switch Q1, the control terminal of the second electronic switch Q2, and the output terminal of the logic unit 40 are respectively connected to the VIN terminal, and the VOUT terminal is the output terminal of the capacitor.

The capacitor array circuit C outputs a monotonically changing total capacitance, so that the charging and discharging frequency of the capacitor charging and discharging circuit 20 can be monotonically changed.

In one embodiment, the first electronic switch Q1 is a PMOS transistor, and the first terminal, the second terminal and the third terminal of the first electronic switch Q1 correspond to the drain, the source and the gate of the PMOS transistor, respectively. The second electronic switch Q2 is an NMOS transistor, and the first terminal, the second terminal and the third terminal of the second electronic switch Q2 correspond to the drain, the source and the gate of the NMOS transistor, respectively.

The control unit 50 is respectively connected with the gate of each MOS transistor. The control unit 50 is used for controlling the on and off of each MOS transistor through a control signal to adjust the total capacitance of the capacitor array circuit C.

The control unit 50 is used for controlling the conduction and the cut-off of the MOS transistor through the control signal so as to adjust the total capacitance of the capacitor array circuit C. The control signal is a pulse signal. Specifically, the control unit 50 sets binary signals of the 1 st to nth MOS transistors to be trim <1>, trim <2>, trim <3>, …, trim < n-1>, trim < n >, and transmits a pulse signal corresponding to each binary signal to the MOS transistors, and when values corresponding to the binary signals trim <1>, trim <2>, trim <3>, …, trim < n-1>, and trim < n > are monotonously changed, the charging and discharging frequency of the charging and discharging circuit 20 is monotonously changed, so that the frequency of the clock signal output by the RC oscillation circuit is monotonously changed, thereby improving the accuracy of the output frequency of the RC oscillator.

The total capacitance of the capacitor array circuit C is adjusted to be monotonously changed by the control unit 50, so that the charging and discharging frequency of the capacitor charging and discharging circuit 20 is monotonously changed, the frequency of the clock signal output by the RC oscillation circuit is monotonously changed, and the accuracy of the output frequency of the RC oscillator is improved.

The logic unit 40 may include an RS flip-flop. The metal wire can be a copper wire, and the copper wire has better conductivity and low cost.

The operation principle of the RC oscillation circuit according to the embodiment of the present application will be described below by taking the circuit diagram shown in fig. 9 as an example.

The first charging and discharging circuit 21 includes a capacitor array circuit C1, a power source V1, a first electronic switch M1, a first resistor R1 and a second electronic switch M2, and the second charging and discharging circuit 22 includes a capacitor array circuit C2, a power source V1, a first electronic switch M3, a first resistor R2 and a second electronic switch M4. The first electronic switch is a PMOS tube, and the second electronic switch is an NMOS tube. The first input terminal and the second input terminal of the first comparator I1 correspond to the non-inverting input terminal and the inverting input terminal of the first comparator, respectively. The first input terminal and the second input terminal of the second comparator I2 correspond to the non-inverting input terminal and the inverting input terminal of the second comparator, respectively. The logic unit is an RS flip-flop I3, and the RS flip-flop I3 includes an input terminal S, an input terminal R, an output terminal Q, and an output terminal Qn. The output terminal Q and the output terminal Qn of the RS flip-flop I3 output clock signals CLK and CLKn, respectively.

In the first clock half cycle of the RC oscillation circuit, the last states of Q and Qn are high level and low level respectively, the first electronic switch M1 is turned on, the second electronic switch M2 is turned off, the first charging and discharging circuit 21 charges, and the first comparator I1 outputs high level to the input terminal R of the RS flip-flop I3; meanwhile, the first electronic switch M3 is turned off, the second electronic switch M4 is turned on, the second charging and discharging circuit 22 discharges, the second comparator I2 outputs a low level to the input terminal S of the RS flip-flop I3, the output terminal Q of the RS flip-flop I3 becomes a low level, the output terminal Qn becomes a high level, and the RC oscillating circuit enters a second clock half period. In the second clock half cycle, the last states of Q and Qn are low level and high level respectively, the first electronic switch M1 is turned off, the second electronic switch M2 is turned on, the first charging and discharging circuit 21 discharges, and the first comparator I1 outputs low level to the input terminal R of the RS flip-flop I3; meanwhile, the first electronic switch M3 is turned on, the second electronic switch M4 is turned off, the second charging and discharging circuit 22 charges, the second comparator I2 outputs a high level to the input terminal S of the RS flip-flop I3, the output terminal Q of the RS flip-flop I3 becomes a high level, and the output terminal Qn becomes a low level. Thus, the RC oscillating circuit completes charging and discharging for one whole clock period.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.