阅读说明：本技术 非易失性存储器装置、存储装置和存储器控制器操作方法 (Nonvolatile memory device, and memory controller operating method ) 是由 郑凤吉 于 2019-12-27 设计创作，主要内容包括：提供了非易失性存储器装置、存储装置和存储器控制器操作方法。所述非易失性存储器装置包括：接收并且解码第一命令和第二命令的命令解码器；在解码第一命令的命令解码器的控制下生成第一控制信息的第一控制电路；在解码第二命令的命令解码器的控制下生成第二控制信息的第二控制电路；包括基于第一控制信息操作的第一存储器单元的第一存储体；以及包括基于第二控制信息操作的第二存储器单元的第二存储体。响应于第一命令从第一存储体输出数据的第一时间不同于响应于第二命令从第二存储体输出数据的第二时间。(A non-volatile memory device, a storage device, and a memory controller operating method are provided. The non-volatile memory device includes: a command decoder that receives and decodes the first command and the second command; a first control circuit that generates first control information under control of a command decoder that decodes the first command; a second control circuit that generates second control information under control of a command decoder that decodes the second command; a first bank including a first memory cell operating based on first control information; and a second bank including a second memory cell operating based on the second control information. A first time to output data from the first bank in response to the first command is different from a second time to output data from the second bank in response to the second command.)

1. A non-volatile memory device, comprising:

a command decoder configured to receive and decode the first command and the second command;

a first control circuit configured to generate first control information under control of a command decoder that decodes a first command;

a second control circuit configured to generate second control information under control of a command decoder that decodes the second command;

a first bank including first memory cells operating based on first control information; and

a second memory bank including a second memory cell operating based on second control information, wherein

A first time required to output data from the first bank in response to the first command is different from a second time required to output data from the second bank in response to the second command.

2. The non-volatile memory device of claim 1, further comprising:

a first read circuit configured to generate a first read signal for a first memory cell, wherein the first read signal has a first amplitude determined according to first control information; and

a second read circuit configured to generate a second read signal for a second memory cell, wherein the second read signal has a second amplitude determined from second control information, the second amplitude being different from the first amplitude.

3. The non-volatile memory device of claim 1, further comprising:

a first read circuit configured to generate a first read signal for a first memory cell, wherein the first read signal has a first pulse period determined according to first control information; and

a second read circuit configured to generate a second read signal for the second memory cell, wherein the second read signal has a second pulse period determined according to the second control information, the second pulse period being different from the first pulse period.

4. The non-volatile memory device of claim 3, wherein the first control circuit is configured to load the value for the first pulse period from at least one third memory cell included in the first bank.

5. The non-volatile memory device of claim 1, wherein:

the command decoder is configured to receive an update request for the first bank from the host;

the first control circuit is configured to store the second control information instead of the first control information under control of a command decoder that receives the update request; and is

The first memory unit of the first bank is configured to operate based on the second control information instead of the first control information in response to the command decoder receiving a third command from the host for the first memory unit of the first bank.

6. The non-volatile memory device of claim 1, further comprising:

a first column decoder configured to operate in response to the first control information, wherein the first column decoder is configured to:

in a standby state, a bit line connected to the first memory cell is discharged, and

precharging a bit line connected to a first memory cell after receiving a read request from a host; and

a second column decoder configured to precharge a bit line connected to the second memory cell not in the standby state in response to second control information.

7. The non-volatile memory device of claim 1, wherein the second memory cells of the second bank operate based on the second control information while the first memory cells of the first bank operate based on the first control information.

8. The non-volatile memory device of claim 1, wherein the first memory cell and the second memory cell are phase change random access memory cells.

9. A method of operation of a memory controller connected with a memory device, the method comprising:

dividing a plurality of banks of a memory device into a bank operating in a first mode and a bank operating in a second mode different from the first mode;

receiving a first request corresponding to the first mode from the host, and transmitting a first bank address corresponding to a first bank among the banks operating in the first mode to the memory device in response to the first request; and is

A second request corresponding to the second mode is also received from the host, and a second bank address corresponding to a second bank of the banks operating in the second mode is sent to the memory device in response to the second request.

10. The method of claim 9, further comprising:

receiving a third request from the host; and is

The plurality of memory banks are divided into a memory bank operating in a first mode, a memory bank operating in a second mode, and a memory bank operating in a third mode.

11. The method of claim 9, wherein the step of partitioning comprises:

mapping a first bank address corresponding to a first bank to a first pattern;

mapping a second bank address corresponding to a second bank to a second pattern; and is

The mapping result is stored in a buffer memory of the memory controller.

12. The method of claim 11, further comprising:

receiving a reclassification request from a host; and is

In response to the reclassification request, a first bank address corresponding to the first bank is mapped to the second pattern.

13. The method of claim 9, wherein:

the step of receiving the first request from the host includes determining whether the first request corresponds to the first mode or the second mode, and

the step of receiving the second request from the host includes determining whether the second request corresponds to the first mode or the second mode.

14. The method of claim 9, further comprising:

after selecting the first bank in response to the first request, sending a third request to the memory device for reading the first bank, wherein,

the second request is sent to the memory device between the first request and the third request.

15. A memory device, comprising:

a non-volatile memory device including a first bank, a second bank, a first control circuit configured to control the first bank in response to first control information, and a second control circuit configured to control the second bank in response to second control information; and

a memory controller configured to:

in response to a first request by a host to read a first bank, a first read command is sent to a non-volatile memory device, and

sending a second read command to the non-volatile memory device in response to a second request by the host to read a second bank, wherein

A first time delay from a time when the memory controller transmits the first read command to a time when the memory controller receives data of the first bank corresponding to the first read command is different from a second time delay from a time when the memory controller transmits the second read command to a time when the memory controller receives data of the second bank corresponding to the second read command.

16. The memory device according to claim 15, wherein the first control circuit determines a signal to be applied to the first bank through the first control information so that the first bank outputs data of the first bank with a first delay, and

the second control circuit determines a signal to be applied to the second memory bank through the second control information so that the second memory bank outputs data of the second memory bank with a second time delay.

17. The storage device of claim 16, wherein the memory controller is configured to:

prior to sending the first read command to the non-volatile memory device, also sending a first select command to the non-volatile memory device for selecting the first bank; and is

Sending a second select command to the non-volatile memory device for selecting a second bank prior to sending a second read command to the non-volatile memory device, wherein

The time interval between the first select command and the first read command is different from the time interval between the second select command and the second read command.

18. The storage device of claim 17, wherein the memory controller is configured to:

the first bank and the second bank are selected in parallel based on the memory controller sending a first select command and a second select command to the non-volatile storage.

19. The memory device according to claim 16, wherein based on the memory controller receiving the first request again after receiving the update request for the first bank from the host, the first control circuit determines a signal to be applied to the first bank through the second control information so that the first bank outputs the data of the first bank with the second latency.

20. The storage device of claim 15, wherein a third latency from a time the host receives the first request to a time the data of the first bank is output to the host is different from a fourth latency from a time the host receives the second request to a time the data of the second bank is output to the host.

Technical Field

Embodiments of the inventive concepts described herein relate to a semiconductor memory device, and more particularly, to a nonvolatile memory device including banks operating in different operation modes, an operating method of a memory controller, and a memory device including the nonvolatile memory device and the memory controller.

Background

Requests sent by the host to the memory system are classified based on the operational purpose of the memory system and the characteristics of the data to be read or written. For example, the request of the host may be used to request the memory system to operate at the highest speed, to request the memory system to consume the least power, or to request an operation with high reliability.

To maximize performance, the memory system should perform separate operations based on different requests of the host. For this reason, it is necessary to control the memory devices in the memory system by dividing the memory devices into a plurality of areas and individually controlling the thus divided areas according to different requests of the host.

Disclosure of Invention

Embodiments of the inventive concepts provide a non-volatile memory device, a method of operating a memory controller, and a storage device including a non-volatile memory device and a memory controller.

According to some example embodiments, a non-volatile memory device may include: a command decoder that receives and decodes the first command and the second command; a first control circuit that generates first control information under control of a command decoder that decodes the first command; a second control circuit that generates second control information under control of a command decoder that decodes the second command; a first bank including a first memory cell operating based on first control information; and a second bank including a second memory cell operating based on the second control information. A first time to output data from the first bank in response to the first command may be different from a second time to output data from the second bank in response to the second command.

According to some example embodiments, a method of operating a memory controller connected with a memory device may include: dividing a plurality of banks of a memory device into a bank operating in a first mode and a bank operating in a second mode different from the first mode; receiving a first request corresponding to the first mode from the host, and transmitting a first bank address corresponding to a first bank among the banks operating in the first mode to the memory device in response to the first request; and also receives a second request corresponding to the second mode from the host, and transmits a second bank address corresponding to a second bank among the banks operating in the second mode to the memory device in response to the second request.

According to some example embodiments, a storage device may include: a non-volatile memory device including a first bank, a second bank, a first control circuit configured to control the first bank in response to first control information, and a second control circuit configured to control the second bank in response to second control information; and a memory controller configured to send a first read command to the non-volatile memory device in response to a first request by the host to read the first bank, and configured to send a second read command to the non-volatile memory device in response to a second request by the host to read the second bank. A first time delay from a time when the memory controller transmits the first read command to a time when the memory controller receives data of the first bank corresponding to the first read command may be different from a second time delay from a time when the memory controller transmits the second read command to a time when the memory controller receives data of the second bank corresponding to the second read command.

Drawings

The above objects and features and other objects and features of the inventive concept will become apparent from the detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings.

Fig. 1 is a block diagram illustrating a non-volatile memory device according to some example embodiments of the inventive concepts.

Fig. 2 is an architecture of a non-volatile memory device according to some example embodiments of the inventive concepts.

Fig. 3 is a block diagram illustrating an example of a memory cell array included in the nonvolatile memory device of fig. 1.

Fig. 4 is a graph showing the supply of write voltages to the first bank and the second bank of fig. 1 over time.

Fig. 5 is a graph illustrating the supply of bit line voltages to the first and second banks of fig. 1 over time.

Fig. 6 is a block diagram illustrating a storage device including the nonvolatile memory device of fig. 1 according to some example embodiments of the inventive concepts.

Fig. 7 is a timing diagram of signals provided to the non-volatile memory device of fig. 6.

Fig. 8 is a block diagram illustrating a storage device including the nonvolatile memory device of fig. 2 according to some example embodiments of the inventive concepts.

Fig. 9 is a block diagram illustrating the memory controller of fig. 6.

Fig. 10 is a flowchart illustrating an operation method of a memory controller according to some example embodiments of the inventive concepts.

Fig. 11 is a flowchart illustrating a method for changing a category of a bank included in a nonvolatile memory device according to some example embodiments of the inventive concepts.

Detailed Description

Hereinafter, embodiments of the inventive concept will be described in detail and clearly to the extent that the inventive concept is easily implemented by those skilled in the art.

Fig. 1 is a block diagram illustrating a non-volatile memory device according to some example embodiments of the inventive concepts. The non-volatile memory device 100 may include: command decoder 110, address buffer 120, first control circuit 130, second control circuit 140, first memory bank 150, second memory bank 160, and/or input/output circuit 170.

The nonvolatile memory device 100 may receive a command CMD and an address ADDR from an external device (e.g., a memory controller). The nonvolatile memory device 100 may write data DQ to one of the first bank 150 and the second bank 160 based on the command CMD and the address ADDR. The nonvolatile memory device 100 may read data stored in one of the first and second memory banks 150 and 160 based on the command CMD and the address ADDR, and may output the read data as data DQ.

In some example embodiments, one or more or all of the command decoder 110, the first control circuitry 130, the second control circuitry 140, the memory controller, and/or any portion thereof may be included in, may include, and/or may be implemented as one or more instances of processing circuitry (such as hardware including logic circuitry), a hardware/software combination (such as a processor executing software), and combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to: a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SOC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), etc. In some example embodiments, the processing circuit may include a non-transitory computer readable storage device (e.g., a memory device) such as a Solid State Drive (SSD) and storing a program of instructions, and a processor configured to execute the program of instructions to implement the functionality of one or more or all of the command decoder 110, the first control circuit 130, the second control circuit 140, and the memory controller.

The command decoder 110 may decode a command CMD received from an external device (e.g., a memory controller). The command decoder 110 may receive the address ADDR. The command decoder 110 may determine whether the received command CMD is associated with the first memory bank 150 or the second memory bank 160 with reference to the bank address BA included in the address ADDR. The command decoder 110 may select and/or activate one of the first control circuit 130 and the second control circuit 140 based on the command CMD and the address ADDR. For example, the commands CMD may include a read command, a write command, an activate command, an update command for the first bank 150 or the second bank 160, and/or a reclassification command for the first bank 150 or the second bank 160.

The address buffer 120 may receive an address ADDR from an external device (e.g., a memory controller). The address buffer 120 may provide the address ADDR to the command decoder 110. The address buffer 120 may provide an address ADDR to one of the first control circuit 130 and the second control circuit 140 under the control of the command decoder 110.

Under the control of the command decoder 110, the address buffer 120 may provide the row decoder 152 and the row decoder 162 with the received address ADDR as a row address RA and/or may provide the column decoder 153 and the column decoder 164 with the received address ADDR as a column address CA.

The first control circuit 130 may generate first control information under the control of the command decoder 110 and may provide a first control signal CTRL1 based on the first control information to the first memory bank 150. The second control circuit 140 may generate second control information under the control of the command decoder 110 and may provide a second control signal CTRL2 based on the second control information to the second memory bank 160. The first and second control circuits 130 and 140 may control the operations of the first and second memory banks 150 and 160 by using first and second control signals CTRL1 and CTRL2, respectively.

The first control signal CTRL1 may include a first row control signal CTRL1_ RA for controlling the row decoder 152, a first column control signal CTRL1_ CA for controlling the column decoder 153, and a first read/write control signal CTRL1_ RW for controlling the write driver 154 and the sense amplifier 155. The second control signal CTRL2 may include a second row control signal CTRL2_ RA for controlling the row decoder 162, a second column control signal CTRL2_ CA for controlling the column decoder 163, and a second read/write control signal CTRL2_ RW for controlling the write driver 164 and the sense amplifier 165. The first row control signal CTRL1_ RA, the second row control signal CTRL2_ RA, the first column control signal CTRL1_ CA, the second column control signal CTRL2_ CA, the first read/write control signal CTRL1_ RW, and the second read/write control signal CTRL2_ RW will be more fully described with reference to fig. 4 and 5.

The first control circuit 130 may include a register R1. The second control circuit 140 may include a register R2. The registers R1 and R2 may include first and second control information associated with a mode of operation, operating characteristics, and operating settings of the first and second memory banks 150 and 160, respectively. Here, the mode of operation, the operation characteristics, and the operation settings of the first bank 150 may include at least one of a speed at which the first bank 150 operates, power consumption of the first bank 150, and information on reliability of the first bank 150 operation. The first control circuit 130 may generate the first control signal CTRL1 with reference to the register R1. The second control circuit 140 may generate the second control signal CTRL2 with reference to the register R2.

In some exemplary embodiments, the command decoder 110 may receive an update request for the first bank 150 from an external device (e.g., a host). The first control circuit 130 may store not the first control information but the second control information under the control of the command decoder 110 receiving the update request. When the command decoder 110 receives a command for the memory cells of the first bank 150 from an external device, the memory cells of the first bank 150 may operate based on the second control information instead of the first control information.

The first bank 150 may include memory cells MC that operate based on the first control information. The second bank 160 may include memory cells MC that operate based on the second control information. The first bank 150 and the second bank 160 may perform a write operation and a read operation independently or simultaneously. The write operation may include a set operation to change the logic value of the memory cell MC from the first logic value "0" to the second logic value "1", and a reset operation to change the logic value of the memory cell MC from the second logic value "1" to the first logic value "0". Here, the logical values stored in the memory cells MC by the set operation and the reset operation are merely examples.

The first and second banks 150 and 160 may perform a write operation or a read operation based on information of the operation setting. Here, the information of the operation setting may include information on one or more signals for performing a write operation or a read operation on the first and second banks 150 and 160. In some example embodiments, the information of the operation setting may include information on a bit line signal, a word line signal, a set signal, and a reset signal. The information about the bit line signal, the word line signal, the set signal, and the reset signal may include, but is not limited to, information about the amplitude, pulse duration (or pulse period), and timing of each signal.

The first bank 150 and the second bank 160 may operate in different modes. For example, the first bank 150 may operate in a low reliability, high power consumption, or fast mode; the second bank 160 may operate in another mode of high reliability, low power consumption, or slow speed.

One example is shown in fig. 1 as: the number of banks included in the nonvolatile memory device 100 is "2", but the inventive concept is not limited thereto. The number of banks included in the nonvolatile memory device 100 is not limited to any number.

The first bank 150 may include a memory cell array 151, a row decoder 152, a column decoder 153, a write driver 154, and a sense amplifier 155. The second bank 160 may include a memory cell array 161, a row decoder 162, a column decoder 163, a write driver 164, and a sense amplifier 165. The second bank 160 may be implemented substantially the same as the first bank 150. Accordingly, the components of the first bank 150 and the first bank 150 will be described below, and descriptions associated with the components of the second bank 160 and the second bank 160 will be omitted to avoid redundancy.

In fig. 1, a description will be given in the case where the first bank 150 includes a memory cell array 151, a row decoder 152, a column decoder 153, a write driver 154, and a sense amplifier 155. However, unlike fig. 1, the first bank 150 may be referred to only as a memory cell array 151, and the row decoder 152, the column decoder 153, the write driver 154, and the sense amplifier 155 may be included in any other components.

The memory cell array 151 may include a plurality of memory cells MC connected to a plurality of word lines WL and a plurality of bit lines BL. Each of the plurality of memory cells MC may be connected between one of the plurality of word lines WL and one of the plurality of bit lines BL. For example, the memory cell array 151 may be a cross-point memory cell array. The memory cell array 151 may be controlled in units of a plurality of blocks (tiles) (not shown). The memory cell array 151 may include a DRAM (dynamic random access memory) cell, an SRAM (static random access memory) cell, a PRAM (phase change random access memory) cell, a ReRAM (resistive random access memory) cell, a FeRAM (ferroelectric random access memory) cell, a TRAM (thyristor random access memory) cell, an MRAM (magnetic random access memory) cell, etc., but the inventive concept is not limited thereto. The memory cell array 151 will be described more fully with reference to fig. 3.

The row decoder 152 may be connected to the memory cell array 151 through a plurality of word lines WL. The row decoder 152 may receive a row address RA from the address buffer 120. The row decoder 152 may select at least one of the plurality of word lines WL based on the row address RA. The row decoder 152 may apply a selection voltage and/or a selection current to a selected word line, and may apply a non-selection voltage and/or a non-selection current to unselected word lines.

The column decoder 153 may be connected to the data lines DL. The column decoder 153 may be connected to the memory cell array 151 through a plurality of bit lines BL. The column decoder 153 may receive a column address CA from the address buffer 120. The column decoder 153 may select at least one of the plurality of bit lines BL based on a column address CA.

In a write operation, the write driver 154 may write data into the memory cell MC. In this case, the write driver 154 may write data by performing a set operation or a reset operation such that the resistance value of the memory cell MC is changed. In the set operation or the reset operation, the write driver 154 may apply a write pulse to the memory cell MC. The write driver 154 may be connected to a plurality of data lines DL.

The sense amplifier 155 may generate a first read signal having an amplitude or a pulse period determined according to the first control information with respect to the memory cells in the first bank 150. The first control circuit 130 may load a value of an amplitude or a pulse period of the first read signal from at least one memory cell included in the first bank 150.

In a read operation, the sense amplifier 155 may read data from the memory cell MC. In this case, the sense amplifier 155 may read data by determining a range of resistance values of the memory cell MC. The sense amplifier 155 may be connected to a plurality of data lines DL. The sense amplifier 155 may also be referred to as a "read circuit".

The input/output circuit 170 may exchange data DQ with one of the first and second memory banks 150 and 160. Further, the input/output circuit 170 may exchange data DQ with an external device (e.g., a memory controller).

The input/output circuit 170 may transmit data DQ from one of the first and second memory banks 150 and 160 to an external device, and may transmit data DQ from the external device to one of the first and second memory banks 150 and 160.

Fig. 2 is an architecture of a non-volatile memory device according to some example embodiments of the inventive concepts. Fig. 2 will be described with reference to fig. 1. The nonvolatile memory device 200 may include first through sixteenth banks 211 through 226 and a peripheral circuit PERI. The non-volatile memory device 200 may be a cross-point non-volatile memory device. The first through sixteenth banks 211 through 226 and the peripheral circuit PERI may be formed on a semiconductor substrate. Hereinafter, it is assumed that the first bank 211 is the first bank 150 of fig. 1.

As the first bank 150 of fig. 1, the first bank 211 may include a memory cell array 151, a row decoder 152, a column decoder 153, a write driver 154, and a sense amplifier 155. However, the first bank 211 may further include the first control circuit 130.

The first bank 211 is divided into a first region 230, a second region 240, and a third region 250. The first bank 211 may include the memory cell array 151 in the first to third regions 230 to 250. The memory cell array 151 may be disposed in the first region 230 and the third region 250. A circuit (e.g., the first control circuit 130) for controlling the memory cell array 151 may be disposed in the second region 240.

The first bank 211 may include a row decoder 152, a column decoder 153, a write driver 154, a sense amplifier 155, and a first control circuit 130 in the second region 240.

The second through sixteenth banks 212 through 226 may have the same structure and configuration as the first bank 211. Each of the second through sixteenth memory banks 212 through 226 may include components in the first memory bank 150.

The first through sixteenth banks 211 through 226 may perform a write operation or a read operation independently of each other. For example, the first through sixteenth banks 211 through 226 may perform a write operation or a read operation based on different operation setting information. For another example, each of the first through sixteenth banks 211 through 226 may be classified as a bank performing a write operation or a read operation based on the first operation setting information, or a bank performing a write operation or a read operation based on the second operation setting information. For example, the first bank 211 may perform a write operation or a read operation based on the first operation setting information, and the second to sixteenth banks 212 to 226 may perform a write operation or a read operation based on the second operation setting information.

Referring to fig. 2, the number of banks included in the nonvolatile memory device 200 is "16", but the inventive concept is not limited thereto. That is, the number of banks included in the nonvolatile memory device 200 is not limited to any number.

The peripheral circuit PERI may receive an address ADDR, a command CMD, and a control signal CTRL from an external device (e.g., a memory controller). The peripheral circuit PERI may exchange data DQ with an external device (e.g., a memory controller) in response to a received signal. The peripheral circuit PERI may include a command decoder 260, an address buffer 270, and an input/output circuit 280. The command decoder 260, the address buffer 270, and the input/output circuit 280 may be substantially the same as the command decoder 110, the address buffer 120, and the input/output circuit 170 of fig. 1, respectively. The command decoder 260, the address buffer 270, and the input/output circuit 280 may be connected with components in the second region 240.

Regarding the first to sixteenth banks 211 to 226, the manufacturing process, the electrical signals provided to the first to sixteenth banks 211 to 226, and the degree of degradation according to the use of the first to sixteenth banks 211 to 226 may be different from each other. In this way, a difference between optimized signals (e.g., a read signal and a write signal) for operating the first through sixteenth banks 211 through 226 may be increased. Further, since one bank is selected and operated based on a bank address, a characteristic difference between components in the bank may be smaller than a characteristic difference between components in different banks. The characteristic difference may depend on the holding time, temperature, transmission path of the control signal, or degree of variation of the pulse supplied to the write driver. In the inventive concept, since the first through sixteenth banks 211 through 226 included in the nonvolatile memory device 200 operate according to respective operation settings, the performance of the nonvolatile memory device 200 may be optimized.

Fig. 3 is a block diagram illustrating an example of a memory cell array included in the nonvolatile memory device of fig. 1. One example is shown in fig. 3 as: the memory cell array 151 includes memory cells MC arranged in a two-dimensional structure, but the memory cells MC may be arranged in a three-dimensional structure.

The memory cells MC may be arranged in rows and columns. The memory cells MC in the row may be connected to the first to ith word lines WL1 to WLi. The memory cells MC in the column may be connected to first to jth bit lines BL1 to BLj. Here, the number of word lines "i", the number of bit lines "j", and the number of memory cells may be variously changed according to some example embodiments.

Each of the memory cells MC may be connected to one word line and one bit line. According to some example embodiments, each of the memory cells MC may include a variable resistance element "R" and a selection element "D". Here, the variable resistance element "R" may be referred to as a "variable resistance material", and the selection element "D" may be referred to as a "switching element".

In some example embodiments, the variable resistance element "R" may be connected between one of the first to ith word lines WL1 to WLi and the selection element "D", and the selection element "D" may be connected between the variable resistance element "R" and one of the first to jth bit lines BL1 to BLj. However, the inventive concept is not limited thereto. For example, a selection element "D" may be connected between one of the first to ith word lines WL1 to WLi and the variable resistance element "R", and the variable resistance element "R" may be connected between the selection element "D" and one of the first to jth bit lines BL1 to BLj.

According to some example embodiments, the variable resistance element "R" may have one of a plurality of resistance states by an electrical pulse applied thereto. In some example embodiments, the variable resistance element "R" may include a phase change material, a crystal (or crystalline) state of which is changed according to a magnitude of voltage or a magnitude of current. The phase change material may include various materials, such as GaSb, InSb, InSe, Sb₂Te₃GeTe, GeSbTe (also called GST), GaSetE, InSbTe, SnSb₂Te₄InSbGe, AgInSbTe, (GeSN) SbTe, GeSb (SeTe) and/or Te₈₁Ge₁₅Sb₂S₂。

The phase change material may have an amorphous state with a relatively large resistance and a crystalline state with a relatively small resistance. The phase of the phase change material may be changed by joule heat generated according to the amount of current. Data can be written by using a phase change of a phase change material.

The selection element "D" may be connected between one of the first to ith word lines WL1 to WLi and one of the first to jth bit lines BL1 to BLj, and may control supply of voltage or current to the variable resistance element "R" based on signals (e.g., word line signals and bit line signals) applied to the word line and the bit line connected to the selection element "D". In some example embodiments, the selection element "D" may be a PN junction diode or a PIN junction diode. An anode of the diode may be connected to the variable resistance element "R", and a cathode of the diode may be connected to one of the first word line WL1 through the ith word line WLi. In this case, when a voltage difference between the anode and the cathode of the diode is greater than a threshold voltage of the diode, the diode may be turned on, and thus, a current may be supplied to the variable resistive element "R". One example is shown in fig. 3 as: the selection element "D" is a diode, but the inventive concept is not limited thereto. For example, the selection element "D" may be implemented with a switchable element (e.g., a transistor).

As in some example embodiments of the inventive concepts, the memory cell array 151 may be implemented with a three-dimensional (3D) memory array. The three-dimensional memory array may be monolithically formed with one or more physical layers of a memory cell array having active regions disposed on a silicon substrate and circuitry associated with operation of the memory cells. Circuitry associated with the operation of the memory cell may be located in and/or on the substrate. The term "monolithic" means that each horizontal (level) layer of the array is deposited directly on each bottom level layer of the array. The 3D memory array may be configured such that the switching element including at least one memory cell and the variable resistance element are vertically arranged according to a vertical direction.

Fig. 4 is a graph showing the supply of write voltages to the first bank and the second bank of fig. 1 over time. Fig. 4 will be described with reference to fig. 1. Only the write voltage is shown in fig. 4, but the principle of fig. 4 may be equally applied to the read voltages of the first and second memory banks 150 and 160.

The write voltage of the first bank 150 may be a voltage supplied to the memory cells included in the first bank 150 for a write operation of the first bank 150. The write voltage of the second bank 160 may be a voltage supplied to the memory cells included in the second bank 160 for a write operation of the second bank 160.

In fig. 4, in response to the first control signal CTRL1, the first control circuit 130 may perform a write operation on memory cells included in the first bank 150 based on the write voltage of the first bank 150 having the magnitude of "W1-Vss". In response to the second control signal CTRL2, the second control circuit 140 may perform a write operation on the memory cells included in the second bank 160 based on the write voltage of the second bank 160 having the magnitude "W2-Vss". That is, the first and second memory banks 150 and 160 may operate based on write voltages having different magnitudes. Referring to fig. 4, since the magnitude of the write voltage of the second bank 160 is smaller than that of the first bank 150, the power consumption of the second bank 160 may be smaller than that of the first bank 150. In this way, the nonvolatile memory device 100 can set the banks so that power consumption is different.

Referring to fig. 4, the pulse duration of the write voltage of the first bank 150 may be T1, and the pulse duration of the write voltage of the second bank 160 may be T2. T1 and T2 may be different from each other. Here, T1 and T2 may be different from each other due to differences between activation time, deactivation time, application time, and non-application time of the write voltages of the first bank 150 and the second bank 160.

For example, where T1 and T2 are different from each other, T1 may be greater than T2. The pulse duration of the write voltage of the first bank 150 may be greater than that of the second bank 160, and thus, the first bank 150 may operate with higher reliability than the second bank 160. In contrast, the pulse duration of the write voltage of the second bank 160 may be less than that of the first bank 150, and thus, the second bank 160 may operate faster than the first bank 150.

The second bank 160 may be activated while the write/read operation of the first bank 150 is performed. In some example embodiments, the first write driver 154 of the first bank 150 may provide a write pulse to the memory cells included in the first bank 150 and may provide a voltage across the memory cells of the first bank 150 in response to the first read/write control signal CTRL1_ RW in the first control signal CTRL 1. The first control circuit 130 may perform a read operation on the memory cells of the first bank 150 based on the voltage across the memory cells of the first bank 150. When a read operation is performed on the memory cells of the first bank 150, the second write driver 164 may supply a write pulse to the memory cells included in the second bank 160 in response to the second read/write control signal CTRL2_ RW in the second control signal CTRL2, and may supply a voltage across the memory cells of the second bank 160.

Fig. 5 is a graph illustrating the supply of bit line voltages to the first and second banks of fig. 1 over time. Fig. 5 will be described with reference to fig. 1. Only the bit line voltages of the first and second banks 150 and 160 are shown in fig. 5, but the principle of fig. 5 can be equally applied to the word line voltages of the first and second banks 150 and 160.

The column decoder 153 in the first bank 150 of fig. 1 may discharge bit lines connected to memory cells in the first bank 150 in a standby state in response to a first row control signal CTRL1_ RA among the first control signals CTRL1 output from the first control circuit 130. Here, the discharge of the bit line may mean applying the ground voltage Vss or the discharge voltage to the bit line. The column decoder 153 may precharge the bit lines connected to the memory cells in the first bank 150 at time t10 after receiving a read request from an external device. Here, the precharging of the bit lines may mean applying a voltage greater than "0" (e.g., the precharge voltage Vpre of fig. 5) to the bit lines instead of the ground voltage Vss or the discharge voltage.

At time t11 when the precharge operation is completed, first control circuit 130 may perform a read operation on the memory cells in first bank 150. For example, in a read operation, a read voltage Vread (═ 2Vpre) greater than the precharge voltage Vpre may be applied to bit lines connected to memory cells in the first bank 150.

At time t12 when the read operation is completed, a recovery operation may be performed. That is, the voltage of the bit line connected to the memory cell in the first bank 150 may be restored to the precharge voltage Vpre. However, in other embodiments, the recovery operation may be omitted.

At time t13 when the recovery operation is completed, the ground voltage Vss may be applied to the bit lines connected to the memory cells in the first bank 150. That is, the voltage of the bit line connected to the memory cell in the first bank 150 may be restored to the standby state voltage. As a result, in the standby state, since the bit lines connected to the memory cells in the first bank 150 are maintained at the standby state voltage, potential current leakage may be significantly reduced, and power consumption of the first bank 150 may be reduced.

The row decoder 162 and the column decoder 163 in the second bank 160 of fig. 1 may precharge word lines and bit lines connected to memory cells in the second bank 160 that are not in a standby state, in response to a second row control signal CTRL2_ RA among the second control signals CTRL2 output from the second control circuit 140. That is, the precharge operation may not be performed in the standby state.

At time t14, second control circuit 140 may perform a read operation on memory cells in second bank 160. For example, in a read operation, a read voltage Vread (═ 2Vpre) greater than the precharge voltage Vpre may be applied to bit lines connected to memory cells in the second bank 160.

At time t15 when the read operation is completed, the precharge voltage Vpre may be applied to the bit lines connected to the memory cells in the second bank 160. That is, the memory cells in the second bank 160 may immediately enter the standby state without a separate recovery operation.

In this way, even in the standby state, the bit lines and word lines connected to the memory cells in the second bank 160 can maintain the precharge state by the precharge voltage. That is, a separate precharge operation need not be performed on the second bank 160. After the standby state, it is possible to respond to a request of an external device (e.g., a host) at a high speed with respect to the memory cells in the second bank 160 and perform a write operation at a high speed.

Fig. 6 is a block diagram illustrating a storage device including the nonvolatile memory device of fig. 1 according to some example embodiments of the inventive concepts. The memory device 1000 may also be referred to as a "memory system". The memory device 1000 may include a memory controller 1100 and a non-volatile memory device 1200.

The memory controller 1100 may allow the nonvolatile memory device 1200 to perform a read operation or a write operation. For example, the memory controller 1100 may provide the commands CMD, the addresses ADDR, and the data DQ to the nonvolatile memory device 1200, so that the nonvolatile memory device 1200 performs a write operation.

The memory controller 1100 may provide a physical connection between an external device (e.g., a host) and the non-volatile memory device 1200. The memory controller 1100 may control the nonvolatile memory device 1200 in response to a signal received from an external device. The memory controller 1100 may provide an interface connection with the nonvolatile memory device 1200 according to a bus format of an external device. In particular, the memory controller 1100 may decode a command provided from an external device. The memory controller 1100 may access the nonvolatile memory device 1200 based on the decoded result.

The memory controller 1100 may include a buffer memory 1121. The buffer memory 1121 may store a mapping table in which a first bank address of a bank operating in a first mode is mapped to the first mode, and a second bank address of a bank operating in a second mode is mapped to the second mode.

The non-volatile memory device 1200 may include a first control circuit 1211, a second control circuit 1212, a first bank 1231, and a second bank 1232. The non-volatile memory device 1200 may be substantially the same as the non-volatile memory device 100 of FIG. 1. That is, the first control circuit 1211 and the second control circuit 1212 may be substantially the same as the first control circuit 130 and the second control circuit 140, and the first bank 1231 and the second bank 1232 may be substantially the same as the first bank 150 and the second bank 160.

The nonvolatile memory device 1200 may store data and/or may provide data stored therein to the memory controller 1100 under the control of the memory controller 1100. The nonvolatile memory device 1200 may be provided as a storage medium of the storage device 1000. For example, non-volatile memory device 1200 may be implemented with Phase Change Memory (PCM). The non-volatile memory device 1200 may include a plurality of memory devices. In this case, the memory device may be connected to the memory controller 1100 in units of channels.

The memory controller 1100 may receive a first request corresponding to a first mode from an external device (e.g., a host). The memory controller 1100 may determine whether the first request corresponding to the first pattern is associated with the first bank 1231 based on a mapping table stored in the buffer memory 1121. When a first request corresponding to a first mode is associated with first bank 1231, memory controller 1100 may select first bank 1231.

In some example embodiments, memory controller 1100 may access first bank 1231 based on a first request that includes operating characteristics of first bank 1231 from an external device (e.g., a host). In this case, the memory controller 1100 may determine an address of the first bank 1231 that is a target of the access (e.g., an access target bank address) based on the first request including the operation characteristic of the first bank 1231. In this way, memory controller 1100 may access first bank 1231.

In some example embodiments, the first control circuit 1211 may receive an update request for the first bank 1231 from an external device (e.g., a host) through the memory controller 1100, and then may receive a read request from the external device. Here, the update request may refer to a request for updating the amplitude value, duration value, and timing of the pulse for the operation of the first bank 1231. In the case where a read request is received from an external device through the memory controller 1100 after a refresh request to the first bank 1231 is received from the external device (e.g., a host), the first control circuit 1211 may perform a read operation on the memory cells of the first bank 1231 by using a read/write pulse different from a read/write pulse used before the refresh request is received. The first control circuit 1211 may load an amplitude value and a pulse duration value of a read/write pulse different from a read/write pulse used before the update request is received from at least one memory cell included in the first bank 1231.

In some example embodiments, memory controller 1100 may receive a reclassification request for a bank from an external device (e.g., a host). Here, a reclassification request may refer to a request to change an operating characteristic of a bank (e.g., an amplitude value and a duration value of a read/write pulse). For example, when the first operating characteristic corresponds to the first bank 1231 and the second operating characteristic corresponds to the second bank 1232, in response to a re-classification request from an external device, the memory controller 1100 may update the first bank 1231 so as to be set as the second operating characteristic and may update the second bank 1232 so as to be set as the first operating characteristic. Further, to update the first bank 1231, the memory controller 1100 may refer to a third operating characteristic different from the first and second operating characteristics; in response to a reclassification request from an external device, the memory controller 1100 may update the first bank 1231 to be set as the third operation characteristic. In response to a reclassification request from an external device, the memory controller 1100 may map the bank address of the first bank 1231 to the second pattern in the mapping table in response to the reclassification request.

In some example embodiments, the memory controller 1100 may activate or access the second bank 1232 while performing a read operation or a write operation on the first bank 1231. Memory controller 1100 may access second bank 1232 simultaneously with accessing first bank 1231. When performing a read operation on the first bank 1231, the memory controller 1100 may receive a second request corresponding to a second mode, which is different from the first request corresponding to the first bank 1231, from an external device. The memory controller 1100 may determine whether the second request corresponding to the second mode is associated with the second bank 1232 based on the mapping table stored in the buffer memory. When a second request corresponding to the second mode is associated with the second bank 1232, the memory controller 1100 may access the second bank 1232 while performing a read operation on the first bank 1231.

In some example embodiments, the memory controller 1100 and/or the non-volatile memory device 1200 may be packaged according to any of a variety of different packaging technologies. Examples of such packaging techniques may include the following: package on package (PoP), Ball Grid Array (BGA), Chip Scale Package (CSP), Plastic Leaded Chip Carrier (PLCC), plastic dual in-line package (PDIP), waffle pack die, wafer die, Chip On Board (COB), ceramic dual in-line package (CERDIP), plastic Metric Quad Flat Package (MQFP), Small Outline Integrated Circuit (SOIC), small outline package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flat Package (TQFP), System In Package (SIP), multi-chip package (MCP), wafer level package (WFP), and wafer level process stack package (WSP), among others.

Fig. 7 is a timing diagram of signals provided to the non-volatile memory device of fig. 6. Fig. 7 will be described with reference to fig. 1 and 6. Timing of transmitting and receiving the command CMD and the address ADDR, and timing of outputting and receiving the data DQ are shown in fig. 7.

The commands CMD may include a select command BK1 SEL for the first bank 1231, a select command BK2 SEL for the second bank 1232, a read command BK1 RD for the first bank 1231, and a read command BK2 RD for the second bank 1232. The address ADDR may include a row address BK1 RA of the first bank 1231, a row address BK2 RA of the second bank 1232, a column address BK1 CA of the first bank 1231, and a column address BK2CA of the second bank 1232. The DATA DQ may include read DATA1 of the first memory bank 1231 and read DATA2 of the second memory bank 1232.

At time t20, memory controller 1100 may send a select command BK1 SEL for first bank 1231 and a row address BK1 RA for first bank 1231 to nonvolatile memory device 1200, and nonvolatile memory device 1200 may receive a select command BK1 SEL for first bank 1231 and a row address BK1 RA for first bank 1231. At time t21, memory controller 1100 may send a select command BK2 SEL for second bank 1232 and a row address BK2 RA of second bank 1232 to nonvolatile memory device 1200, and nonvolatile memory device 1200 may receive a select command BK2 SEL for second bank 1232 and a row address BK2 RA of second bank 1232. When the memory controller 1200 sends the selection commands BK1 SEL and BK2 SEL, the first bank 1231 and the second bank 1232 may be selected in parallel. Selecting in parallel refers to selecting independently and is not affected by the other banks selected by the memory controller 1200. For example, a first bank 1231 and a second bank 1232 selected in parallel may be simultaneously selected by the memory controller 1200.

At time t22, memory controller 1100 may send a read command BK1 RD for first bank 1231 and column address BK1 CA for first bank 1231 to non-volatile memory device 1200, and non-volatile memory device 1200 may receive BK1 RD for first bank 1231 and column address BK1 CA for first bank 1231. At time t23, memory controller 1100 may send a read command BK2 RD for second bank 1232 and a column address BK2CA for second bank 1232 to non-volatile memory device 1200, and non-volatile memory device 1200 may receive read command BK2 RD for second bank 1232 and column address BK2CA for second bank 1232.

At time t24, the first bank 1231 may output read DATA1 from at least one memory cell in the first bank 1231, and the memory controller 1100 may receive the read DATA 1. At time t25, the second bank 1232 may output read DATA2 from at least one memory cell in the second bank 1232, and the memory controller 1100 may receive the read DATA 2.

In some example embodiments, the first control signal CTRL1 may include a value of a delay time interval BK1Latency from time t22 when a read command BK1 RD for the first bank 1231 is received by the non-volatile memory device 1200 to time t24 when read DATA1 is output from the first bank 1231. The second control signal CTRL2 may include a value of a delay time interval BK2Latency from time t23 when the read command BK2 RD for the second bank 1232 is received by the nonvolatile memory device 1200 to time t25 when the DATA2 is output from the second bank 1232. As shown in fig. 6, since there is a difference between "a time interval from a time t20 when the first control circuit 1211 receives the selection command BK1 SEL for the first bank 1231 to a time t24 when the first bank 1231 outputs the DATA 1" and "a time interval from a time t21 when the second control circuit 1212 receives the selection command BK2 SEL for the second bank 1232 to a time t25 when the second bank 1232 outputs the read DATA 2", the value of the delay time interval BK1Latency of the first bank 1231 and the value of the delay time interval BK2Latency of the second bank 1232 may be different from each other.

In some example embodiments, the time at which the read DATA1 is output from the first bank 1231 in response to the read command BK1 RD may be different from the time at which the read DATA2 is output from the second bank 1232 in response to the read command BK2 RD. In other embodiments, the signal applied to the first memory bank 1231 may be determined by the first control information in the register R1 of the first control circuit 1211 such that data is output from the first memory bank 1231 with the first time delay. The signal applied to the second memory bank 1232 may be determined by the second control information in the register R2 of the second control circuit 1212, so that the data is output from the second memory bank 1232 with the second time delay.

Fig. 8 is a block diagram illustrating a storage device including the nonvolatile memory device of fig. 2 according to some example embodiments of the inventive concepts. The memory controller may be the memory controller of fig. 6. The non-volatile memory device may comprise the architecture of the non-volatile memory device of fig. 2.

The memory controller 2100 may be substantially the same as the memory controller 1100 of fig. 6. Although not shown in fig. 8, the memory controller 2100 may include a buffer memory (e.g., the buffer memory 1121 of fig. 6).

Non-volatile memory device 2200 may be implemented with the architecture of fig. 2. The first through sixteenth banks 2210 through 2226 may be substantially the same as the first through sixteenth banks 211 through 226 of fig. 2. That is, the first through sixteenth banks 2210 through 2226 are divided into a first area 2230, a second area 2240, and a third area 2250. The command decoder 2260, the address buffer 2270, and the input/output circuit 2280 may be substantially the same as the command decoder 260, the address buffer 270, and the input/output circuit 280 of fig. 2, respectively.

The memory controller 2100 may divide the first through sixteenth banks 2210 through 2226 into a plurality of classes. For example, the memory controller 2100 may divide the first through sixteenth banks 2210 through 2226 into a first category and a second category. The first category may include first through eighth banks 2210 through 2218, and the second category may include ninth through sixteenth banks 2219 through 2226. In this case, the banks included in the same category may operate in the same mode, may have the same operation characteristics, and may operate according to the same operation setting. The memory controller 2100 may set the core control operation of the bank differently for each class. Here, the core control operation may mean an operation of setting a circuit generating a control signal for controlling the bank.

The memory controller 2100 may receive a request from an external device (e.g., a host) and may identify the received request. In this case, the received request may be identified according to the operating characteristics corresponding to the request. For example, the received request may correspond to an operating characteristic for reducing or minimizing power consumption, may correspond to an operating characteristic for operating at a faster speed, or may correspond to an operating characteristic with higher reliability. The memory controller 2100 may select an associated bank in response to the identified request. In this way, the non-volatile memory device 2200 may achieve optimal performance.

The memory controller 2100 may change the categories of the first through sixteenth banks 2210 through 2226. To change the category, an external device (e.g., a host) may send a reclassification request to the memory controller 2100, and the memory controller 2100 may change the categories of the first through sixteenth banks 2210 through 2226 in response to the reclassification request. For example, in response to the reclassification request, the memory controller 2100 may again divide the first through sixteenth banks 2210 through 2226 of the first and second classes into the third and fourth classes. Here, the third category may include thirteenth to sixteenth banks 2223 to 2226, and the fourth category may include first to twelfth banks 2211 to 2222. The operating characteristics of the banks included in the third category may correspond to the operating characteristics of the banks included in the first category, and the operating characteristics of the banks included in the fourth category may correspond to the operating characteristics of the banks included in the second category.

Similar to fig. 3, one example is shown in fig. 9 as: the number of banks included in the nonvolatile memory device 2200 is "16", but the inventive concept is not limited thereto. That is, the number of banks included in the nonvolatile memory device 2200 is not limited to any number.

Fig. 9 is a block diagram illustrating the memory controller of fig. 6. Fig. 9 will be described with reference to fig. 6. Referring to fig. 1 and 9, the memory controller 1100 may include a processor 1110, an SRAM 1120, a ROM 1130, a host interface 1140, and a memory interface 1150.

The processor 1110 may control the overall operation of the memory controller 1100, and may perform various logical operations. For example, the processor 1110 may include a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Neural Processing Unit (NPU), a Digital Signal Processor (DSP), or the like, and the number of processors may be two or more (e.g., a multi-core processor).

The SRAM 1120 may be used as a cache, a working memory, and/or a buffer memory (e.g., the buffer memory 1121 of fig. 6) of the memory controller 1100. SRAM 1120 may also be used as a cache memory for processor 1110. SRAM 1120 may store code and instructions to be executed by processor 1110. The SRAM 1120 may store data processed by the processor 1110.

The ROM 1130 may store various information for the operation of the memory controller 1100 in the form of firmware. In some example embodiments, various information (e.g., a flash translation layer and a mapping table) for controlling the nonvolatile memory device 1200 may be stored in the SRAM 1120, the ROM 1130, or a separate buffer memory, and may be managed or driven by the processor 1110.

The host interface 1140 may communicate with an external host under the control of the processor 1110. Host interface 1140 may send requests (e.g., read/write requests and reclassification requests) from a host to processor 1110 over bus 1160. In some example embodiments, host interface 1140 may include at least one of various interfaces, such as a Double Data Rate (DDR) interface, a low power DDR (lpddr) interface, a Universal Serial Bus (USB) interface, a multimedia card (MMC) interface, an embedded MMC (emmc) interface, a Peripheral Component Interconnect (PCI) interface, a PCI express (PCI-e) interface, an Advanced Technology Attachment (ATA) interface, a serial ATA (sata) interface, a parallel ATA (pata) interface, an external sata (esata) interface, a Small Computer System Interface (SCSI), an Enhanced Small Disk Interface (ESDI), an electronic Integrated Drive (IDE) interface, a Mobile Industry Processor Interface (MIPI), a high speed non-volatile memory (NVM-e) interface, and a universal flash memory (UFS) interface.

The memory interface 1150 may perform communication mediation between the nonvolatile memory device 1200 and the memory controller 1100 under the control of the processor 1110. That is, the memory controller 1100 may communicate with the nonvolatile memory device 1200 through the memory interface 1150. In some example embodiments, the memory controller 1100 may provide various signals (e.g., CMD, ADDR, and DQ) to the nonvolatile memory device 1200 based on the memory interface 1150.

Bus 1160 provides a communications path between the components of memory controller 1100. The components of memory controller 1100 may exchange data with one another based on the bus format of bus 1160. For example, the bus format may include one or more of various protocols, such as USB, SCSI, PCIe, ATA, PATA, SATA, IDE, and UFS.

The memory controller 1100 shown in fig. 9 is an example, and the inventive concept is not limited thereto. Memory controller 1100 may also include various components, such as an Error Correction Code (ECC) engine, a random generator, and buffer management circuitry.

The memory controller 1100 of fig. 9 may be described with respect to the memory device of fig. 6, but the memory controller 2100 of fig. 8 may be configured the same as the memory controller 1100 of fig. 9.

Fig. 10 is a flowchart illustrating an operation method of a memory controller according to some example embodiments of the inventive concepts. Fig. 10 will be described with reference to fig. 8.

In operation S110, the memory controller 2100 may divide a plurality of banks included in the nonvolatile memory device 2200 into a bank operating in a first mode and a bank operating in a second mode different from the first mode. In some other example embodiments, the memory controller 2100 may again divide the plurality of memory banks into a memory bank operating in a first mode, a memory bank operating in a second mode, and a memory bank operating in a third mode different from the first mode and the second mode. Although not shown in fig. 9, as described with reference to fig. 6, the memory controller 2100 may include a buffer memory in which a mapping table is stored, in which a first bank address of a bank operating in the first mode is mapped to the first mode and a second bank address of a bank operating in the second mode is mapped to the second mode.

In operation S120, the memory controller 2100 may receive a first request corresponding to the first mode from the host, and may transmit a first bank address corresponding to a first bank among the banks operating in the first mode to the non-volatile memory device 2200 in response to the first request. The memory controller 2100 may determine whether the first request corresponds to the first mode or the second mode.

The memory controller 2100 may also receive a second request corresponding to the second mode from the host, and may transmit a second bank address corresponding to a second bank among the banks operating in the second mode to the non-volatile memory device 2200 in response to the second request in operation S130. The memory controller 2100 may determine whether the second request corresponds to the first mode or the second mode.

In some example embodiments, after selecting the first bank of the nonvolatile memory apparatus 2200, the memory controller 2100 may send a third request for reading the first bank to the nonvolatile memory device 2200. Here, the second request may be sent to the non-volatile storage 2200 between the first request and the third request.

In some example embodiments, the memory controller 2100 may receive a write request corresponding to the first mode from a host, and may select a first bank of the banks operating in the first mode in response to the write request. The memory controller 2100 may determine a bank address that is a target of access based on a write request corresponding to the first mode. The memory controller 2100 may access a first bank corresponding to a bank address that is a target of access. However, the inventive concept is not limited thereto. For example, as in a write request, the memory controller 2100 may receive a bank address as a target of access from a host. The memory controller 2100 may perform a read/write operation on a memory cell included in one of the first banks.

The memory controller 2100 may receive a second read/write request from the host that includes a different command than the command included in the first read/write request. When a read/write operation is performed on a memory cell included in one of the first banks, the memory controller 2100 may access one of the second banks based on a second read/write request.

Fig. 11 is a flowchart illustrating a method for changing a category of a bank included in a nonvolatile memory device according to some example embodiments of the inventive concepts. Fig. 11 will be described with reference to fig. 8.

In operation S210, the memory controller 2100 may receive a reclassification request from a host.

In operation S220, the memory controller 2100 may map one of the first bank addresses to a second pattern in response to the reclassification request. However, the inventive concept is not limited thereto. For example, the memory controller 2100 may map one of the first bank addresses to a third pattern different from the first pattern and the second pattern in response to the reclassification request.

The non-volatile memory device according to some example embodiments of the inventive concepts may support operation settings differently for different requests of the host to each bank (or to respective banks), thereby optimizing performance.

A storage device including a nonvolatile memory device according to some example embodiments of the inventive concepts may change a category of a bank included in the nonvolatile memory device and may update a value for an operation setting of the bank.

Although described with reference to specific examples and drawings, modifications, additions, and substitutions of the example embodiments may be made by those of ordinary skill in the art in light of the description. For example, the described techniques may be performed in an order different than that of the described methods, and/or components such as the described systems, architectures, devices, circuits, etc. may be connected or combined differently than the methods described above, or the results may be suitably achieved by other components or equivalents.

Although the inventive concept has been described with reference to example embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the inventive concept as set forth in the following claims.