阅读说明：本技术 锁相环电路以及应用锁相环电路的设备 (Phase-locked loop circuit and apparatus using the same ) 是由 简思平 曹炜 李光明 俞波 于 2018-08-28 设计创作，主要内容包括：一种锁相环电路,涉及数字电路领域,用于跟踪和生成时钟信号。该锁相环电路包括目标频率相等的参考相位产生电路和时钟信号产生电路,上述参考相位产生电路根据第一参考相位信号产生第二参考相位信号,上述时钟产生电路根据上述第二参考相位信号产生输出时钟信号,其中上述第一参考相位信号、第二参考相位信号和输出时钟信号的相位差均为0。由于参考相位产生电路和时钟信号产生电路之间没有反馈支路,时钟信号产生电路中的杂散和抖动不会反馈至参考相位产生电路,因此提升了锁相环电路的整体性能,提高输出时钟信号的精度。(A phase-locked loop circuit relates to the field of digital circuits and is used for tracking and generating clock signals. The phase-locked loop circuit comprises a reference phase generating circuit and a clock signal generating circuit, wherein the target frequencies of the reference phase generating circuit and the clock signal generating circuit are equal, the reference phase generating circuit generates a second reference phase signal according to a first reference phase signal, the clock generating circuit generates an output clock signal according to the second reference phase signal, and the phase difference of the first reference phase signal, the second reference phase signal and the output clock signal is 0. Because there is no feedback branch between the reference phase generating circuit and the clock signal generating circuit, the stray and jitter in the clock signal generating circuit can not be fed back to the reference phase generating circuit, thereby improving the overall performance of the phase-locked loop circuit and improving the precision of the output clock signal.)

A phase locked loop circuit for generating an output clock signal, comprising a reference phase generating circuit and a clock signal generating circuit, wherein:

the reference phase generation circuit includes: a first phase detector, a first loop filter, a first digital integrator, and a first feedback circuit, wherein:

the first phase detector is used for receiving a first reference phase signal and a first feedback phase signal, comparing the phases of the first reference phase signal and the first feedback phase signal, and outputting the comparison result as a first comparison result to the first loop filter;

the first loop filter is configured to perform low-pass filtering on the received first comparison result, and output the first comparison result after the low-pass filtering to the first digital integrator;

the first digital integrator is used for generating the second reference phase signal according to the filtered first comparison result;

the first feedback circuit is configured to receive the second reference phase signal and output the second reference phase signal to the first phase detector as the first feedback phase signal.

The clock signal generating circuit is used for receiving the second reference phase signal and generating the output clock signal according to the second reference phase signal;

wherein a target frequency of the reference phase generating circuit is equal to a target frequency of the clock signal generating circuit, a phase difference between the first reference phase signal and the second reference phase signal is 0, and a phase difference between the second reference phase signal and the output clock signal is 0.

The phase-locked loop circuit of claim 1, wherein the first digital integrator is configured to control a phase change amount of the second reference phase signal in one clock cycle according to a first frequency control word, the first frequency control word being the filtered first comparison result.

A phase locked loop circuit as claimed in claim 1 or 2, wherein said reference phase generating circuit further comprises a second digital integrator for generating said first reference phase signal based on a second frequency control word for controlling the amount of phase change of said first reference phase signal in one clock cycle.

The phase-locked loop circuit of any one of claims 1 through 3, wherein the reference phase generation circuit further comprises a first interpolation circuit for synchronizing a frequency of the first reference phase signal with a frequency of the second reference phase signal and outputting the synchronized first reference phase signal to the first phase detector.

The phase-locked loop circuit of any one of claims 1 through 3, wherein the reference phase generation circuit further comprises a second interpolation circuit and a third interpolation circuit, wherein:

the second interpolation circuit is configured to synchronize a frequency of the filtered first comparison result generated by the first loop filter with a frequency of the second reference phase signal, and output the synchronized filtered first comparison result to the first digital integrator;

the first feedback circuit includes the third interpolation circuit, and the third interpolation circuit is configured to synchronize the frequency of the second reference phase signal generated by the first digital integrator with the frequency of the first reference phase signal, and feed the synchronized second reference phase signal back to the first phase detector.

The phase-locked loop circuit of claims 1 through 5, wherein the clock signal generation circuit comprises a second phase detector, a second loop filter, a voltage controlled oscillator, and a second feedback circuit, wherein:

the second phase discriminator is used for receiving the second reference phase signal and the second feedback phase signal, subtracting the second reference phase signal and the second feedback phase signal, and outputting the obtained phase difference to the second loop filter;

the second loop filter is used for receiving the phase difference, performing low-pass filtering on the phase difference and outputting the filtered phase difference to a voltage-controlled oscillator;

the voltage-controlled oscillator is used for receiving the filtered phase difference and generating an output clock signal according to the filtered phase difference;

the second feedback circuit is configured to convert the output clock signal generated by the voltage-controlled oscillator into the second feedback phase signal, and output the second feedback phase signal to the second phase detector.

A baseband processor comprising a radio frequency transceiver for converting low frequency digital signals to radio frequency signals and a phase locked loop circuit for providing a high frequency carrier to the radio frequency transceiver, wherein the phase locked loop circuit is as claimed in any one of claims 1 to 6

An optical module for transmitting and receiving an optical signal, the optical module comprising a clock synthesis circuit for providing a transmission clock to the multiplexer, a multiplexer for combining a plurality of signals into a single signal, and a laser for converting the single signal into an optical signal and transmitting, wherein the clock synthesis circuit comprises the phase-locked loop circuit as claimed in any one of claims 1 to 6