阅读说明：本技术 锁相环电路以及应用锁相环电路的设备 (Phase-locked loop circuit and apparatus using the same ) 是由 简思平 曹炜 李光明 俞波 于 2018-08-28 设计创作，主要内容包括：一种锁相环电路,涉及数字电路领域,用于跟踪和生成时钟信号。该锁相环电路包括目标频率相等的参考相位产生电路和时钟信号产生电路,上述参考相位产生电路根据第一参考相位信号产生第二参考相位信号,上述时钟产生电路根据上述第二参考相位信号产生输出时钟信号,其中上述第一参考相位信号、第二参考相位信号和输出时钟信号的相位差均为0。由于参考相位产生电路和时钟信号产生电路之间没有反馈支路,时钟信号产生电路中的杂散和抖动不会反馈至参考相位产生电路,因此提升了锁相环电路的整体性能,提高输出时钟信号的精度。(A phase-locked loop circuit relates to the field of digital circuits and is used for tracking and generating clock signals. The phase-locked loop circuit comprises a reference phase generating circuit and a clock signal generating circuit, wherein the target frequencies of the reference phase generating circuit and the clock signal generating circuit are equal, the reference phase generating circuit generates a second reference phase signal according to a first reference phase signal, the clock generating circuit generates an output clock signal according to the second reference phase signal, and the phase difference of the first reference phase signal, the second reference phase signal and the output clock signal is 0. Because there is no feedback branch between the reference phase generating circuit and the clock signal generating circuit, the stray and jitter in the clock signal generating circuit can not be fed back to the reference phase generating circuit, thereby improving the overall performance of the phase-locked loop circuit and improving the precision of the output clock signal.)