阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 徐成吉 于 2020-08-25 设计创作，主要内容包括：半导体装置。公开了一种包括一个或更多个晶体管的半导体装置。该半导体装置包括：第一有源区,其设置在基板的阱区上；多个虚设有源区,其围绕第一有源区设置；以及栅极,其设置成横穿第一有源区,其中栅极的一部分设置为与多个虚设有源区中的至少一个交叠,并且电联接到多个虚设有源区中的至少一个。(A semiconductor device is provided. A semiconductor device including one or more transistors is disclosed. The semiconductor device includes: a first active region disposed on the well region of the substrate; a plurality of dummy active regions disposed around the first active region; and a gate disposed to traverse the first active region, wherein a portion of the gate is disposed to overlap and electrically couple to at least one of the plurality of dummy active regions.)

1. A semiconductor device, comprising:

a first active region disposed on the well region of the substrate;

a plurality of dummy active regions disposed around the first active region; and

a gate disposed across the first active region;

wherein a portion of the gate electrode is disposed to overlap and electrically coupled to at least one of the plurality of dummy active regions.

2. The semiconductor device according to claim 1, wherein the first active region is provided in a central region of the well region and has a rectangular shape.

3. The semiconductor device according to claim 1, further comprising:

a second active region disposed at one side of the first active region with respect to a second direction; and

a third active region disposed at the other side of the first active region with respect to the second direction.

4. The semiconductor device according to claim 3,

the second active region and the third active region each have a line shape extending in a first direction, and the second active region and the third active region are spaced apart from each other by a predetermined distance in the second direction.

5. The semiconductor device of claim 1, wherein the plurality of dummy active regions comprises:

a first dummy active region disposed at one side of the first active region with respect to a first direction;

a second dummy active region disposed at the other side of the first active region with respect to the first direction;

a third dummy active region disposed at one side of the first active region with respect to the second direction; and

a fourth dummy active region, a fifth dummy active region, and a sixth dummy active region, the fourth dummy active region, the fifth dummy active region, and the sixth dummy active region being disposed at the other side of the first active region with respect to the second direction, wherein the fourth dummy active region, the fifth dummy active region, and the sixth dummy active region are spaced apart from each other by a predetermined distance in the first direction.

6. The semiconductor device according to claim 5,

the first dummy active region and the second dummy active region each have a line shape extending in the second direction and are longer than the first active region in the second direction.

7. The semiconductor device according to claim 5, wherein the first dummy active region and the second dummy active region are spaced apart from each other by a predetermined distance in the first direction.

8. The semiconductor device according to claim 5,

the third dummy active region is disposed between the first dummy active region and the second dummy active region in the first direction.

9. The semiconductor device according to claim 5, wherein the third dummy active region has the same width as the first active region in the first direction.

10. The semiconductor device of claim 5, wherein the fifth dummy source region is electrically coupled to the gate.

11. The semiconductor device according to claim 10, further comprising:

a gate through-silicon-via passing through the gate and coupled to the fifth dummy active region and configured to enable the fifth dummy active region to be coupled to the first metal layer.

12. The semiconductor device according to claim 11, further comprising:

a plurality of metal layers including the first metal layer, the plurality of metal layers formed over the substrate,

wherein the first metal layer is coupled to the gate and the fifth dummy active region through the gate TSV, and

a second metal layer of the plurality of metal layers is coupled to the first active region through a contact.

13. The semiconductor device according to claim 12,

the first metal layer is arranged above the grid electrode and the fifth virtual set source region along the vertical direction; and is

The second metal layer is disposed over the first active region along the vertical direction.

14. The semiconductor device according to claim 13, further comprising:

a third metal layer formed over the second metal layer in the vertical direction.

15. The semiconductor device according to claim 5, wherein the gate electrode has a hammer shape having a handle extending in the second direction and a head protruding in the first direction.

16. The semiconductor device according to claim 15, wherein a hammer head region of the gate electrode protruding in the first direction is disposed above the fifth dummy active region in a vertical direction.

17. The semiconductor device according to claim 5, further comprising:

a dummy gate disposed around edges of the plurality of dummy active regions when viewed in a vertical direction,

wherein a portion of the dummy gate traverses the third dummy active region in the second direction.

18. A semiconductor device, comprising:

a first active region formed on the well region of the substrate;

a plurality of dummy active regions formed on the well region and spaced apart from the first active region by a predetermined distance;

a gate disposed over one of the plurality of dummy active regions; and

a gate through-silicon-via coupled to the one dummy active region and passing through the gate, and configured to couple the one dummy active region to a first metal layer disposed over the gate.

19. The semiconductor device according to claim 18, further comprising:

a contact configured to couple the first active region to a second metal layer disposed over the first active region.

20. The semiconductor device of claim 18, wherein the gate is formed on a same line as the dummy active region in a vertical direction and is electrically coupled to the gate through silicon via.

21. A semiconductor device, comprising:

a first transistor region; and

a second transistor region arranged to be symmetrical to the first transistor region with respect to a first direction;

wherein the first transistor region and the second transistor region each include:

a first active region disposed on the well region of the substrate;

a dummy active region disposed on the well region and spaced apart from the first active region by a predetermined distance;

a gate formed over the dummy active region,

a gate through-silicon-via coupled to the dummy active region and passing through the gate; and

a first metal layer coupling the dummy active region to the gate.

22. The semiconductor device of claim 21, wherein the first transistor region and the second transistor region share the first metal layer that electrically couples the gate through silicon via of the first transistor region to the gate through silicon via of the second transistor region.

Technical Field

The techniques and implementations disclosed herein relate generally to a semiconductor device and, more particularly, to a semiconductor device including one or more transistors.

Background

Recently, with the continuous development of lighter, thinner, shorter, and smaller electronic products, the demand for highly integrated semiconductor devices is rapidly increasing. According to the trend of semiconductor devices to shrink, device isolation structures can be formed in smaller and narrower regions, so that variations in electrical characteristics occur more easily in smaller semiconductor devices.

Therefore, there is a need to develop a device isolation structure in which the change or degradation of electrical characteristics can be prevented from occurring in a smaller and narrower area. Further, there is an increasing demand for reducing the size of a formation region of one or more transistors used in constructing unit cells of a semiconductor device.

Disclosure of Invention

Various embodiments of the disclosed technology relate to a semiconductor device for improving stress of at least one transistor and for reducing the size of the entire area in which the transistor may be placed.

According to one embodiment of the disclosed technology, a semiconductor device may include: a first active region disposed on the well region of the substrate; a plurality of dummy active regions disposed around the first active region; and a gate disposed to traverse the first active region, wherein a portion of the gate is disposed to overlap and electrically couple to at least one of the plurality of dummy active regions.

According to another embodiment of the disclosed technology, a semiconductor device may include: a first active region formed on the well region of the substrate; a plurality of dummy active regions formed on the well region and spaced apart from the first active region by a predetermined distance; a gate disposed over one of the plurality of dummy active regions; and a gate-through-silicon via (gate-through-silicon via) coupled to the one dummy active region and passing through the gate, and configured to couple the one dummy active region to the first metal layer disposed over the gate.

According to still another embodiment of the disclosed technology, a semiconductor device may include: a first transistor region; and a second transistor region arranged to be symmetrical to the first transistor region with respect to the first direction, wherein the first and second transistor regions each include: a first active region disposed on the well region of the substrate; a dummy active region disposed on the well region and spaced apart from the first active region by a predetermined distance; a gate formed over the dummy active region, a gate through silicon via coupled to the dummy active region and passing through the gate; and a first metal layer coupling the dummy active region to the gate.

It is to be understood that both the foregoing general description and the following detailed description of the presently disclosed technology are exemplary and explanatory and are intended to provide further explanation of the scope of the disclosure to those skilled in the art.

Drawings

The above and other features and advantageous aspects of the disclosed technology will become apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

Fig. 1 is a diagram illustrating a layout structure of a semiconductor device according to one embodiment of the present disclosure.

Fig. 2 is a cross-sectional view illustrating an example of a semiconductor apparatus taken along the line Y-Y' shown in fig. 1 according to an embodiment of the present disclosure.

Fig. 3A to 3D are sectional views illustrating an example of a manufacturing process of the semiconductor device taken along the line Y-Y' shown in fig. 1 according to an embodiment of the present disclosure.

Fig. 4A to 4D are sectional views illustrating an example of a manufacturing process of the semiconductor device taken along the line X-X' shown in fig. 1 according to an embodiment of the present disclosure.

Fig. 5 is a diagram illustrating an example of a layout structure of a semiconductor device according to one embodiment of the present disclosure.

Fig. 6 is a cross-sectional view illustrating an example of the semiconductor apparatus taken along the line C-C' shown in fig. 5 according to one embodiment of the present disclosure.

Symbols of the various elements in the drawings:

DACT1 to DACT 6: multiple virtual source regions

ACT1 to ACT 3: multiple active regions

G: grid electrode

GTV: gate silicon through hole

Detailed Description

This patent document provides an implementation and an example of a semiconductor device that substantially solves one or more problems associated with the limitations or disadvantages of the related art. Some implementations of the disclosed technology propose a semiconductor device capable of improving stress of at least one transistor and reducing the size of the entire area of the transistor.

Reference will now be made in detail to aspects of the disclosed technology, embodiments and examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

Specific structural and functional descriptions are disclosed in connection with embodiments of the disclosed technology for purposes of illustration only. These embodiments represent a limited number of possible embodiments. However, implementations of the disclosed technology may be implemented in various or different ways, without departing from the scope or spirit of the disclosed technology.

In describing the disclosed technology, the terms "first" and "second" may be used to describe various components, but the components are not limited by these terms in number or order. These terms may be used to distinguish one component from another component. For example, a first component may be termed a second component, and a second component may be termed a first component, without departing from the scope of the present disclosure.

The terminology used in the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosed technology. Unless expressly stated otherwise, singular expressions may include plural expressions.

Unless otherwise defined, all terms (including technical or scientific terms) used herein have the same meaning as understood by one of ordinary skill in the art. Terms defined in a general dictionary may be analyzed to have the same meaning as the context of the related art, and should not be analyzed to have an ideal meaning or an excessively formal meaning unless explicitly defined in the present application. The terminology used in the disclosed technology is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

Fig. 1 is a diagram illustrating a layout structure of a semiconductor device according to one embodiment of the present disclosure.

Referring to fig. 1, a plurality of transistor regions TR1 and TR2 may be substantially identical in structure to each other, so that the following embodiments will be described hereinafter using only one transistor region TR1 as an example.

The transistor region TR1 may be implemented as an NMOS transistor or a PMOS transistor, but is not limited thereto. In addition, the transistor region TR2 may be implemented as an NMOS transistor or a PMOS transistor, but is not limited thereto.

The first direction (I) may refer to a direction perpendicular to the second direction (II). The third direction (III) may refer to a direction perpendicular to a horizontal plane extending in the first direction (I) and the second direction (II). For example, the third direction (III) may be perpendicular to each of the first direction (I) and the second direction (II).

The substrate 100 may include, for example, a semiconductor material such as silicon (Si) or germanium (Ge), or a compound semiconductor material such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The substrate 100 may include a conductive region such as a well doped with an impurity or a structure doped with an impurity.

The well region 110 may be formed in a designated area of the substrate 100. In this case, the substrate 100 may be doped with impurities to have a P-type or N-type conductive material.

For convenience of description, it is assumed that the substrate 100 is implemented as a P-type substrate. In some embodiments, the well region 110 may be doped with impurities to have a P-type or N-type conductive material. For convenience of description, it is assumed that the well region 110 is implemented as an N-type well.

The well region 110 may include a plurality of active regions ACT 1-ACT 3. The plurality of active regions ACT1 through ACT3 may be regions for receiving a source voltage, a drain voltage, and a body voltage of a transistor region.

The plurality of active regions ACT1 through ACT3 may be doped with impurities to have P-type or N-type conductivity. In some implementations, each of the plurality of active regions ACT 1-ACT 3 may be implemented as a P-type region doped with P-type impurities. The plurality of active regions ACT1 through ACT3 may be configured to have different sizes and different shapes according to the use of various circuit types.

The active region ACT1 may be located in a central region of the transistor TR 1. The active region ACT1 may be formed in a rectangular island shape.

The active regions ACT2 and ACT3 may be formed on both sides in the second direction (II) with respect to the central region of the transistor TR 1. That is, the active region ACT2 may be located on one side of the active region ACT1 in the second direction (II). The active region ACT3 may be located on the other side of the active region ACT1 in the second direction (II). Each of the active regions ACT2 and ACT3 may be formed in a linear shape extending in the first direction (I). The active region ACT2 and the active region ACT3 may be spaced apart from each other by a predetermined distance in the second direction (II). The active regions ACT2 and ACT3 may have the same or substantially the same length in the first direction (I).

In addition, a plurality of dummy active regions DACT1 through DACT6 may be formed on the substrate 100. A plurality of dummy active regions DACT1 to DACT6 may be each formed near the outer wall of the active region ACT1 formed in the central region. For example, when viewed in the third direction, a plurality of dummy active regions DACT1 to DACT6 may be arranged on the substrate 100 around the active region ACT1 in the first and second directions.

In some embodiments, a plurality of dummy active regions DACT1 through DACT6 may be provided to prevent stress from being applied to the transistors in the active region ACT 1. For example, the dummy active areas DACT1 through DACT6 may be formed near and adjacent to the active area ACT 1.

In a semiconductor device, unit elements (e.g., transistors, diodes, resistors, etc.) formed on a semiconductor substrate must be electrically isolated from each other. Accordingly, such a device isolation process can be completed using an initial stage process used in all semiconductor manufacturing processes. The initial stage process can greatly affect the size of each active region and the manufacturing margin of the subsequent process.

For example, a Shallow Trench Isolation (STI) process may solve instability caused by a manufacturing process, such as degradation of a field oxide film caused by design rules of a semiconductor device. Recently, in order to further improve the integration degree of highly integrated semiconductor memory devices, semiconductor memory devices have been developed to have smaller-sized constituent elements. Semiconductor memory devices with smaller elements may have trenches with weakened sidewalls due to stress in a Shallow Trench Isolation (STI) process. To address this possibility, the semiconductor device in embodiments of the disclosed technology may include a plurality of dummy active regions DACT1 through DACT6 in the semiconductor device to reduce or prevent stress in one or more transistors due to a Shallow Trench Isolation (STI) process.

Each of the plurality of dummy active regions DACT1 through DACT6 may be formed as a P-type region doped with P-type impurities. Although each of the plurality of dummy active regions DACT1 through DACT6 is formed as a P-type region for convenience of description in the embodiments disclosed herein, the scope or spirit of the disclosed technology is not limited thereto. In other embodiments, the plurality of dummy active areas DACT 1-DACT 6 may also be formed using other types of materials as desired.

Referring to fig. 1, dummy active areas DACT1 and DACT2 among the plurality of dummy active areas DACT1 through DACT6 may be disposed at both sides of the active area ACT1 with respect to a central area. Each of the dummy active areas DACT1 and DACT2 may be formed in a line shape extending in the second direction (II). Each of the dummy active areas DACT1 and DACT2 may be formed to have a longer length in the second direction (II) than the active area ACT 1. For example, the dummy active areas DACT1 may be disposed in the first direction from the active area ACT1 such that an edge or side of the dummy active area DACT1 overlaps an adjacent edge or side of the active area ACT1 or completely overlaps an adjacent edge or side of the active area ACT 1. Similarly, on the side of the active area ACT1 opposite the dummy active area DACT1, the dummy active area DACT2 may be disposed in the first direction from the active area ACT1 such that an edge or side of the dummy active area DACT2 overlaps an adjacent edge or side of the active area ACT1 or completely overlaps an adjacent edge or side of the active area ACT 1. The dummy active area DACT1 and the dummy active area DACT2 may be spaced apart from each other by a predetermined distance in the first direction (I). The active region ACT1 may be disposed between the dummy active region DACT1 and the dummy active region DACT 2.

The active region ACT1 and the active region ACT2 may be spaced apart from each other by a predetermined distance in the second direction (II). A dummy active region DACT3 may be formed between the active region ACT1 and the active region ACT 2. In other words, the dummy active area DACT3 may be positioned adjacent to or adjacent to the active area ACT 2. The dummy active regions DACT3 may be disposed between the dummy active regions DACT1 and DACT2 in the first direction (I). The virtual active area DACT3 may be formed in a rectangular or linear shape. The dummy active area DACT3 may have the same or substantially the same width in the first direction (I) as the active area ACT 1.

The active region ACT1 and the active region ACT3 may be spaced apart from each other by a predetermined distance in the second direction (II), and the active region ACT3 is located at the other side of the active region ACT1 opposite to the active region ACT 2. A plurality of dummy active regions DACT4 to DACT6 may be formed between the active region ACT1 and the active region ACT 3. Each of the plurality of dummy active regions DACT4 through DACT6 may be formed in a rectangular or linear shape.

The plurality of dummy active regions DACT4 through DACT6 may be disposed along the second direction (II) from a side (e.g., a lower side) of the plurality of dummy active regions DACT1 through DACT3, respectively. Each of the plurality of dummy active regions DACT4 through DACT6 may be adjacent to or abut the active region ACT 3. The dummy active regions DACT4 through DACT6 may be spaced apart from each other in the first direction (I) and may be spaced apart by a predetermined distance.

The gate (G) may be disposed over the active area ACT1 and the dummy active area DACT 5. The transistors TR1 and TR2 may be distinguished from each other by each having its respective gate.

The gate electrode (G) may be formed to extend in the second direction (II), and may be formed in an angular shape or a hammer shape. For example, the handle of the hammer shape may extend in the second direction (II), while the region (a) of the grid (G) corresponds to the head of the hammer shape and protrudes or extends in the first direction (I). In other words, the gate electrode (G) may extend in the second direction (II), and may be formed in an L-shaped structure in which a region (a) of the gate electrode (G) is bent in the first direction (I). The region (a) of the gate (G) may be disposed to overlap the dummy active area DAC 5. In this case, the region (a) of the gate (G) may be formed to supply a voltage to each transistor.

Region (a) of gate (G) may be electrically coupled to dummy active region DACT5 through gate through-silicon-vias (GTV). That is, the region (a) of the gate (G) and the dummy active region (DACT5) may be disposed on the same line in the third direction (III).

The region (a) of the gate electrode (G) and the dummy active area DACT5 may have the same size with respect to each of the first direction (I) and the second direction (II) or may have different sizes. In some embodiments, the region (a) of the gate (G) may be smaller in size than the dummy active area DACT5 with respect to each of the first direction (I) and the second direction (II).

Although the gate (G) is disposed to cross the active region ACT1 at or near the top surface of the active region ACT1, the gate (G) may not be disposed in the peripheral region of the transistor TR1, such as the region in which the dummy active regions DACT4 and DACT6 are disposed. Therefore, in the absence of the gate pattern in any particular region, there is a difference in pattern density, which may result in the gate pattern being realized unevenly in the exposure and etching steps.

Accordingly, the dummy gate DG may be formed such that any difference in separation distance between the gate patterns can be reduced by disposing the dummy gate DG. By implementing the dummy gates DG, the gate patterns can be spaced apart from each other at the same or substantially the same distance, more uniformly. In fig. 1, the dummy gate DG may be disposed adjacent to some edges of the dummy active regions DACT1 through DACT6 as viewed from the third direction. The dummy gate DG may be formed to surround the dummy active regions DACT1 and DACT 2. The dummy gate DG may be formed to cross a central region of the dummy active region DACT3 in the second direction (II).

The side or edge of the gate (G) may be spaced apart from the Dummy Gate (DG) by a predetermined distance in the first direction (I). The segments of the dummy gate DG may have substantially the same or the same width (e.g., width in the first direction I) as the gates (G) outside the region (a).

A plurality of metal contacts (M0C) may be formed over the active regions ACT1 through ACT 3. The plurality of metal contacts (M0C) may be spaced apart from each other by a predetermined distance in the first direction (I) at or near the top surfaces of the active regions ACT2 and ACT 3. The plurality of metal contacts (M0C) may be formed in a lattice or grid shape along the first direction (I) and the second direction (II) at or near the top surface of the active region (ACT 1).

As described above, a gate through silicon via (GTV) may be formed over the dummy active area DACT 5. The gate through silicon via (GTV) may be electrically coupled to a region (a) of the gate (G). In addition, a gate through silicon via (GTV) may be electrically coupled to the lower dummy active area DACT5 after passing through the gate (G).

In addition, a plurality of metal layers may be formed over the substrate 100 (M0). Each of the metal layers (M0) may be formed in a line shape extending in the second direction (II). The plurality of metal layers (M0) may be formed to have different lengths in the second direction (II) and may be staggered with respect to each other. The plurality of metal layers (M0) may be spaced apart from each other by a predetermined distance in the first direction (I). The plurality of metal layers (M0) may be electrically coupled to the active regions ACT 1-ACT 3 through metal contacts (M0C).

The metal layer (M0_1) may be disposed on an extension of the metal layer (M0). The metal layer (M0_1) may be formed in a line shape extending in the second direction (II). The metal layer (M0_1) may be electrically coupled to the gate (G) and the dummy active area DACT5 through a gate through silicon via (GTV). The metal layer (M0 — 1) may electrically couple the gate through silicon via (GTV) of the transistor region TR1 to the gate through silicon via (GTV) of the transistor region TR 2. That is, the gate (G) hammer region (a) of the transistor region TR1 may be electrically coupled to the gate (G) hammer region (a) of the transistor region TR2 through the metal layer (M0 — 1).

The metal layer M2 among the plurality of metal layers (M0) may be spaced apart from the metal layer (M0_1) by a predetermined distance in the first direction (I). The metal layer M2 may be formed in a line shape extending in the second direction (II). The metal layer (M2) may electrically couple the active region ACT1 of the transistor region TR1 to the active region ACT1 of the transistor region TR 2.

A plurality of metal contacts (M1C) may be formed over the metal layer (M0). The plurality of metal contacts (M1C) may be spaced apart from each other by a predetermined distance in the first direction (I).

Further, a plurality of metal layers (M1) may be formed over the metal layer (M0). Each metal layer (M1) may be formed in a line shape extending in the first direction (I). The metal layer (M1) may be electrically coupled to the active region ACT1 through metal contacts (M1C).

Fig. 2 is a cross-sectional view illustrating an example of the semiconductor apparatus shown in fig. 1, taken along the line Y-Y' shown in fig. 1, according to one embodiment of the present disclosure.

Referring to fig. 2, a well region 110 may be formed in the substrate 100 or on the substrate 100. In this case, the substrate 100 may be implemented as a P-type substrate doped with P-type impurities.

The well region 110 may include an active region ACT1 of the transistor and a dummy active region DACT 5. In this case, each of the active area ACT1 and the dummy active area DACT5 may be formed as a P-type region doped with P-type impurities.

A region (a) of a gate (G) of the transistor may be formed above the dummy active area DACT5 in the third direction (III). The gate electrode (G) may be formed in the interlayer insulating film 120 or on the interlayer insulating film 120. The interlayer insulating film 120 may be formed as an insulating layer such as an oxide film. The gate (G) may be electrically coupled to the lower dummy active area DACT5 through a gate through silicon via (GTV).

In some embodiments, the dummy active area DACT5 may be formed under the gate (G), i.e., the dummy active area DACT5 may be offset from the gate (G) in the second direction (II). In this example, if the dummy active region DACT5 is not formed under the gate electrode (G) in the third direction (III), but the dummy active region DACT5 is spaced apart from the side of the gate electrode (G), the width of the cross-section shown by the line Y-Y' may be increased so as to include the dummy active region DACT 5. Thus, in fig. 2, the dummy active area DACT5 disposed under the gate (G) is formed along the same vertical line and any distance separating the active area ACT1 and the dummy active area DACT5 is reduced or eliminated. The shorter width of line Y-Y' may correspond to a device isolation structure disposed in a smaller or narrower region in the semiconductor device.

Each of the metal contacts (M0C) may be formed between a top surface of the active region ACT1 and a bottom surface of the metal layer (M0). A gate through silicon via (GTV) may be formed between the bottom surface of the metal layer (M0_1) and the top surface of the dummy active area DACT5 while passing through the gate (G). The gate through silicon via (GTV) may electrically couple the upper metal layer (M0_1), the lower gate (G), and the dummy active area DACT5 to each other.

In some embodiments, the gate (G) and the dummy active area DACT5 may be electrically coupled to each other through a gate through silicon via (GTV). As a result, Plasma Induced Damage (PID) can be prevented from occurring in a subsequent plasma implantation process that requires protection of the sidewalls of the device isolation trench.

That is, the gate through silicon via (GTV) and the dummy active area DACT5 electrically coupled to the gate (G) may be used as a diode pattern capable of preventing Plasma Induced Damage (PID). As a result, deterioration of the electrical characteristics of the constituent elements of the semiconductor device can be prevented. More specifically, a shift in the threshold voltage of the transistor can be considered as one example of such deterioration in electrical characteristics.

Further, the metal layer (M0) and the metal layer (M0_1) may be formed in the same layer with respect to the third direction (III), and may be spaced apart from each other by a predetermined distance in the second direction (II). The metal contact (M1C) may be formed between the top surface of the metal layer (M0) and the bottom surface of the metal layer (M1). The metal layer (M1) may be formed over the metal layer (M0). The metal layer (M1) may be electrically coupled to the metal layer (M0) through a metal contact (M1C).

Fig. 3A to 3D are sectional views illustrating an example of a manufacturing process of the semiconductor device taken along the line Y-Y' shown in fig. 1 according to an embodiment of the present disclosure. Fig. 4A to 4D are sectional views illustrating an example of a manufacturing process of the semiconductor device taken along the line X-X' shown in fig. 1 according to an embodiment of the present disclosure. In fig. 3A to 3D and fig. 4A to 4D, some constituent elements identical to those of fig. 2 will be omitted herein for convenience of description.

Referring to fig. 3A and 4A, an impurity implantation process may be performed to adjust a doping density in the substrate 100, thereby forming the well region 110. In this case, the well region 110 may serve as a body of a device (e.g., a transistor).

Active regions ACT1 and dummy active regions DACT5 of the transistors may be formed in the well region 110. In this case, the active region ACT1 and the dummy active region DACT5 may be formed by Shallow Trench Isolation (STI), local oxidation of silicon (LOCOS) process, or the like.

In addition, a gate (G) of a transistor may be formed over the dummy active area DACT 5. That is, the gate (G) may be formed over the dummy active area DACT5 in the vertical direction or the third direction (III). After forming an oxide film (not shown) and a conductive line over the dummy active area DACT5, the conductive line may be etched in response to a gate length of a corresponding transistor, thereby forming a pattern of a gate (G). The gate (G) may correspond to a hammer region (a) to be coupled to upper and lower metal lines (not shown).

In this case, the gate electrode (G) may be formed of various conductive materials. For example, the gate electrode (G) may be formed of any one selected from metal, metal and polysilicon, and polysilicon. In some embodiments, the gate (G) may be formed of metal and polysilicon.

Thereafter, as shown in fig. 3B and 4B, the gate electrode (G) formed above the dummy active area DACT5 in the vertical direction may be etched, thereby forming a contact hole H1. In this case, the contact hole H1 may be etched to expose the top surface of the dummy active area DACT 5.

Subsequently, as shown in fig. 3C and 4C, an interlayer insulating film 120 may be deposited over the entire surface of the gate (G) structure. In this case, the interlayer insulating film 120 may include a nitride film or an oxide film.

The interlayer insulating film 120 may be etched to form the contact hole H2. In this case, the contact hole H2 may be etched to expose the top surface of the active region ACT 1. Therefore, the lower active region ACT1 and the contacts for connecting the dummy active region DACT5 and the upper metal lines may be electrically isolated from each other. When the interlayer insulating film 120 is etched, the hole H1 of the gate electrode (G) may be opened or reopened.

Thereafter, as shown in fig. 3D and 4D, the contact holes H1 and H2 may be buried with a contact plug material, thereby enabling the formation of a metal contact (M0C) and a gate through silicon via (GTV). Accordingly, the gate through silicon via (GTV), the gate (G), and the dummy active area DACT5 may physically contact each other. In this case, the material buried in the contact hole H1 to form the gate through silicon via (GTV) may be the same as the material buried in the contact hole H2 to form the metal contact (M0C).

In some embodiments, in order to improve electrical characteristics, a boundary region in which the contact hole H1 contacts the gate (G) and the dummy active region DACT5 may be additionally buried with a certain material.

The specific material buried in the boundary area where the contact hole H1 contacts the gate (G) and the dummy active area DACT5 should be electrically coupled to the gate (G) and the dummy active area DACT5 so that the specific material may be formed of a conductive material. In this case, the conductive material may include a metal material such as tungsten (W), titanium (Ti), and titanium nitride (TiN), may include polysilicon, or may include metal and polysilicon.

Thereafter, a metal layer (M0) may be deposited over the metal contact (M0C), and a metal layer (M0_1) may be deposited over the gate through silicon via (GTV).

Fig. 5 is a diagram illustrating an example of a layout structure of a semiconductor device according to one embodiment of the present disclosure. Fig. 6 is a cross-sectional view illustrating an example of the semiconductor apparatus taken along the line C-C' shown in fig. 5 according to one embodiment of the present disclosure. In fig. 5 and 6, the same constituent elements as those in fig. 1 and 2 are denoted by the same reference numerals, and thus a detailed description thereof will be omitted herein for convenience of description.

Referring to fig. 5 and 6, the transistor region TR1 and the transistor TR2 may be symmetrical to each other on a line crossing therebetween in the first direction (I). That is, the transistor region TR1 and the transistor region TR2 may be arranged to face each other while having a mirror-symmetrical structure with respect to the first direction (I).

In fig. 6, the gate through silicon via (GTV) of the transistor region TR1 and the gate through silicon via (GTV) of the transistor region TR2 may be electrically coupled to each other through a metal layer (M0_ 1). That is, the gate (G) of the transistor region TR1, the gate (G) of the transistor region TR2, and the dummy active region DACT5 of each transistor may be electrically coupled to each other through a metal layer (M0_ 1).

As is apparent from the above description, the semiconductor device based on the embodiment of the disclosed technology can improve the stress of at least one transistor and can reduce the overall size of the region to be occupied.

Embodiments of the disclosed technology may provide various effects that can be directly or indirectly recognized through the above-mentioned patent documents.

It will be appreciated by those of ordinary skill in the art that the embodiments can be practiced in other specific ways than those set forth herein without departing from the spirit and essential characteristics of the present disclosure. The above-described embodiments are therefore to be construed in all aspects as illustrative and not restrictive. The scope of the disclosure should be determined by the appended claims and their legal equivalents, rather than by the description above. Furthermore, all changes which come within the meaning and range of equivalency of the appended claims are to be embraced within their scope. Further, it should be understood by those skilled in the art that claims that are not explicitly cited in each other in the appended claims may be presented in combination as an embodiment or included as a new claim by subsequent amendment after the application is filed.

While a number of illustrative embodiments have been described, it will be appreciated that those skilled in the art will be able to devise numerous other modifications and embodiments which will fall within the spirit and scope of the principles of this disclosure. In particular, various modifications and variations may be made in the component parts and/or arrangements of the subject disclosure within the scope of the disclosure, the drawings and the appended claims. In addition to variations and modifications in the component parts and/or arrangements, alternative uses will also be apparent to those skilled in the art.

Cross Reference to Related Applications

This patent document claims priority and benefit from korean patent application No.10-2020-0032699, filed on 17.3.2020, which is incorporated herein by reference in its entirety.