阅读说明：本技术 半导体装置和数据驱动器 (Semiconductor device and data driver ) 是由 土弘 于 2020-03-23 设计创作，主要内容包括：目的在于提供能够抑制芯片占有面积的增加并且缩短放大电路的输出响应时间的半导体装置和数据驱动器。在本发明中,在包括将与由差动级生成的第一差动信号对应的电流送出到输出端子的第一输出晶体管、以及从输出端子抽出与第一差动信号相同相位且电位不同的第二差动信号所对应的电流的第二输出晶体管的差动放大器中,设置包括与使第一差动信号的电平进行移位的电平移位信号对应地向输出端子送出电流的第三输出晶体管、以及与使第二差动信号的电平进行移位的电平移位信号对应地从上述输出端子抽出电流的第四输出晶体管的升压电路。采用与第一和第二输出晶体管相比针对栅极源极间电压的耐压较低、漏极电流较大的晶体管来作为第三和第四输出晶体管。(A semiconductor device and a data driver capable of shortening the output response time of an amplifier circuit while suppressing an increase in the chip-occupied area. In the present invention, a differential amplifier including a first output transistor for sending a current corresponding to a first differential signal generated by a differential stage to an output terminal, and a second output transistor for extracting a current corresponding to a second differential signal having the same phase as the first differential signal and a different potential from the first differential signal from the output terminal is provided with a booster circuit including a third output transistor for sending a current to the output terminal corresponding to a level shift signal for shifting a level of the first differential signal, and a fourth output transistor for extracting a current from the output terminal corresponding to a level shift signal for shifting a level of the second differential signal. As the third and fourth output transistors, transistors having a lower withstand voltage with respect to the voltage between the gate and the source and a larger drain current than the first and second output transistors are used.)

1. A semiconductor device is characterized by comprising:

an input terminal for receiving an input signal;

an output terminal for outputting an output signal;

a first power supply terminal and a second power supply terminal that receive a first power supply potential and a second power supply potential lower than the first power supply potential, respectively;

a differential stage that generates a first differential signal corresponding to a difference between the input signal and the output signal and a second differential signal having the same phase as the first differential signal and different potential;

a first output transistor of a first conductivity type connected to the first power supply terminal, receiving the first differential signal at its control terminal, and supplying a current corresponding to the first differential signal to the output terminal based on the first power supply potential;

a second output transistor of a second conductivity type connected to the second power supply terminal, receiving the second differential signal at its control terminal, and causing a current corresponding to the second differential signal to flow from the output terminal to the second power supply terminal;

a first potential control circuit that generates a first shift signal for level-shifting the first differential signal to the first power supply potential side;

a second potential control circuit that generates a second shift signal for level-shifting the second differential signal to the second power supply potential side;

a third output transistor of the first conductivity type connected to the first power supply terminal, receiving the first shift signal at its own control terminal, and supplying a current corresponding to the first shift signal to the output terminal based on the first power supply potential; and

a fourth output transistor of the second conductivity type connected to the second power supply terminal, receiving the second shift signal at its own control terminal, and causing a current corresponding to the second shift signal to flow from the output terminal to the second power supply terminal,

the third output transistor is a transistor having a lower withstand voltage with respect to a voltage between the first power supply terminal and the control terminal than the first output transistor and having a larger drain current corresponding to the voltage between the first power supply terminal and the control terminal,

the fourth output transistor is a transistor having a lower withstand voltage with respect to a voltage between the second power supply terminal and the control terminal than the second output transistor, and having a larger drain current corresponding to the voltage between the second power supply terminal and the control terminal.

2. The semiconductor device according to claim 1, comprising:

a third power supply terminal that receives a third power supply potential having a potential equal to or higher than the first power supply potential; and

a fourth power supply terminal for receiving a fourth power supply potential having a potential equal to or lower than the second power supply potential,

the first potential control circuit includes a first load element having a first terminal connected to the first power supply terminal and a second terminal connected to the control terminal of the third output transistor, and a first transistor and a second transistor of a first conductivity type cascade-connected between the second terminal of the first load element and the fourth power supply terminal, the first transistor receiving the first differential signal at the control terminal thereof and receiving a first bias signal at the control terminal thereof, whereby the first shift signal is output from the second terminal of the first load element,

the second potential control circuit includes a second load element having a first terminal connected to the second power supply terminal and a second terminal connected to the control terminal of the fourth output transistor, and a third transistor and a fourth transistor of a second conductivity type cascade-connected between the second terminal of the second load element and the third power supply terminal, and the second potential control circuit outputs the second shift signal from the second terminal of the second load element by receiving the second differential signal at the control terminal of the third transistor and receiving a second bias signal at the control terminal of the fourth transistor.

3. The semiconductor device according to claim 2, wherein the first load element is formed of a current source or a resistance element, and wherein the second load element is formed of a current source or a resistance element.

4. The semiconductor device according to claim 2 or 3,

the first potential control circuit includes a first switch that connects the second terminal of the first load element and the first power supply terminal when set to an on state,

the second potential control circuit includes a second switch that connects the second terminal of the second load element and the second power supply terminal when set to an on state,

the first switch and the second switch are both set to the on state only during a predetermined period from the power-on time point.

5. The semiconductor device according to claim 2 or 3,

the first potential control circuit includes a plurality of diode-connected transistors cascade-connected between the second terminal of the first load element and the first power supply terminal,

the second potential control circuit includes a plurality of diode-connected transistors cascade-connected between the second terminal of the second load element and the second power supply terminal.

6. The semiconductor device according to any one of claims 1 to 5, wherein the differential stage has:

a first current source and a second current source;

a first differential pair of a second conductivity type receiving a first input and a second input forming an input pair and introducing a current of 2 minutes based on the first input and the second input, the current being generated by the first current source, from an output pair thereof;

a second differential pair of the first conductivity type receiving the first input and the second input and outputting a current obtained by dividing a current generated by the second current source by 2 from its own output pair based on the first input and the second input;

a first cascode gate mirror circuit of a first conductivity type connected to the output pair of the first differential pair, and configured to output a current corresponding to a current introduced into the output pair of the first differential pair to a first terminal thereof and to output a current corresponding to the current output to the first terminal to a second terminal thereof;

a first parasitic current source having one end connected to the first end of the first cascode current-mirror circuit;

a second parasitic current source having one end connected to the second end of the first cascode current-mirror circuit; and

a second cascode gate mirror circuit of a second conductivity type connected to the output pair of the second differential pair, and having a first terminal to which a current corresponding to a current sent from the output pair of the second differential pair is supplied and a second terminal to which a current corresponding to a current supplied to the first terminal is supplied,

receiving the first input at the input terminal, and receiving an output signal output from the output terminal as the second input,

the other end of the first parasitic current source is connected to the first end of the second cascode current-mirror circuit, the other end of the second parasitic current source is connected to the second end of the second cascode current-mirror circuit,

the first differential signal is output from the second terminal of the first cascode gate-mirror circuit, and the second differential signal is output from the second terminal of the second cascode gate-mirror circuit.

7. The semiconductor device according to any one of claims 1 to 6,

the first output transistor and the second output transistor are both MOS transistors,

the third output transistor and the fourth output transistor are configured such that an insulating film between a gate electrode and a semiconductor layer forming the control terminal is thinner than that of the first output transistor, or are transistors of an LDMOS (laterally diffused MOS) type.

8. A semiconductor device is characterized by comprising:

an input terminal for receiving an input signal;

an output terminal for outputting an output signal;

a first power supply terminal and a second power supply terminal that receive a first power supply potential and a second power supply potential different from the first power supply potential, respectively;

a differential stage that generates a first differential signal corresponding to a difference between the input signal and the output signal and a second differential signal having the same phase as the first differential signal and different potential;

a first output transistor of a first conductivity type connected to the first power supply terminal, receiving the first differential signal at its control terminal, and outputting a current corresponding to the first differential signal to the output terminal based on the first power supply potential;

a second output transistor of a second conductivity type connected to the second power supply terminal, receiving the second differential signal at its control terminal, and outputting a current corresponding to the second differential signal to the output terminal based on the second power supply potential;

a first potential control circuit that generates a first shift signal for level-shifting the first differential signal to the first power supply potential side; and

a third output transistor of the first conductivity type connected to the first power supply terminal, receiving the first shift signal at its own control terminal, and outputting a current corresponding to the first shift signal to the output terminal based on the first power supply potential,

the third output transistor is a transistor having a lower withstand voltage with respect to a voltage between the first power supply terminal and the control terminal than the first output transistor, and having a larger drain current corresponding to the voltage between the first power supply terminal and the control terminal.

9. The semiconductor device according to claim 8, comprising a third power supply terminal which receives a third power supply potential having a potential difference equal to or greater than the second power supply potential in a same direction as the first power supply potential,

the first potential control circuit includes a first load element having a first terminal connected to the first power supply terminal and a second terminal connected to the control terminal of the third output transistor, and a first transistor and a second transistor of a first conductivity type cascade-connected between the second terminal of the first load element and the third power supply terminal, and outputs the first shift signal from the second terminal of the first load element by receiving the first differential signal at the control terminal of the first transistor and receiving a first bias signal at the control terminal of the second transistor.

10. The semiconductor device according to claim 9, wherein the first load element is formed of a current source or a resistance element.

11. The semiconductor device according to claim 9 or 10,

the first potential control circuit includes a first switch that connects the second terminal of the first load element and the first power supply terminal when set to an on state,

the first switch is set to an on state only during a predetermined period from a power-on time point.

12. The semiconductor device according to claim 9 or 10, wherein the first potential control circuit includes a plurality of diode-connected transistors connected in cascade between the second terminal of the first load element and the first power supply terminal.

13. The semiconductor device according to any one of claims 8 to 13,

the first output transistor and the second output transistor are both MOS transistors,

the third output transistor is configured such that an insulating film between a gate electrode and a semiconductor layer forming the control terminal is thinner than that of the first output transistor, or is a LDMOS (lateral diffusion MOS) type transistor.

14. A data driver comprising a plurality of amplifier circuits which individually amplify a plurality of gradation voltages each having a voltage value corresponding to a luminance level of each of a plurality of pixels and supply the amplified voltages to a display device, wherein each of the amplifier circuits comprises:

an input terminal for receiving the gradation voltage as an input signal;

an output terminal for supplying an output signal obtained by amplifying the gradation voltage to the display device;

a first power supply terminal and a second power supply terminal that receive a first power supply potential and a second power supply potential different from the first power supply potential, respectively;

a differential stage that generates a first differential signal corresponding to a difference between the input signal and the output signal and a second differential signal having the same phase as the first differential signal and different potential;

a first output transistor of a first conductivity type connected to the first power supply terminal, receiving the first differential signal at its control terminal, and outputting a current corresponding to the first differential signal to the output terminal based on the first power supply potential;

a second output transistor of a second conductivity type connected to the second power supply terminal, receiving the second differential signal at its control terminal, and outputting a current corresponding to the second differential signal to the output terminal based on the second power supply potential;

a first potential control circuit that generates a first shift signal for level-shifting the first differential signal to the first power supply potential side; and

a third output transistor of the first conductivity type connected to the first power supply terminal, receiving the first shift signal at its own control terminal, and outputting a current corresponding to the first shift signal to the output terminal based on the first power supply potential,

the third output transistor is a transistor having a lower withstand voltage with respect to a voltage between the first power supply terminal and the control terminal than the first output transistor, and having a larger drain current corresponding to the voltage between the first power supply terminal and the control terminal.

15. The data driver of claim 14, further comprising:

a second potential control circuit that generates a second shift signal for level-shifting the second differential signal to the second power supply potential side; and

a fourth output transistor of a second conductivity type connected to the second power supply terminal, receiving the second shift signal at its own control terminal, and outputting a current corresponding to the second shift signal to the output terminal based on the second power supply potential,

the fourth output transistor is a transistor having a lower withstand voltage with respect to a voltage between the second power supply terminal and the control terminal than the second output transistor, and having a larger drain current corresponding to the voltage between the second power supply terminal and the control terminal.

Technical Field

The present invention relates to a semiconductor device in which an amplifier circuit is formed and a data driver of a display device.

Background

Currently, as an active matrix display device, a liquid crystal display device, an organic EL display device, and the like are mainstream. In such a display device, a data driver that supplies analog voltage signals corresponding to a gray scale level to a plurality of data lines of a display panel and a scan driver that supplies scan signals for controlling on/off of each pixel switch to a plurality of scan lines of the display panel are mounted together with the display panel in which a plurality of data lines and a plurality of scan lines are arranged in a matrix and display cells connected to the plurality of data lines via the pixel switches are arranged in a crossing manner.

In addition, recently, with the increase in screen size and resolution of display panels, the load capacitance of the data lines of the display panels has increased, and the driving period per 1 pixel for driving the data lines by the data driver tends to be shortened. Here, the data driver charges or discharges a load capacitance of the data line in accordance with an input signal corresponding to a luminance level indicated by the video signal, and thereby supplies an output signal corresponding to the input signal to the data line.

Therefore, when the load capacitance of the data line becomes large and the driving period becomes short, the amplification operation cannot follow the level change of the input video signal, and accordingly, a delay occurs in the rise or fall of the voltage level of the output signal, and image quality deterioration such as display unevenness may be caused.

In order to prevent such a problem, a data driver is proposed which is provided with a circuit (hereinafter referred to as a booster circuit (boost) circuit) for shortening a rise time and a fall time of an output signal outputted from an output stage of the data driver, i.e., a so-called output response time (see, for example, fig. 1 of patent document 1).

The booster circuit includes MOS (metal oxide semiconductor) type first to third transistors. The first transistor (MP 9, MN 9) generates a constant current and supplies it to the source terminal of the second transistor (MP 8, MN 8). The gate terminal of the second transistor is connected to the gate terminal of an output transistor included in an operational amplifier (24) as an amplification circuit. The gate terminal of the third transistor (MPO 2, MNO 2) is connected to the source terminal of the second transistor. A power supply potential is applied to a source terminal of the third transistor, and a drain terminal is connected to an output terminal of the operational amplifier.

With such a configuration, when, for example, the voltage level of an input signal to the operational amplifier increases and then the voltage level of an output signal output from the output terminal of the operational amplifier increases, during this, the second and third transistors (MP 8, MPO 2) become on-state. When the third transistor is turned on, the transistor sends a current corresponding to the gate potential to the output terminal of the operational amplifier, thereby charging the output terminal. This can accelerate the increase speed of the voltage level of the output signal and shorten the rise time.

Disclosure of Invention

Problems to be solved by the invention

However, the potential of the gate terminal of the third transistor (MPO 2, MNO 2) described above becomes a potential shifted by the amount of the threshold voltage of the second transistor (MP 8, MN 8) from the potential of the gate terminal of the output transistor (MP 0, MN 0) of the operational amplifier (24). Therefore, the gate | Vgs | of the third transistor (MPO 2, MNO 2) becomes lower than | Vgs | of the output transistor (MP 0, MN 0) of the operational amplifier (24), and therefore, there is a possibility that the third transistor does not become an on state.

Therefore, in order to shorten the output response time by such a booster circuit, the size (particularly, the gate width) of the third transistor (MPO 2, MNO 2) must be increased, which causes a problem of an increase in chip area.

Thus, the present invention provides a semiconductor device and a data driver capable of suppressing an increase in chip occupation area and shortening the output response time of an amplification circuit.

Means for solving the problems

The semiconductor device of the present invention includes: an input terminal for receiving an input signal; an output terminal for outputting an output signal; first and second power supply terminals that receive a first power supply potential and a second power supply potential lower than the first power supply potential, respectively; a differential stage that generates a first differential signal corresponding to a difference between the input signal and the output signal and a second differential signal having the same phase as the first differential signal and different potential; a first output transistor of a first conductivity type connected to the first power supply terminal, receiving the first differential signal at its control terminal, and supplying a current corresponding to the first differential signal to the output terminal based on the first power supply potential; a second output transistor of a second conductivity type connected to the second power supply terminal, receiving the second differential signal at its control terminal, and causing a current corresponding to the second differential signal to flow from the output terminal to the second power supply terminal; a first potential control circuit that generates a first shift signal for level-shifting the first differential signal to the first power supply potential side; a second potential control circuit that generates a second shift signal for level-shifting the second differential signal to the second power supply potential side; a third output transistor of the first conductivity type connected to the first power supply terminal, receiving the first shift signal at its own control terminal, and supplying a current corresponding to the first shift signal to the output terminal based on the first power supply potential; and a fourth output transistor of a second conductivity type connected to the second power supply terminal, the fourth output transistor receiving the second shift signal at its control terminal and flowing a current corresponding to the second shift signal from the output terminal to the second power supply terminal, the third output transistor having a lower withstand voltage against a voltage between the first power supply terminal and the control terminal than the first output transistor and having a larger drain current corresponding to the voltage between the first power supply terminal and the control terminal, the fourth output transistor having a lower withstand voltage against a voltage between the second power supply terminal and the control terminal than the second output transistor and having a larger drain current corresponding to the voltage between the second power supply terminal and the control terminal.

The semiconductor device of the present invention includes: an input terminal for receiving an input signal; an output terminal for outputting an output signal; first and second power supply terminals that receive a first power supply potential and a second power supply potential different from the first power supply potential, respectively; a differential stage that generates a first differential signal corresponding to a difference between the input signal and the output signal and a second differential signal having the same phase as the first differential signal and different potential; a first output transistor of a first conductivity type connected to the first power supply terminal, receiving the first differential signal at its control terminal, and outputting a current corresponding to the first differential signal to the output terminal based on the first power supply potential; a second output transistor of a second conductivity type connected to the second power supply terminal, receiving the second differential signal at its control terminal, and outputting a current corresponding to the second differential signal to the output terminal based on the second power supply potential; a first potential control circuit that generates a first shift signal for level-shifting the first differential signal to the first power supply potential side; and a third output transistor of the first conductivity type connected to the first power supply terminal, receiving the first shift signal at its own control terminal, and outputting a current corresponding to the first shift signal to the output terminal based on the first power supply potential, wherein the third output transistor is a transistor having a lower withstand voltage with respect to a voltage between the first power supply terminal and the control terminal than the first output transistor and having a larger drain current corresponding to the voltage between the first power supply terminal and the control terminal.

A data driver according to the present invention is a data driver including a plurality of amplifier circuits that individually amplify a plurality of gradation voltages each having a voltage value corresponding to a luminance level of each of a plurality of pixels and supply the amplified voltages to a display device, each of the amplifier circuits including: an input terminal for receiving the gradation voltage as an input signal; an output terminal for supplying an output signal obtained by amplifying the gradation voltage to the display device; first and second power supply terminals that receive a first power supply potential and a second power supply potential different from the first power supply potential, respectively; a differential stage that generates a first differential signal corresponding to a difference between the input signal and the output signal and a second differential signal having the same phase as the first differential signal and different potential; a first output transistor of a first conductivity type connected to the first power supply terminal, receiving the first differential signal at its control terminal, and outputting a current corresponding to the first differential signal to the output terminal based on the first power supply potential; a second output transistor of a second conductivity type connected to the second power supply terminal, receiving the second differential signal at its control terminal, and outputting a current corresponding to the second differential signal to the output terminal based on the second power supply potential; a first potential control circuit that generates a first shift signal for level-shifting the first differential signal to the first power supply potential side; and a third output transistor of the first conductivity type connected to the first power supply terminal, receiving the first shift signal at its own control terminal, and outputting a current corresponding to the first shift signal to the output terminal based on the first power supply potential, wherein the third output transistor is a transistor having a lower withstand voltage with respect to a voltage between the first power supply terminal and the control terminal than the first output transistor and having a larger drain current corresponding to the voltage between the first power supply terminal and the control terminal.

Effects of the invention

In the present invention, the following booster circuit is provided in a differential amplifier including a first output transistor for sending a current corresponding to a first differential signal generated by a differential stage to an output terminal, and a second output transistor for extracting a current corresponding to a second differential signal having the same phase as the first differential signal and a different potential from the first differential signal from the output terminal. That is, a booster circuit including at least one of a third output transistor that receives a level shift signal for shifting the level of the first differential signal at a gate terminal and sends a current to an output terminal, and a fourth output transistor that receives a level shift signal for shifting the level of the second differential signal at a gate terminal and draws a current from the output terminal is provided. At this time, transistors having higher drain currents and lower withstand voltages for gate-seed-source voltages than those of the first and second output transistors are used as the third and fourth output transistors.

With such a configuration, the speed of charging and discharging with respect to the load connected to the output terminal can be accelerated without increasing the element size of the third or fourth output transistor of the booster circuit, and therefore, the output response time of the amplifier circuit can be shortened without increasing the chip-occupied area and increasing the cost.

Drawings

Fig. 1 is a block diagram showing a schematic configuration of a display device 200 including a data driver as a semiconductor device of the present invention.

Fig. 2 is a block diagram showing an internal structure of the data driver 103.

Fig. 3 is a circuit diagram showing a first embodiment of the amplifying circuit 100.

Fig. 4 is a characteristic diagram showing the gate-to-source voltage-to-drain current characteristics of the transistor included in the amplifier circuit 100.

Fig. 5 is a circuit diagram showing a second embodiment of the amplifying circuit 100.

Fig. 6 is a circuit diagram showing a third embodiment of the amplifying circuit 100.

Fig. 7 is a circuit diagram showing a fourth embodiment of the amplifying circuit 100.

Fig. 8 is a circuit diagram of the differential stage 10A.

Detailed Description

Fig. 1 is a block diagram showing a schematic configuration of a display device 200 including a data driver as a semiconductor device of the present invention.

As shown in fig. 1, the display device 200 has a display panel 80, a drive control section 101, a scan driver 102, and a data driver 103.

The display panel 80 is formed of, for example, a liquid crystal panel, an organic EL panel, or the like, and includes r (r is a natural number of 2 or more) horizontal scanning lines S1 to Sr extending in the horizontal direction of the two-dimensional screen, and n (n is a natural number of 2 or more) data lines D1 to Dn extending in the vertical direction of the two-dimensional screen. Display cells serving as pixels are formed at intersections of the horizontal scanning lines and the data lines.

The drive control section 101 supplies a scan timing signal for generating a horizontal scan pulse to be supplied to each horizontal scan line to the scan driver 102.

Further, the drive control unit 101 generates a control signal such as a start pulse signal STP or a clock signal CLK and a video digital signal DVS including a sequence of video data pieces each representing a luminance level of each pixel by, for example, 8 bits, based on the video signal VD, and supplies the generated control signal to the data driver 103.

The scan driver 102 sequentially applies horizontal scan pulses to the horizontal scan lines S1 to Sr of the display panel 80 based on the scan timing signal supplied from the drive control section 101.

The data driver 103 introduces a sequence of pieces of video data (hereinafter referred to as video data PD) included in the video digital signal DVS in accordance with the control signals (STP, CLK) supplied from the drive control unit 101. Then, the data driver 103 converts the sequence of the introduced video data PD into n drive voltages G1 to Gn having voltage values of magnitudes corresponding to the luminance levels of the respective data lines for 1 horizontal scanning line (n), and supplies the respective data voltages to the data lines D1 to Dn of the display panel 80.

Fig. 2 is a block diagram showing an internal structure of the data driver 103.

The data driver 103 is formed in a semiconductor IC chip, and includes a shift register 801, a data register latch 802, a level shifter 803, a reference voltage generating circuit 804, a decoder 805, an output unit 806, and a bias voltage generating circuit 807 as shown in fig. 2.

The shift register 801 generates latch timing signals U1 to Un for selecting latches in synchronization with a clock signal CLK based on a start pulse STP supplied from the drive control unit 101, and supplies the latch timing signals to the data register latches 802.

The data register latch 802 sequentially takes in the video data PD supplied from the drive control unit 101 based on the latch timing signals U1 to Un, and supplies the video data signals R1 to Rn indicating the video data PD to the level shifter 803 every 1 horizontal scanning line (n).

The level shifter 803 supplies n video data signals J1 to Jn, which are obtained by applying a level shift process of increasing the signal level to each of the video data signals R1 to Rn, to the decoder 805.

The reference voltage generation circuit 804 generates reference voltages V0 to V255 corresponding to, for example, 256 gradations, and supplies these reference voltages V0 to V255 to the decoder 805.

The decoder 805 selects a reference voltage corresponding to the video data signal from among the reference voltages V0 to V255 for each of the video data signals J1 to Jn. Then, the decoder 805 supplies the gradation voltage signals F1 to Fn having the reference voltages selected for each of the video data signals J1 to Jn to the output unit 806.

The bias voltage generation circuit 807 generates a plurality of bias signals for setting an operation current for operating the output unit 806, and supplies the bias signals to the output unit 806. The first and second bias signals VBP and VBN are also generated by the bias voltage generation circuit 807.

The output unit 806 outputs signals amplified individually for the gradation voltage signals F1 to Fn as the drive voltage signals G1 to Gn. The driving voltage signals G1 to Gn output from the output unit 806 are supplied to the data lines D1 to Dn of the display panel 80, respectively.

As shown in fig. 2, the output unit 806 includes n amplifier circuits 100 having the same internal configuration and provided in one-to-one correspondence with the gradation voltage signals F1 to Fn.

Each of the amplifier circuits 100 operates in response to the power supply potentials E1 to E4, generates an output signal VO having a voltage value corresponding to the input signal VI and having an amplified current amount based on the received input signal VI, and outputs the output signal VO from the output terminal N2.

For example, the amplifier circuit 100 that receives the gradation voltage signal F1 as the input signal VI generates an output signal VO having a voltage value corresponding to the gradation voltage signal F1 and having an amplified current amount as the driving voltage signal G1, and outputs the output signal VO. The amplifier circuit 100 that receives the gradation voltage signal F2 as the input signal VI generates an output signal VO having a voltage value corresponding to the gradation voltage signal F2 and having an amplified current amount as the drive voltage signal G2, and outputs the output signal VO.

[ example 1]

Fig. 3 is a circuit diagram showing an internal configuration of the amplification circuit 100 as the first embodiment.

The amplifier circuit 100 includes an input terminal N1 that receives the input signal VI, an output terminal N2 that outputs the output signal VO as a result of amplification, and first to fourth power supply terminals NE1 to NE4 that receive first to fourth power supply potentials E1 to E4, respectively.

The power supply potentials E1 to E4 have the following magnitude relationships, for example.

E3≥E1＞E2≥E4

Further, the amplifier circuit 100 includes: the differential amplifier includes a differential stage 10, a first output transistor 11 of a first conductivity type (P-channel type), a second output transistor 12 of a second conductivity type (N-channel type), and a booster circuit BST.

The differential stage 10 receives the input signal VI received at the input terminal N1 at its non-inverting input terminal (+) and receives the output signal VO of the output terminal N2 at its inverting input terminal (-) as well. The differential stage 10 outputs a first differential signal VN3 corresponding to the difference between the input signal VI and the output signal VO via its first output terminal N3, and outputs a second differential signal VN4 having the same phase and different potential as the first differential signal VN3 from a second output terminal N4.

In the first output transistor 11, a first terminal (source) of itself is connected to the first power supply terminal NE1, and a second terminal (drain) is connected to the output terminal N2. The output transistor 11 receives the first differential signal VN3 output from the first output terminal N3 of the differential stage 10 at its own control terminal (gate). The output transistor 11 supplies a current corresponding to the first differential signal VN3 to the output terminal N2 based on the first power supply potential E1.

In the second output transistor 12, a first terminal (source) of itself is connected to the second power supply terminal NE2, and a second terminal (drain) is connected to the output terminal N2. The output transistor 12 receives the second differential signal VN4 output from the second output terminal N4 of the differential stage 10 at its own control terminal (gate). The output transistor 12 causes a current corresponding to the second differential signal VN4 to flow from the output terminal N2 to the second power supply terminal NE 2.

When the level of the input signal VI changes more than a predetermined value, the boost circuit BST sends a current to the output terminal N2, thereby shortening the output response time of the output signal VO output from the output transistors 11 and 12 in response to the input signal VI.

The booster circuit BST includes a first potential control circuit 20, a second potential control circuit 30, a third output transistor 13 of a first conductivity type (P-channel type), and a fourth output transistor 14 of a second conductivity type (N-channel type).

The first potential control circuit 20 includes first and second transistors 21 and 22 of a first conductivity type (P-channel type), and a first load element 23 as a first load whose own first terminal is connected to a power supply terminal NE 1. As the first load element 23, for example, a resistance element or a current source may be employed.

In the transistor 21, a second terminal (drain) thereof is connected to the power supply terminal NE4, and a first terminal (source) is connected to a second terminal (drain) of the transistor 22. The transistor 21 receives a first differential signal VN3 output from a first output terminal N3 of the differential stage 10 at its control terminal (gate). In the transistor 22, a first terminal (source) thereof is connected to the second terminal of the first load element 23 and the control terminal (gate) of the output transistor 13 via a node N5. The transistor 22 receives a bias signal VBP supplied from the bias voltage generation circuit 807 at its control terminal (gate). As such, the first and second transistors 21 and 22 are cascade-connected between the second terminal (N5) of the first load element 23 and the power supply terminal NE 4. Further, the positions of the first and second transistors 21 and 22 cascade-connected between the second terminal (N5) of the first load element 23 and the power supply terminal NE4 may be switched.

With such a configuration, the first potential control circuit 20 receives the first differential signal VN3 output from the differential stage 10, generates the first shift signal VN5 that is level-shifted toward the first power supply potential E1 side, and supplies the first shift signal VN to the control terminal (gate) of the output transistor 13.

The second potential control circuit 30 includes third and fourth transistors 31 and 32 of a second conductivity type (N-channel type), and a second load element 33 as a second load whose own first terminal is connected to a second power supply terminal NE 2. As the second load element 33, for example, a resistance element may be employed.

In the transistor 31, a second terminal (drain) thereof is connected to the power supply terminal NE3, and a first terminal (source) is connected to a second terminal (drain) of the transistor 32. The transistor 31 receives the second differential signal VN4 output from the second output terminal N4 of the differential stage 10 at its control terminal (gate). In the transistor 32, a first terminal (source) thereof is connected to the second terminal of the second load element 33 and the control terminal (gate) of the output transistor 14 via a node N6. The transistor 32 receives a bias signal VBN supplied from the bias voltage generation circuit 807 at its control terminal (gate). As such, the third and fourth transistors 31 and 32 are cascade-connected between the second terminal (N6) of the second load element 33 and the power supply terminal NE 3. Further, the positions of the third and fourth transistors 31 and 32 cascade-connected between the second terminal (N6) of the second load element 33 and the power supply terminal NE3 may be switched.

With such a configuration, the second potential control circuit 30 receives the second differential signal VN4 output from the differential stage 10, generates the second shift signal VN6 for level-shifting toward the second power supply potential E2 side, and supplies the second shift signal VN to the control terminal (gate) of the output transistor 14.

Here, the second transistor 22 functions as a clamp (clamp) element, and is controlled by the first bias signal VBP so as not to exceed a withstand voltage between the first terminal (source) and the control terminal (gate) of the third output transistor 13, which will be described below. Hereinafter, the absolute value of the maximum voltage that can be applied between the gate and the source of the transistor, which is the breakdown voltage, is referred to as the Vgs maximum applied voltage.

The first bias signal VBP has a potential level-shifted from the first power supply potential E1 toward the fourth power supply potential E4 side by an amount of voltage not exceeding the sum voltage of the Vgs maximum applied voltage of the output transistor 13 and the threshold voltage (absolute value) of the transistor 22.

Thereby, the first shift signal VN5 is limited to a voltage range from the first power supply potential E1 to the Vgs maximum applied voltage of the output transistor 13.

Similarly, the fourth transistor 32 functions as a clamp element, and is controlled by the second bias signal VBN so as not to exceed a withstand voltage (Vgs maximum applied voltage) between the first terminal (source) and the control terminal (gate) of the fourth output transistor 14 described below.

Therefore, the second bias signal VBN has a potential shifted from the second power supply potential E2 to the third power supply potential side by an amount of voltage not exceeding the sum voltage of the Vgs maximum applied voltage of the output transistor 14 and the threshold voltage of the transistor 32.

Thereby, the second shift signal VN6 is limited to the voltage range from the second power supply potential E2 to the Vgs maximum applied voltage of the output transistor 14.

In the third output transistor 13, a first terminal (source) thereof is connected to the first power supply terminal NE1, and a second terminal (drain) is connected to the output terminal N2. The output transistor 13 receives the first shift signal VN5 output from the first potential control circuit 20 at its own control terminal (gate). The output transistor 13 supplies a current corresponding to the first shift signal VN5 to the output terminal N2 based on the first power supply potential E1.

In the fourth output transistor 14, a first terminal (source) thereof is connected to the second power supply terminal NE2, and a second terminal (drain) is connected to the output terminal N2. The output transistor 14 receives the second shift signal VN6 output from the second potential control circuit 30 at its own control terminal (gate). The output transistor 14 flows a current corresponding to the second shift signal VN6 from the output terminal N2 to the second power supply terminal NE 2.

Here, the third and fourth output transistors 13 and 14 have different gate-seed-source-intermediate voltage-drain current characteristics from those of the first and second output transistors 11 and 12 described above.

Fig. 4 is a characteristic diagram showing the gate-to-source voltage-to-drain current characteristics of the transistor included in the amplifier circuit 100.

Here, all the transistors (11, 12, 21, 22, 31, 32) except for the output transistors 13 and 14 among the transistors included in the amplification circuit 100 have the gate-to-source voltage-to-drain current characteristics shown by the characteristic curve L1 in fig. 4. On the other hand, the output transistors 13 and 14 have the gate-seed-source-intermediate voltage-drain current characteristics shown in the characteristic curve L2 of fig. 4.

As shown in fig. 4, the third output transistor 13 is, for example, a transistor in which the drain current amount | Ids/W | corresponding to the voltage | Vgs | between the first terminal (source) and the control terminal (gate) is larger and the withstand voltage (Vgs maximum applied voltage) between the first terminal (source) and the control terminal (gate) is lower than the first output transistor 11. As the output transistor 13 of the first conductivity type (P channel type) having such characteristics, for example, a transistor in which a gate insulating film is formed thinner than the first output transistor 11 or, for example, an LDMOS (laterally diffused MOS) transistor of the first conductivity type (P channel type) is used. Note that the withstand voltage between the first terminal (source) and the second terminal (drain) of the output transistor 13 of the first conductivity type (P-channel type) may be equal to or higher than that of the first output transistor 11.

Similarly, the fourth output transistor 14 is, for example, a transistor in which the drain current amount Ids/W corresponding to the voltage Vgs between the first terminal (source) and the control terminal (gate) is larger and the withstand voltage (Vgs maximum applied voltage) between the first terminal (source) and the control terminal (gate) is lower than that of the second output transistor 12. As the output transistor 14 of the second conductivity type (N-channel type) having such characteristics, for example, a transistor in which a gate insulating film is formed thinner than the second output transistor 12 or, for example, an LDMOS (laterally diffused MOS) transistor of the second conductivity type (N-channel type) is used. Note that the withstand voltage between the first terminal (source) and the second terminal (drain) of the output transistor 14 of the second conductivity type (N-channel type) may be equal to or higher than that of the second output transistor 12.

Hereinafter, the operation of the amplifier circuit 100 shown in fig. 1 will be described with the transistor of the first conductivity type (P-channel type) referred to as a "PMOS transistor" and the transistor of the second conductivity type (N-channel type) referred to as an "NMOS transistor".

The amplifying circuit 100 shown in fig. 3 has a negative feedback structure in which the input terminal N1 is connected to the non-inverting input terminal (+) of the differential stage 10 and the output terminal N2 is connected to the inverting input terminal (-). In this case, in the example shown in fig. 2, the input signal VI received by each amplifier circuit 100 is the gradation voltage signal F output from the decoder 805. Therefore, in each data period of the video data piece corresponding to each pixel, a step signal of a voltage level corresponding to a gradation indicating a luminance level of the pixel is input to the amplifier circuit 100 as an input signal VI, and an output voltage VO corresponding to the input signal VI is output from the output terminal N2. Of the power supply potentials E1 to E4 received by the amplifier circuit 100, for example, the power supply potentials E1 and E3 are high power supply potentials, and the power supply potentials E2 and E4 are low power supply potentials.

Here, as an initial state, when the input signal VI is a constant voltage and the output voltage VO is in an output stable state, the voltage values of the first differential signal VN3 and the second differential signal VN4 output from the output terminals N3 and N4 of the differential stage 10 are constant, respectively. That is, the respective gate ­ to-source voltages | Vgs | of the PMOS transistor 11 and the NMOS transistor 12 are stabilized at a voltage slightly larger than the absolute value of the threshold voltage of each. When both the PMOS transistor 11 and the NMOS transistor 12 are in the on state, the reactive current flowing through each is controlled to be a sufficiently small current by the first and second differential signals VN3, VN 4.

With regard to the PMOS transistor 21 included in the first potential control circuit 20, the first shift signal VN5 of the node N5 is controlled to a potential as high as the threshold voltage (absolute value) of the PMOS transistor 21 in accordance with the first differential signal VN3 of the differential stage 10. Here, when the threshold voltages of the PMOS transistors 11 and 21 are made the same degree, the first shift signal VN5 of the node N5 in the output steady state has a voltage sufficiently close to the power supply potential E1. At this time, the PMOS transistor 22 has a sufficiently higher gate/seed/source voltage than a threshold voltage (absolute value), and is turned on. Therefore, the PMOS transistor 13 receiving the first shift signal VN5 at the control terminal (gate) is turned off because the gate/seed/source voltage difference is smaller than the threshold voltage (absolute value).

Further, as for the NMOS transistor 31 included in the second potential control circuit 30, the second shift signal VN6 of the node N6 is controlled to a potential as low as the threshold voltage level of the NMOS transistor 31 in accordance with the second differential signal VN4 of the differential stage 10. Here, when the threshold voltages of the NMOS transistors 12 and 31 are made the same degree, the second shift signal VN6 of the node N6 in the output steady state has a voltage sufficiently close to the power supply potential E2. At this time, the NMOS transistor 32 is in an on state in which the gate/seed/source voltage difference is sufficiently larger than the threshold voltage. Therefore, the NMOS transistor 14 receiving the second shift signal VN6 at the control terminal (gate) has a smaller voltage difference between its own gate and seed and source than the threshold voltage, and turns off.

As described above, when the input signal VI is at a constant voltage and the output voltage VO is in the output stable state, both the PMOS transistor 13 and the NMOS transistor 14, which are output transistors, are turned off.

Next, an operation in the case where the level voltage of the input signal VI changes toward the power supply potential E1 (toward the high potential side) in the next data period from the data period in which both the input signal VI and the output signal VO are in the steady state will be described. At this time, the first and second differential signals VN3, VN4 of the first and second output terminals N3, N4 of the differential stage 10 each change toward the power supply potential E2 side (low potential side), and the NMOS transistor 12 becomes off. On the other hand, the PMOS transistor 11 is turned on by expanding its own gate/seed/source voltage difference, and a current based on the power supply potential E1 is sent to the output terminal N2, whereby the output terminal N2 and a load capacitance of a data line, which is a load connected to the output terminal N2, are charged.

Further, when the second differential signal VN4 of the differential stage 10 decreases, the second shift signal VN6 output from the second potential control circuit 30 decreases to the power supply potential E2. Therefore, the NMOS transistor 14 continues to maintain the off state. Further, when the first differential signal VN3 of the differential stage 10 decreases, the first shift signal VN5 output from the first potential control circuit 20 also decreases from around the power supply potential E1. The difference in voltage between the gate and the seed of the PMOS transistor 13 is enlarged by the first shift signal VN5, and when the threshold voltage of the PMOS transistor 13 is exceeded, the PMOS transistor 13 becomes conductive. Thus, the PMOS transistor 13 sends a current based on the power supply potential E1 to the output terminal N2, thereby charging the parasitic capacitance of the data line, which is the load connected to the output terminal N2. That is, the charging speed is promoted by cooperation with the charging operation performed by the PMOS transistor 11 described above.

However, as described above, the PMOS transistor 13 has the gate/seed/source voltage/drain current characteristics shown in the characteristic curve L2 of fig. 4. Therefore, the PMOS transistor 13 has higher current driving capability than the PMOS transistor 11, and the PMOS transistor 11 has the gate-to-source voltage-to-drain current characteristic shown by the characteristic curve L1 in fig. 4. Therefore, even if the gate seed-source voltage difference of the PMOS transistor 13 is smaller than the gate seed-source voltage difference of the PMOS transistor 11 by the amount of the threshold voltage (absolute value) of the PMOS transistor 21, the PMOS transistor 13 can charge the load connected to the output terminal N2 with high current drive capability. Therefore, even if the element size of the PMOS transistor 13 is reduced, the load connected to the output terminal N2 can be appropriately charged by the PMOS transistor 13, and the chip occupation area of the amplifier circuit 100 can be reduced.

When the first differential signal VN3 of the differential stage 10 is greatly reduced, the first shift signal VN5 is also reduced in accordance therewith, but the potential variation of the first shift signal VN5 is limited by the PMOS transistor 22 to a voltage range up to the withstand voltage (Vgs maximum applied voltage) of the PMOS transistor 13. Thus, with respect to the PMOS transistor 13, the self gate/seed/source voltage is limited to within the withstand voltage, thereby preventing element destruction due to the withstand voltage exceeding.

Then, when the potential of the load connected to the output terminal N2 approaches the output signal VO corresponding to the input signal VI, the first and second differential signals VN3, VN4 of the first and second output terminals N3, N4 of the differential stage 10 gradually rise from the lowered potential and become a stable state when returning to the potential of the initial state. Similarly, the first shift signal VN5 also rises following the first differential signal VN3, and becomes a steady state when returning to the potential in the initial state. The PMOS transistor 13 is stable in the off state.

Next, an operation in the case where the input signal VI changes to the level voltage on the power supply potential E2 side (low potential side) in the next data period from the data period in which both the input signal VI and the output signal VO are in the steady state will be described. At this time, the first and second differential signals VN3, VN4 of the first and second output terminals N3, N4 of the differential stage 10 each change toward the power supply potential E1 side (high potential side), and the PMOS transistor 11 becomes off. In contrast, the NMOS transistor 12 expands the difference in voltage between its own gate and seed and source to turn on, and discharges the charge accumulated in the load connected to the output terminal N2, that is, the load capacitance of the data line.

Further, when the first differential signal VN3 of the differential stage 10 rises, the first shift signal VN5 output from the first potential control circuit 20 rises to the power supply potential E1. Accordingly, the PMOS transistor 13 becomes an off state. Further, when the second differential signal VN4 of the differential stage 10 rises, the second shift signal VN6 output from the second potential control circuit 30 also rises from near the power supply potential E2. By the second shift signal VN6, the difference in voltage between the gate and the seed of the NMOS transistor 14 is enlarged, and when the threshold voltage of the NMOS transistor 14 is exceeded, the NMOS transistor 14 becomes conductive.

Thereby, the NMOS transistor 14 discharges the electric charge accumulated in the load connected to the output terminal N2, that is, the load capacitance of the data line. That is, the discharge speed is promoted by cooperation with the discharge operation by the NMOS transistor 12 described above.

However, as described above, the NMOS transistor 14 has the gate-to-source voltage-to-drain current characteristic shown in the characteristic curve L2 of fig. 4. Therefore, the NMOS transistor 14 has higher current driving capability than the NMOS transistor 12, and the NMOS transistor 12 has the gate-source-drain voltage-drain current characteristic shown by the characteristic curve L1 in fig. 4. Therefore, even if the gate/seed/source voltage difference of the NMOS transistor 14 is smaller than the gate/seed/source voltage difference of the NMOS transistor 12 by the threshold voltage of the NMOS transistor 31, the NMOS transistor 14 can charge the load connected to the output terminal N2 with high current driving capability. Therefore, even if the element size of the NMOS transistor 14 is reduced, the charge accumulated in the load connected to the output terminal N2 can be appropriately discharged by the NMOS transistor 14, and therefore, the chip occupation area of the amplifier circuit 100 can be reduced.

When the second differential signal VN4 of the differential stage 10 has greatly increased, the second shift signal VN6 also increases in accordance therewith, but the potential variation of the second shift signal VN6 is limited by the NMOS transistor 32 to a voltage range up to the withstand voltage (Vgs maximum applied voltage) of the NMOS transistor 14. Thus, with respect to the NMOS transistor 14, the gate/seed/source voltage is limited to within the withstand voltage, thereby preventing element destruction due to the withstand voltage excess.

Then, when the potential of the load connected to the output terminal N2 approaches the output signal VO corresponding to the input signal VI, the first and second differential signals VN3, VN4 of the first and second output terminals N3, N4 of the differential stage 10 gradually decrease from the rising potential and become a stable state when returning to the potential of the initial state. Similarly, the second shift signal VN6 also decreases in accordance with the second differential signal VN4, and becomes a steady state when returning to the potential in the initial state. The NMOS transistor 14 becomes off-state and stable.

As described above, in the amplifier circuit 100 shown in fig. 3, for example, an element having a larger drain current for a gate-seed-source voltage than a normal MOS transistor, such as an LDMOS transistor, is used as the output transistors 13 and 14 of the booster circuit BST. As for the LDMOS transistor, an element is used which has a withstand voltage equal to or higher than that of a normal MOS transistor and is lower than that of a drain/seed/source voltage | Vds | with respect to the gate/seed/source voltage | Vgs |.

That is, in the amplification circuit 100, as the output transistors 13 and 14 included in the booster circuit BST, transistors such as LDMOS transistors, for example, having a higher drain current for a gate-to-source voltage and a lower withstand voltage for a gate-to-source voltage than the output transistors 11 and 12 included in the differential amplifier are used. Thus, in the amplifier circuit 100, the transistors 22 and 32 are provided, and the transistors 22 and 32 limit the variation range of the gate potentials of the two transistors (13, 14) in such a manner that the withstand voltage for the gate-to-source voltage of the output transistors 13 and 14 is not exceeded. However, the transistors 22 and 32 may be omitted as long as a design is performed such that the first differential signal VN3 of the differential stage 10 is always above the bias signal VBP and the second differential signal VN4 of the differential stage 10 is always below the bias signal VBN.

In short, the amplifier circuit 100 including the input terminal (N1) for receiving the input signal (VI) and the output terminal (N2) for outputting the amplified output signal (VO) may include the following first and second power supply terminals, a differential stage, first and second potential control circuits, and first to fourth output transistors.

That is, each of the first and second power supply terminals (NE 1, NE 2) receives a first power supply potential (E1) and a second power supply potential (E2) lower than the first power supply potential, respectively.

A differential stage (10) generates a first differential signal (VN 3) corresponding to the difference between an input signal and an output signal, and a second differential signal (VN 4) having the same phase as the first differential signal and a different potential.

The first output transistor (11) is of a first conductivity type (P-channel type), is connected to a first power supply terminal (NE 1), receives a first differential signal (VN 3) at its control terminal (gate), and supplies a current corresponding to the first differential signal to an output terminal (N2) based on a first power supply potential.

The second output transistor (12) is of a second conductivity type (N-channel type), is connected to the second power supply terminal (NE 2), receives the second differential signal (VN 4) at its control terminal (gate), and causes a current corresponding to the second differential signal to flow from the output terminal (N2) to the second power supply terminal (NE 2).

The first potential control circuit (20) generates a first shift signal (VN 5) for level-shifting the first differential signal (VN 3) to the first power supply potential (E1) side.

The second potential control circuit (30) generates a second shift signal (VN 6) for level-shifting the second differential signal (VN 4) to the second power supply potential (E2) side.

The third output transistor (13) is of a first conductivity type (P-channel type), is connected to a first power supply terminal (NE 1), receives a first shift signal (VN 5) at its control terminal (gate), and supplies a current corresponding to the first shift signal to an output terminal (N2) based on the first power supply potential.

The fourth output transistor (14) is of a second conductivity type (N-channel type), is connected to the second power supply terminal (NE 2), receives the second shift signal (VN 6) at its own control terminal (gate), and causes a current corresponding to the second shift signal to flow from the output terminal (N2) to the second power supply terminal.

The third output transistor (13) has a lower withstand voltage against the voltage (Vgs) between the first power supply terminal and the control terminal than the first output transistor (11), and has a larger drain current corresponding to the voltage (Vgs) between the first power supply terminal and the control terminal. The fourth output transistor (14) is a transistor having a lower withstand voltage against the voltage (Vgs) between the second power supply terminal and the control terminal than the second output transistor (12), and having a larger drain current corresponding to the voltage (Vgs) between the second power supply terminal and the control terminal.

Therefore, according to the amplifier circuit 100 shown in fig. 3, the speed of charging and discharging with respect to a load (for example, a load capacitance of a data line) can be accelerated without increasing the element size of the output transistors 13 and 14. Therefore, according to the present invention, the output response time of the amplifier circuit can be shortened without increasing the chip occupation area and increasing the cost.

In the first embodiment, the configuration in which the amplifier circuit 100 includes the booster circuit BST of all of the first and second potential control circuits 20 and 30 and the third and fourth output transistors 13 and 14 has been described, but the amplifier circuit may be configured by only one of the first potential control circuit 20 and the third output transistor 13, or the second potential control circuit 30 and the third output transistor 14. Preferably, the amplifier circuit 100 is configured such that one of the charging rate and the discharging rate of the output terminal N2 is particularly increased.

[ example 2]

Fig. 5 is a circuit diagram showing an internal configuration of an amplification circuit 100 as a second embodiment of the present invention, which employs current sources 23A and 33A as a first load element 23 and a second load element 33 included in the first and second potential control circuits 20 and 30 shown in fig. 3, respectively. Note that, in the configuration shown in fig. 5, the configuration is the same as that shown in fig. 3, except that the current sources 23A and 33A are used as the first load element 23 and the second load element 33 shown in fig. 3.

In fig. 5, the current source 23A is connected between the node N5 and the power supply terminal NE1 as shown in fig. 5, generates a predetermined constant current based on the power supply potential E1 received at the power supply terminal NE1, and sends the generated constant current to the node N5 shown in fig. 5. As shown in fig. 5, the current source 33A is connected between the node N6 and the power supply terminal NE2, and draws a predetermined constant current from the node N6.

The current values of the constant currents flowing through the current sources 23A and 33A are set to values that do not prevent the fluctuations of the first and second shift signals VN5 and VN6, respectively. Specifically, the current source 23A may be a PMOS transistor that receives a predetermined bias voltage at its gate. Similarly, the current source 33A may be formed of an NMOS transistor that receives a predetermined bias voltage at its gate. The current sources 23A and 33A stably maintain the output transistors 13 and 14 in an off state in the output stable state, respectively.

[ example 3]

Fig. 6 is a circuit diagram showing an internal configuration of an amplification circuit 100 as a third embodiment of the present invention, which employs another internal configuration as the first and second potential control circuits 20 and 30 shown in fig. 5. Note that, in the configuration shown in fig. 6, the withstand voltage protection circuits 24 and 34 are newly provided in the first and second potential control circuits 20 and 30 of the booster circuit BST, respectively, and the configuration is the same as that shown in fig. 5 except for this point.

The withstand voltage protecting circuit 24 includes, for example, a transistor 24A of the first conductivity type (P-channel type) having its own first terminal (source) connected to the power supply terminal NE1 and its second terminal (drain) connected to the control terminal (gate) of the output transistor 13 via a node N5. The transistor 24A receives a control signal XCTL at its control terminal (gate).

The withstand voltage protecting circuit 34 includes, for example, a transistor 34A of a second conductivity type (N-channel type) having its own first terminal (source) connected to the power supply terminal NE2 and its second terminal (drain) connected to the control terminal (gate) of the output transistor 14 via a node N6. The transistor 34A receives a control signal CTL at its control terminal (gate).

The control signals CTL and XCTL are signals having opposite phases to each other, and are generated by, for example, the drive control unit 101. In this case, the drive control unit 101 supplies the voltage-withstanding protection circuits 24 and 34 with the control signal XCTL at logic level 0 and the control signal CTL at logic level 1 for voltage-withstanding protection over a predetermined period from, for example, the power supply startup time point to the power supply startup completion time point at which the power supply potential reaches a predetermined voltage value. Then, after the power supply startup is completed, the drive control section 101 supplies the control signal XCTL of logic level 1 and the control signal CTL of logic level 0, which stop the withstand voltage protection, to the withstand voltage protection circuits 24 and 34.

Therefore, the transistors 24A and 34A are turned on only when there is a possibility that the first and second shift signals VN5 and VN6 become indefinite and the voltage difference between the gate and seed sources of the output transistors 13 and 14 becomes withstand voltage excess during a period until the bias circuits supplying the bias voltages VBN and VBP perform stable operation, such as at the time of power supply startup. Thus, the first and second shift signals VN5, VN6 quickly change from an indefinite state later at the time of power supply startup to zero in the gate/seed/source voltage difference of the output transistors 13, 14.

Therefore, according to the withstand voltage protection circuits 24 and 34, the voltage difference between the gate and the seed of the output transistors 13 and 14 is prevented from exceeding the withstand voltage at the time of unstable operation of the amplification circuit 100 (for example, at the time of power supply startup).

In the above-described embodiment, the control signals CTL and XCTL are generated by the drive control unit 101, but a circuit for generating these control signals CTL and XCTL may be provided in the data driver 103.

[ example 4]

Fig. 7 is a circuit diagram showing an internal configuration of an amplifier circuit 100 as a fourth embodiment of the present invention, which employs another internal configuration as the withstand voltage protecting circuits 24 and 34 shown in fig. 6. The configuration other than the internal configuration of each of the withstand voltage protection circuits 24 and 34 is the same as that shown in fig. 6.

In the structure shown in fig. 7, the withstand voltage protecting circuit 24 includes transistors 24B and 24C of the first conductivity type (P-channel type). In the transistor 24B, a first terminal (source) of itself is connected to the power supply terminal NE1, and a second terminal (drain) and a control terminal (gate) are both connected to a first terminal (source) of the transistor 24C. The second terminal (drain) and the control terminal (gate) of the transistor 24C are both connected to the control terminal (gate) of the output transistor 13 via a node N5. Here, the transistors 24B and 24C are constructed in an element size such that the sum of threshold voltages (absolute values) of each becomes a voltage slightly lower than the withstand voltage (Vgs maximum applied voltage) of the output transistor 13.

As such, the withstand voltage protection circuit 24 has a structure in which the transistors 24B and 24C of the first conductivity type (P-channel type) are cascade-connected between the node N5 and the power supply terminal NE1, and each of the transistors 24B and 24C is diode-connected.

The withstand voltage protecting circuit 34 includes transistors 34B and 34C of the second conductivity type (N-channel type). In the transistor 34B, a first terminal (source) thereof is connected to the power supply terminal NE2, and a second terminal (drain) and a control terminal (gate) are both connected to a first terminal (source) of the transistor 34C. The second terminal (drain) and the control terminal (gate) of the transistor 34C are both connected to the control terminal (gate) of the output transistor 14 via a node N6. Here, the transistors 34B and 34C are constructed in an element size such that the sum of threshold voltages (absolute values) of each becomes a voltage slightly lower than a withstand voltage (Vgs maximum applied voltage) of the output transistor 14.

As such, the withstand voltage protecting circuit 34 has a structure in which the transistors 34B and 34C of the first conductivity type (P-channel type) are cascade-connected between the node N6 and the power supply terminal NE2, each of the transistors 34B and 34C being diode-connected.

With such a configuration, the transistors 24B, 24C, 34B, and 34C become on when the first and second shift signals VN5 and VN6 exceed the set total of threshold voltages, respectively, and the potential variation of the first and second shift signals VN5 and VN6 is restricted. Therefore, even in the case where the first and second shift signals VN5 and VN6 may become indefinite including at the time of power supply startup and the like, it is possible to prevent the difference in the voltages between the gates and the seeds of the output transistors 13 and 14 from becoming withstand voltage excesses. The number of stages for cascade-connecting the respective diode-connected transistors in the withstand voltage protection circuits 24 and 34 is not limited to 2 stages shown in fig. 7, and may be a plurality of stages of 3 stages or more.

[ example 5]

Fig. 8 is a circuit diagram showing a differential stage 10A as an example of the differential stage 10 in the amplifier circuit 100 of fig. 1.

The differential stage 10A includes an NMOS differential pair composed of transistors 61 and 62 of the second conductivity type (N-channel type), a PMOS differential pair composed of transistors 63 and 64 of the first conductivity type (P-channel type), and current sources 65 and 66.

In the current source 65, one end thereof is connected to the power supply terminal E4 on the low potential side, and the other end is commonly connected to the respective first terminals (sources) of the transistors 61 and 62. In the current source 66, one end thereof is connected to the power supply terminal E3 on the high potential side, and the other end is commonly connected to the respective first terminals (sources) of the transistors 63 and 64.

The control terminal (gate) of each of the transistors 61 and 63, that is, one input of each of the NMOS differential pair and the PMOS differential pair is connected to the input terminal N1 as a non-inverting input (+) of the differential stage 10A. Further, the control terminal (gate) of each of the transistors 62 and 64, that is, the other input of each of the NMOS differential pair and the PMOS differential pair is connected to the output terminal N2 as the inverting input terminal (-) of the differential stage 10A.

The differential stage 10A includes transistors 41 to 44 of a first conductivity type (P-channel type) connected to the NMOS differential pair (61, 62).

In the transistors 41 and 42, a first terminal (source) of each is connected to the power supply terminal E3 on the high potential side, and control terminals (gates) are connected in common with each other. A second terminal (drain) of the transistor 41 is connected to a first terminal (source) of the transistor 43 and a second terminal (drain) of the transistor 62 forming an NMOS differential pair via a node N32. A second terminal (drain) of the transistor 42 is connected to a first terminal (source) of the transistor 44 and a second terminal (drain) of the transistor 61 forming the above-described NMOS differential pair via a node N31.

Transistors 43 and 44 receive bias voltage VB1 at the control terminal (gate) of each. A second terminal (drain) of the transistor 43 is connected to the control terminal (gate) of each of the transistors 41 and 42 and the node N35. A second terminal (drain) of the transistor 44 is connected to the first output terminal N3.

The transistors 41 to 44 constitute a first cascode gate mirror circuit. Here, the drains of the transistors 44 and 43 serve as the first terminal and the second terminal of the first cascode gate-mirror circuit, respectively.

The differential stage 10A includes second conductivity type (N-channel type) transistors 51 to 54 connected to the PMOS differential pair (63, 64).

In the transistors 51 and 52, a first terminal (source) of each is connected to the power supply terminal E4 on the low potential side, and control terminals (gates) are commonly connected to each other. A second terminal (drain) of the transistor 51 is connected to a first terminal (source) of the transistor 53 and a second terminal (drain) of the transistor 64 forming a PMOS differential pair via a node N34. A second terminal (drain) of the transistor 52 is connected to a first terminal (source) of the transistor 54 and a second terminal (drain) of the transistor 63 forming the above-described PMOS differential pair via a node N33.

Transistors 53 and 54 receive bias voltage VB2 at the control terminal (gate) of each. A second terminal (drain) of the transistor 53 is connected to the control terminal (gate) of each of the transistors 51 and 52 and the node N36. A second terminal (drain) of the transistor 54 is connected to the second output terminal N4.

The transistors 51 to 54 constitute a second cascode gate mirror circuit. Here, the drains of the transistors 54 and 53 serve as the first terminal and the second terminal of the second cascode gate-mirror circuit, respectively.

Here, the first terminals of the first and second cascode gate-mirror circuits are the first output terminal N3 and the second output terminal N4 of the differential stage 10A.

Further, the differential stage 10A includes a first parasitic current source 71 and a second parasitic current source 72.

The parasitic current source 71 is connected between the first terminal (N3) of the first cascode gate-mirror circuit and the first terminal (N4) of the second cascode gate-mirror circuit. The parasitic current source 72 is connected between the second terminal (N35) of the first cascode gate mirror circuit and the second terminal (N36) of the second cascode gate mirror circuit.

The parasitic current source 71 includes a transistor 73 of a first conductivity type (P-channel type) and a transistor 74 of a second conductivity type (N-channel type). In the transistor 73, a first terminal (source) thereof is connected to a second terminal (drain) of the transistor 44 of the first cascode current-mirror circuit, and a second terminal (drain) thereof is connected to a second terminal (drain) of the transistor 54 of the second cascode current-mirror circuit. In the transistor 74, a first terminal (source) thereof is connected to a second terminal (drain) of the transistor 54 of the second cascode current-mirror circuit, and a second terminal (drain) thereof is connected to a second terminal (drain) of the transistor 44 of the first cascode current-mirror circuit. The transistor 73 receives a bias voltage VB3 at its control terminal (gate), and the transistor 74 receives a bias voltage VB4 at its control terminal (gate).

The parasitic current source 71 causes constant currents corresponding to the bias voltages VB3 and VB4 to flow between the first terminal (N3) of the first cascode gate mirror circuit and the first terminal of the first terminal (N4) of the second cascode gate mirror circuit.

In the parasitic current source 72, one end thereof is connected to the node N35, and the other end thereof is connected to the node N36. The parasitic current source 72 causes a predetermined constant current to flow between the second terminal (N35) of the first cascode gate-mirror circuit and the second terminal (N36) of the second cascode gate-mirror circuit.

With such a configuration, in the differential stage 10A, when the input signal VI at the input terminal N1 changes with respect to the output signal VO at the output terminal N2, the potentials of the output terminal pair (N3, N4) of the differential stage 10A act in the direction opposite to the voltage change of the input signal VI.

For example, a phase compensation capacitor may be provided between the output terminal N2 of the amplifier circuit 100 in fig. 3 and at least 1 of the terminals of the differential stage 10A to stabilize the output of the amplification operation.

As described above, according to the booster circuit BST included in the amplifier circuit 100 shown in fig. 3 and 5 to 7, it is possible to quickly follow the change of the input signal VI to charge and discharge the load connected to the output terminal N2 with sufficient current driving capability. In addition, in the booster circuit BST, even if the sizes of the output transistors 13 and 14 are made small, the output response time of the amplifier circuit 100 can be appropriately shortened.

Therefore, as shown in fig. 2, by using the output unit 806 including n amplifier circuits 100, the area and cost of the data driver 103 itself can be reduced.

Further, according to the amplifier circuit 100, since the output response time can be shortened, by mounting the amplifier circuit 100 in the data driver 103, high-quality display suitable for a large screen and high resolution of a display panel can be realized at low cost.

Description of reference numerals

10 differential stage

11-14 output transistor

20 first potential control circuit

30 second potential control circuit

100 amplifying circuit

103 data driver

806 output unit

BST boost circuit.