阅读说明：本技术 时序模型、时序模型建立方法、与相关的顶层分析方法 (Time sequence model, time sequence model establishing method and related top layer analysis method ) 是由 蔡孟修 廖信雄 蔡旻修 于 2019-03-27 设计创作，主要内容包括：一种时序模型、时序模型建立方法、与相关的顶层分析方法。时序模型包含对应于门级网表的接口网表和特定内部网表。若门级网表包含未限制时脉树,且门级网表的边界时序限制信息未包含未限制时脉树的时序限制,则接口网表不包含门级网表中由未限制时脉树驱动的电路单元。特定内部网表交叉耦合至接口网表。上述的时序模型能增进顶层分析的准确度并减少分析所需时间。(A time sequence model, a time sequence model establishing method and a related top layer analysis method are provided. The timing model includes an interface netlist and a particular internal netlist corresponding to the gate level netlist. If the gate-level netlist contains the unrestricted clock tree and the boundary timing constraint information of the gate-level netlist does not contain the timing constraint of the unrestricted clock tree, then the interface netlist does not contain the circuit cells in the gate-level netlist that are driven by the unrestricted clock tree. The particular internal netlist is cross-coupled to the interface netlist. The timing model can improve the accuracy of the top layer analysis and reduce the time required by the analysis.)

1. A method for building a timing model for building a gate-level netlist corresponding to a block, the method comprising:

generating an interface netlist of the gate-level netlist by using a microprocessor, wherein if the gate-level netlist includes an unrestricted clock tree and a boundary timing limitation information of the gate-level netlist does not include a timing limitation of the unrestricted clock tree, the interface netlist does not include a circuit unit driven by the unrestricted clock tree in the gate-level netlist;

generating a specific internal netlist of the gate-level netlist using the microprocessor, wherein the specific internal netlist is cross-coupled to the interface netlist; and

and generating the timing model by the microprocessor according to the interface netlist and the specific internal netlist.

2. The method of claim 1, wherein the process of generating the interface netlist comprises:

extracting a plurality of circuit units on a first clock path from an input end of the gate-level netlist to a first register of the gate-level netlist;

extracting a plurality of circuit units on a second clock path from a second register of the gate-level netlist to an output terminal of the gate-level netlist;

extracting a plurality of circuit units on a third clock path from the input end to the output end of the gate level netlist; and

a clock tree is extracted for driving any register in the interface netlist.

3. The method of claim 2, wherein the first register is a first stage register and the second register is a last stage register.

4. The method of claim 1, wherein the transition time of the particular internal netlist is earlier than the transition time of the interface netlist.

5. The method of claim 4, wherein the process of generating the particular internal netlist of the gate level netlist comprises:

extracting an attacker netlist, wherein the attacker netlist is coupled with a first node, the first node is cross-coupled to the interface netlist, and the transition time of the first node is earlier than that of the interface netlist;

extracting a fan-in unit of the attacker netlist;

extracting a next-stage circuit unit of the attacker netlist; and

a clock tree is extracted for driving any register in the particular internal netlist.

6. The method of claim 1, further comprising:

generating annotation information, wherein the annotation information comprises an arrival time of the interface netlist and the specific internal netlist, and the arrival time is constant.

7. The method of claim 6, wherein the arrival time is annotated to an input of one of the register of the interface netlist and the specific internal netlist.

8. A method for top layer analysis, the method comprising:

dividing a circuit design into a plurality of blocks;

reading a gate-level netlist, parasitic element information and boundary timing constraint information of one of the plurality of blocks by using a microprocessor;

establishing a timing model corresponding to the gate-level netlist by using the microprocessor, wherein the timing model comprises an interface netlist and a specific internal netlist of the gate-level netlist, and the specific internal netlist is cross-coupled to the interface netlist; and

performing top-level analysis on the circuit design by using the time sequence model;

wherein if the gate-level netlist includes an unrestricted clock tree and a boundary timing constraint of the gate-level netlist does not include a timing constraint of the unrestricted clock tree, the interface netlist does not include circuit cells of the gate-level netlist driven by the unrestricted clock tree.

9. The method of claim 8, wherein the interface netlist comprises:

a plurality of circuit units located on a first clock path from an input of the gate-level netlist to a first register of the gate-level netlist;

a plurality of circuit units located on a second clock path from a second register of the gate-level netlist to an output of the gate-level netlist;

a plurality of circuit units located on a third clock path from the input end to the output end of the gate level netlist; and

a clock tree for driving any register in the interface netlist.

10. The method of claim 9, wherein the first register is a first stage register and the second register is a last stage register.

11. The method of claim 8, wherein the transition time of the particular internal netlist is earlier than the transition time of the interface netlist.

12. The method of claim 11, wherein the particular internal netlist comprises:

an attacker netlist, wherein the attacker netlist is coupled with a first node, the first node is cross-coupled to the interface netlist, and the transition time of the first node is earlier than that of the interface netlist;

a fan-in unit of the attacker netlist;

a next-stage circuit unit of the attacker netlist; and

a clock tree for driving any register in the specific internal netlist.

13. The method of claim 8, further comprising:

generating annotation information of the timing model, wherein the annotation information includes an arrival time of the interface netlist and the specific internal netlist, and the arrival time is constant.

14. The method of claim 13, wherein the arrival time is annotated to an input of one of the register of the interface netlist and the specific internal netlist.

15. A timing model, comprising:

an interface netlist corresponding to a gate-level netlist of a block, wherein if the gate-level netlist includes an unrestricted clock tree and a boundary timing constraint of the gate-level netlist does not include a timing constraint of the unrestricted clock tree, the interface netlist does not include circuit cells in the gate-level netlist that are driven by the unrestricted clock tree; and

a particular internal netlist corresponding to the gate level netlist, wherein the particular internal netlist is cross-coupled to the interface netlist.

16. The timing model of claim 15, wherein the interface netlist comprises:

a plurality of circuit units located on a first clock path from an input of the gate-level netlist to a first register of the gate-level netlist;

a plurality of circuit units located on a second clock path from a second register of the gate-level netlist to an output of the gate-level netlist;

a plurality of circuit units located on a third clock path from the input end to the output end of the gate level netlist; and

a clock tree for driving any register in the interface netlist.

17. The timing model of claim 16 wherein the first register is a first stage register and the second register is a last stage register.

18. The timing model of claim 15 wherein the transition time of the particular internal netlist is earlier than the transition time of the interface netlist.

19. The timing model of claim 18 wherein the particular internal netlist comprises:

an attacker netlist, wherein the attacker netlist is coupled with a first node, the first node is cross-coupled to the interface netlist, and the transition time of the first node is earlier than that of the interface netlist;

a fan-in unit of the attacker netlist;

a next-stage circuit unit of the attacker netlist; and

a clock tree for driving any register in the specific internal netlist.

20. The timing model of claim 15 wherein a comment is annotated to an input of one of the interface netlist and the specific internal netlist, the comment including an arrival time corresponding to the input of the one of the registers, the arrival time being constant.

Technical Field

The present disclosure relates to a timing model, a timing model building method, and a related top-level analysis method, and more particularly, to a timing model, a timing model building method, and a top-level analysis method suitable for hierarchical design.

Background

Static Timing Analysis (Static Timing Analysis) is a common approach when verifying complex circuit designs. Static timing analysis evaluates whether a timing violation occurs on each possible clock path in a circuit design. However, performing static timing analysis requires a significant amount of computational resources. Therefore, a hierarchical design method is commonly used in the art to divide a circuit design into a plurality of blocks and perform block-level (block-level) analysis to generate a simplified timing model corresponding to each block. Then, the timing model is used to perform a static timing analysis in a top-level (top-level) analysis to reduce the time and hardware resources required for the analysis. Common timing models include an extracted timing Model (ExtractTiming Model), an Interface Logic Model (Interface Logic Model), and a SuperScale Model (HyperScale Model). However, the various timing models described above have the following problems: including too many unnecessary elements, including too few necessary elements, and not fully considering signal coupling effects between elements, etc. Therefore, when performing static timing analysis with the various timing models, it still takes a considerable amount of time or accurate signal integrity (SignalIntegrity) analysis results cannot be obtained.

Disclosure of Invention

The present disclosure provides a model building method. The model building method is used for building a time sequence model corresponding to the gate-level netlist and comprises the following processes: generating an interface netlist of the gate-level netlist by using a microprocessor, wherein if the gate-level netlist comprises an unrestricted clock tree and the boundary timing limitation information of the gate-level netlist does not comprise the timing limitation of the unrestricted clock tree, the interface netlist does not comprise a circuit unit driven by the unrestricted clock tree in the gate-level netlist; generating a specific internal netlist of the gate-level netlist using a microprocessor, wherein the specific internal netlist is cross-coupled to the interface netlist; and generating a timing model according to the interface netlist and the specific internal netlist by using the microprocessor.

In some embodiments, the process of generating the interface netlist comprises: extracting a plurality of circuit units on a first clock path from an input end of the gate-level netlist to a first register of the gate-level netlist; extracting a plurality of circuit units on a second clock path from a second register of the gate-level netlist to an output terminal of the gate-level netlist; extracting a plurality of circuit units on a third clock path from the input end to the output end of the gate level netlist; and extracting a clock tree for driving any register in the interface netlist.

In some embodiments, the first register is a first stage register and the second register is a last stage register.

In some embodiments, the transition time of the particular internal netlist is earlier than the transition time of the interface netlist.

In some embodiments, the process of generating the particular internal netlist of the gate level netlist comprises: extracting an attacker netlist, wherein the attacker netlist is coupled with a first node, the first node is cross-coupled to the interface netlist, and the transition time of the first node is earlier than that of the interface netlist; extracting a fan-in unit of the attacker netlist; extracting a next-stage circuit unit of the attacker netlist; and extracting a clock tree for driving any register in the specific internal netlist.

In some embodiments, the model building method further comprises: generating annotation information, wherein the annotation information comprises an arrival time of the interface netlist and the specific internal netlist, and the arrival time is constant.

In some embodiments, the arrival time is annotated to an input of a register in the interface netlist and the particular internal netlist.

The present disclosure provides a top-level analysis method. The top layer analysis method comprises the following procedures: dividing the circuit design into a plurality of blocks; reading, by a microprocessor, a gate-level netlist, parasitic element information, and boundary timing constraint information of one of a plurality of blocks; establishing a timing model corresponding to the gate-level netlist by using a microprocessor, wherein the timing model comprises an interface netlist and a specific internal netlist of the gate-level netlist, and the specific internal netlist is cross-coupled to the interface netlist; performing top-level analysis on the circuit design by using a time sequence model; and if the gate-level netlist contains the unrestricted clock tree and the boundary timing limitation information of the gate-level netlist does not contain the timing limitation of the unrestricted clock tree, the interface netlist does not contain the circuit units driven by the unrestricted clock tree in the gate-level netlist.

In some embodiments, the interface netlist comprises: a plurality of circuit units located on a first clock path from an input of the gate-level netlist to a first register of the gate-level netlist; a plurality of circuit units located on a second clock path from a second register of the gate-level netlist to an output of the gate-level netlist; a plurality of circuit units located on a third clock path from the input end to the output end of the gate level netlist; and a clock tree for driving any register in the interface netlist.

In some embodiments, the first register is a first stage register and the second register is a last stage register.

In some embodiments, the transition time of the particular internal netlist is earlier than the transition time of the interface netlist.

In some embodiments, the particular internal netlist comprises: an attacker netlist, wherein the attacker netlist is coupled with a first node, the first node is cross-coupled to the interface netlist, and the transition time of the first node is earlier than that of the interface netlist; a fan-in unit of the attacker netlist; a next-stage circuit unit of the attacker netlist; and a clock tree for driving any register in the specific internal netlist.

In some embodiments, the top-level analysis method further comprises: generating annotation information of the timing model, wherein the annotation information includes an arrival time of the interface netlist and the specific internal netlist, and the arrival time is constant.

In some embodiments, the arrival time is annotated to an input of a register in the interface netlist and the particular internal netlist.

The present disclosure provides a timing model. The timing model includes an interface netlist corresponding to the gate level netlist and a specific internal netlist corresponding to the gate level netlist. If the gate-level netlist contains the unrestricted clock tree and the boundary timing constraint information of the gate-level netlist does not contain the timing constraint of the unrestricted clock tree, then the interface netlist does not contain the circuit cells in the gate-level netlist that are driven by the unrestricted clock tree. The particular internal netlist is cross-coupled to the interface netlist.

In some embodiments, the interface netlist comprises: a plurality of circuit units located on a first clock path from an input of the gate-level netlist to a first register of the gate-level netlist; a plurality of circuit units located on a second clock path from a second register of the gate-level netlist to an output of the gate-level netlist; a plurality of circuit units located on a third clock path from the input end to the output end of the gate level netlist; and a clock tree for driving any register in the interface netlist.

In some embodiments, the first register is a first stage register and the second register is a last stage register.

In some embodiments, the transition time of the particular internal netlist is earlier than the transition time of the interface netlist.

In some embodiments, the particular internal netlist comprises: an attacker netlist, wherein the attacker netlist is coupled with a first node, the first node is cross-coupled to the interface netlist, and the transition time of the first node is earlier than that of the interface netlist; a fan-in unit of the attacker netlist; a next-stage circuit unit of the attacker netlist; and a clock tree for driving any register in the specific internal netlist.

In some embodiments, annotation information is annotated to an input of one of the registers of the interface netlist and the particular internal netlist, the annotation information including an arrival time corresponding to the input of the one of the registers, and the arrival time being constant.

The time sequence model establishing method, the top layer analysis method and the time sequence model can improve the accuracy of the top layer analysis and reduce the time required by the analysis.

Drawings

FIG. 1 is a simplified diagram of a gate-level netlist of a block according to an embodiment of the present disclosure;

FIG. 2 is a flow chart of a method for building a timing model according to an embodiment of the present disclosure;

FIG. 3A is a simplified interface netlist corresponding to the gate level netlist of FIG. 1;

FIG. 3B is a simplified diagram of a particular internal netlist corresponding to the gate level netlist of FIG. 1;

FIG. 4 is a simplified schematic diagram of a timing model corresponding to the gate level netlist of FIG. 1;

FIG. 5 is a detailed flowchart of the process S212 according to an embodiment of the disclosure;

FIG. 6 is a flow chart of a method for timing model creation according to another embodiment of the present disclosure;

FIG. 7 is a simplified diagram of a gate level netlist of a block according to another embodiment of the present disclosure;

FIG. 8 is a simplified schematic diagram of a timing model corresponding to the gate level netlist of FIG. 7;

FIG. 9 is a flowchart of a top level analysis method according to an embodiment of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described below with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar elements or process flows.

FIG. 1 is a simplified diagram of a gate-level netlist (gate-level netlist)100 of a block according to an embodiment of the disclosure. The gate level netlist 100 describes the complete circuit design for implementing the block. The gate-level netlist 100 includes first to sixth inputs IN1 to IN6, and first to sixth outputs OUT1 to OUT 6. The gate-level netlist 100 further includes a plurality of registers 110 a-110 j, a plurality of combinational logic units 120 a-120 j, and a plurality of buffers 130 a-130 g. The third input terminal IN3 and the sixth input terminal IN6 are used for providing the first clock tree CK1 and the second clock tree CK2, respectively.

The capacitors C1 and C2 in fig. 1 are only used to represent the cross coupling (cross coupling) phenomenon between different clock paths in the gate-level netlist 100, not the actual and necessary circuit elements in the gate-level netlist 100. In addition, each of the registers 110a to 110j may be implemented by a flip-flop.

Before top-level analysis, block-level analysis may be performed on the gate-level netlist 100 to obtain a simplified timing model corresponding to the gate-level netlist 100. FIG. 2 is a flow chart of a method 200 for timing model creation according to an embodiment of the present disclosure. In the present embodiment, the timing model building method 200 is executed by a microprocessor (not shown). However, the timing model building method 200 can also be performed by an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other integrated module with data processing capability and supported by a non-volatile memory device.

In process S202, the microprocessor finds a clock path from the input of the gate-level netlist 100 to the first-level register, and extracts (extracts) circuit cells on the clock path.

In process S204, the microprocessor finds a clock path from the last register of the gate-level netlist 100 to the output, and extracts circuit cells on the clock path.

In the process S206, the microprocessor finds a clock path from the input to the output of the block, and extracts the circuit units on the clock path.

In the process S208, the microprocessor finds a clock tree for driving any of the registers determined in the processes S202-S206, and extracts the circuit units in the clock tree.

In the process S210, the microprocessor generates an interface netlist of the gate-level netlist 100 according to the circuit units extracted in the steps S202 to S208. It should be noted that the microprocessor is preloaded with boundary timing constraint information (boundary timing information) of the block. The boundary timing constraint information includes arrival time (arrival time) at the input of gate-level netlist 100 and required arrival time (required arrival time) defined by the subsequent circuit at the output of gate-level netlist 100. If the timing constraint associated with a clock tree is not recorded in the boundary timing constraint information (hereinafter referred to as "unrestricted clock tree"), the microprocessor will not extract all circuit units driven by the unrestricted clock tree when performing the timing model building method 200.

In process S212, the microprocessor finds out an aggressor signal (acquiring signal) corresponding to the interface netlist in process S210, and extracts the circuit units through which the aggressor signal flows from the gate-level netlist 100. The microprocessor then generates a specific internal netlist of the gate-level netlist 100 according to the circuit units. In other words, a particular internal netlist is cross-coupled to the interface netlist.

In process S214, the microprocessor generates a timing model of the block according to the interface netlist and the specific internal netlist.

FIG. 3A is a simplified diagram of interface netlist 310 corresponding to gate level netlist 100. According to the rules of the processes S202-S210, the register 110a is the first-level register on the clock path from the first input terminal IN1, so the interface netlist 310 includes the register 110a and the combinational logic cell 120 a. Register 110d is the first level register IN the clock path from second input IN2, so interface netlist 310 includes register 110d and logic cell 120 d. Register 110g is the last-stage register in the clock path that ends at first output OUT1, so interface netlist 310 includes register 110g and logic cell 120 g. Register 110h is the last-stage register in the clock path that ends at second output OUT2, so interface netlist 310 includes register 110h and logic cell 120 h.

Combinational logic cell 120i is located on the clock path from the fourth input IN4 to the fourth output OUT4, so that the interface netlist 310 includes the combinational logic cell 120 i. Since the first clock tree CK1 is used to drive the registers 110a, 110d, 110g, and 110h, the interface netlist 310 includes the buffers 130 c-130 e of the first clock tree CK 1. In the present embodiment, the second clock tree CK2 is an unrestricted clock tree. Therefore, the interface netlist 310 does not include the registers 110 i-110 j, combinational logic units 120 j-120 k, and buffers 130 f-130 g driven by the second clock tree CK 2.

Referring to fig. 1 and fig. 3A, the signal transition time of the first node N1 of the present embodiment is earlier than that of the second node N2 of the interface netlist 310, so that the signal flowing through the first node N1 is an attacker signal of the interface netlist 310. Therefore, according to the rule of the process S212, the microprocessor extracts the register 110B, the combinational logic unit 120c, and the buffer 130a in the same clock path as the first node N1, and extracts the buffers 130 c-130 e in the relevant clock path to form the specific internal netlist 320 as shown in FIG. 3B.

Referring back to fig. 1 and fig. 3A, since the signal transition time of the third node N3 is later than the fourth node N4 of the interface netlist 310, the signal flowing through the third node N3 is the victim signal (victim signal) of the interface netlist 310. Therefore, the specific internal netlist 320 does not include the register 110e, combinational logic cell 120e, and buffer 130b in the same clock path as the third node N3.

FIG. 4 is a simplified schematic diagram of a timing model 400 corresponding to gate-level netlist 100. Timing model 400 is generated for a processor from interface netlist 310 and a particular internal netlist 320. As can be seen from the above, the timing model 400 includes cross-coupling information within the block and does not include circuit cells driven by an unrestricted clock tree (e.g., the second clock tree CK 2). Therefore, the timing model 400 can improve the accuracy of the top-level analysis and reduce the time required for the analysis.

Fig. 5 is a detailed flow of the process S212 in an embodiment. In process S502, the microprocessor extracts the aggressor netlist of interface netlist 310, such as combinational logic circuit 120c of FIG. 3B, from gate-level netlist 100 according to the clock path of the aggressor signal of interface netlist 310.

In process S504, the microprocessor extracts the fan-in cells of the aggressor netlist, such as register 110B of FIG. 3B, from the gate-level netlist 100. The arrival time and the transition time of the fan-in unit are annotated to the input end of the fan-in unit. In this way, the characteristics of the signal flowing through the aggressor netlist can be accurately represented during the top-level analysis.

In flow S506, the microprocessor extracts the next circuit unit of the aggressor netlist, such as buffer 130a of FIG. 3B, from the gate-level netlist 100.

Next, the microprocessor executes the process S508 to find a clock tree for driving any of the extracted registers in the processes S502-S506 from the gate-level netlist 100. Then, the microprocessor extracts the circuit units on the clock tree. As shown in FIG. 3B, the first clock tree CK1 is used to drive the register 110B, so the microprocessor will extract the buffers 130 c-130 e.

In the process S510, the microprocessor builds a specific internal netlist according to the extracted circuit units in the processes S502-S508. Such as the particular internal netlist 320 shown in fig. 3B.

FIG. 6 is a flowchart of a method 600 for timing model building according to an embodiment of the present disclosure. The processes S202 to S212 of the time sequence model establishing method 600 are similar to the corresponding processes of the time sequence model establishing method 200, and are not repeated herein for brevity. In process S614, the microprocessor finds a clock path with fixed transmission characteristics connected to the interface netlist and the specific internal netlist. The fixed transmission characteristics represent that the arrival time and transition time of the signal are not changed by the circuit operation in the gate-level netlist when the signal is transmitted on the clock path.

Next, in the process S616, the microprocessor generates annotation information of the clock path with fixed transmission characteristics, and annotates the annotation information to the input end of the corresponding register in the interface netlist and the specific internal netlist. Furthermore, the microprocessor does not extract the circuit units on the clock path with fixed transmission characteristics.

Next, in flow S618, the microprocessor generates a timing model corresponding to the gate-level netlist according to the interface netlist and the specific internal netlist containing the annotation information.

FIG. 7 is a simplified diagram of a gate-level netlist 700 for a block according to an embodiment of the present disclosure. Gate-level netlist 700 includes a third clock tree CK3 with fixed transmission characteristics. FIG. 8 is a simplified schematic diagram of a timing model 800 corresponding to a gate-level netlist 700. According to the rule of the process S618, since the inputs of the registers 710a and 710e are connected to the third clock tree CK3, the microprocessor generates the annotation information AN corresponding to the third clock tree CK3 and annotates the annotation information AN at the inputs of the registers 710a and 710 e. Moreover, the microprocessor does not extract the circuit units (e.g., the buffers 720 a-720 e) in the third clock tree CK 3. Therefore, the number of elements can be further reduced without affecting the accuracy of the top layer analysis.

In one embodiment, the annotation information annotated to the inputs of registers 710a and 710e includes arrival time and transition time expressed as constants.

In summary, the timing model building methods 200 and 600 can not only build a simple timing model without sacrificing the accuracy of the static timing analysis, but also consider the signal coupling relationship between the clock paths to further improve the accuracy of the static timing analysis. Therefore, the timing model building methods 200 and 600 can greatly save hardware resources and time required by static timing analysis, and are suitable for complex integrated circuit design.

FIG. 9 is a flow chart of a top level analysis method 900 according to an embodiment of the present disclosure. The top-level analysis method 900 is suitable for hierarchical integrated circuit designs and can be performed by a microprocessor. However, the top-level analysis method 900 may also be performed by an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other integrated module with data processing capabilities and supported by a non-volatile memory device.

In flow S902, the microprocessor divides the circuit design into a plurality of blocks. In flow S904, the microprocessor reads the block netlist, parasitic element information, and boundary timing constraint information of one of the blocks. The parasitic element information may be used to determine cross-coupling between different clock paths in the block.

In the process S906, the microprocessor builds a timing model corresponding to the block. The process S906 can be implemented by the aforementioned timing model building method 200 or 600. Next, the microprocessor executes a process S908 to perform a top-level analysis of the circuit design according to the generated timing model.

The execution sequence of the processes in the above flowcharts is only an exemplary embodiment, and is not limited to the actual implementation of the present invention. For example, in the above flowcharts, the processes S202 to S206 may be performed simultaneously, and the processes S502 to S506 may be performed simultaneously.

Certain terms are used throughout the description and following claims to refer to particular components. However, those of ordinary skill in the art will appreciate that the various elements may be referred to by different names. The specification and claims do not intend to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Further, "coupled" herein includes any direct and indirect connection. Therefore, if a first element is coupled to a second element, the first element may be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or may be indirectly connected to the second element through another element or a connection means.

In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.

It should be understood, however, that there is no intent to limit the disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the appended claims.