阅读说明：本技术 垂直双扩散金属氧化物半导体场效应管及制备方法 (Vertical double-diffusion metal oxide semiconductor field effect transistor and preparation method thereof ) 是由 刘雯娇 杨世红 于 2021-09-13 设计创作，主要内容包括：本发明公开了一种垂直双扩散金属氧化物半导体场效应管及制备方法,管中,N型埋层层叠于P型衬底的上表面,N型埋层内注入有N型离子,N型外延层层叠于N型埋层的上表面,N型外延层内设有注入P型离子的P阱,P阱包括背栅P区和分压隔离环P区,背栅P区内分别形成有N+接触区,N+接触区注入有N型离子,栅氧化层层叠于N型外延层的上表面,栅氧化层上形成有多晶硅栅极,中间介质层层叠于栅氧化层及多晶硅栅极上,D端接触孔依次穿通中间介质层、栅氧化层、N型外延层及N型埋层,S端接触孔依次穿通中间介质层、栅氧化层及N+接触区,G端接触孔依次穿通中间介质层与多晶硅栅极。(The invention discloses a vertical double-diffusion metal oxide semiconductor field effect transistor and a preparation method thereof, wherein in the transistor, the N-type buried layer is stacked on the upper surface of the P-type substrate, N-type ions are injected into the N-type buried layer, the N-type epitaxial layer is stacked on the upper surface of the N-type buried layer, a P trap into which the P-type ions are injected is arranged in the N-type epitaxial layer, the P trap comprises a back gate P region and a partial pressure isolating ring P region, N + contact regions are formed in the back gate P region respectively, the N-type ions are injected into the N + contact regions, a gate oxide layer is stacked on the upper surface of the N-type epitaxial layer, a polycrystalline silicon gate is formed on the gate oxide layer, an intermediate medium layer is stacked on the gate oxide layer and the polycrystalline silicon gate, a D-end contact hole sequentially penetrates through the intermediate medium layer, the gate oxide layer, the N-type epitaxial layer and the N-type buried layer, an S-end contact hole sequentially penetrates through the intermediate medium layer, the gate oxide layer and the N + contact region, and a G-end contact hole sequentially penetrates through the intermediate medium layer and the polycrystalline silicon gate.)

1. A vertical double diffused metal oxide semiconductor field effect transistor (VDMOS) comprising:

a P-type substrate,

an N-type buried layer stacked on the upper surface of the P-type substrate, N-type ions implanted in the N-type buried layer,

the N-type epitaxial layer is laminated on the upper surface of the N-type buried layer, a P well for injecting P-type ions is arranged in the N-type epitaxial layer, the P well comprises a back gate P region and a partial pressure isolating ring P region, N + contact regions are respectively formed in the back gate P region, and the N-type ions are injected into the N + contact regions,

a gate oxide layer laminated on the upper surface of the N-type epitaxial layer, wherein a polysilicon gate is formed on the gate oxide layer,

an intermediate dielectric layer stacked on the gate oxide layer and the polysilicon gate,

a D-end contact hole which sequentially penetrates through the intermediate dielectric layer, the gate oxide layer, the N-type epitaxial layer and the N-type buried layer,

an S-terminal contact hole sequentially passing through the intermediate dielectric layer, the gate oxide layer and the N + contact region,

and the G end contact hole sequentially penetrates through the intermediate dielectric layer and the polysilicon gate.

2. The vertical double diffused metal oxide semiconductor field effect transistor according to claim 1 wherein the D, S and G terminal contact holes are filled with a filler.

3. The vertical double diffused metal oxide semiconductor field effect transistor as claimed in claim 2 wherein the filler comprises Ti, TiN and tungsten metal.

4. The vertical double diffused metal oxide semiconductor field effect transistor according to claim 1 wherein there is at least one of the back gate P region and the voltage divider spacer P region, at least one of the D-terminal contact hole and the S-terminal contact hole, and at least one of the G-terminal contact holes.

5. The vertical double diffused metal oxide semiconductor field effect transistor according to claim 1 wherein the D-side contact hole is a trench-type contact hole.

6. A method for preparing the vertical double-diffused metal oxide semiconductor field effect transistor as claimed in any one of claims 1 to 5, which comprises the following steps:

step S1, selecting a P-type substrate with a crystal orientation of <100>, coating photoresist on the upper surface of the P-type substrate, limiting an NBL region of an N-type buried layer on the photoresist by adopting a photomask or a photoetching plate of the N-type buried layer, forming the NBL region through exposure and development, and performing N-type ion implantation in the NBL region to form the N-type buried layer region;

s2, performing high-temperature furnace tube junction pushing at 1000-1150 ℃ on the N-type buried layer region to form an N-type buried layer, and growing an N-type epitaxial layer of 5-6 microns on the upper surface of the N-type buried layer by adopting a vapor phase epitaxy process;

s3, growing a gate oxide layer of 500-600 angstroms on the upper surface of the N-type epitaxial layer by adopting a dry-wet-dry oxidation process, and depositing polycrystalline silicon by adopting a low-pressure chemical vapor deposition process so as to deposit a polycrystalline silicon layer of 3500-4500 angstroms on the gate oxide layer;

step S4, coating a photoresist on the polysilicon layer, defining a P-well ion implantation region on the photoresist by using a photomask or a reticle of a P-well, and simultaneously forming the P-well ion implantation region including a back gate P region and a partial pressure isolation ring P region by exposure and development;

s5, removing polycrystalline silicon in an ion implantation area of the P well by using dry etching, performing ion implantation on the P well, wherein the implantation bevel angle is 35-45 degrees, removing residual photoresist on the polycrystalline silicon layer by using mixed liquid of concentrated sulfuric acid and hydrogen peroxide to form the P well, and the P well comprises a back gate P area and a partial pressure isolation ring P area;

step S6, coating photoresist on the polysilicon layer and the P well, limiting a gate region on the photoresist by adopting a gate photomask or a photoetching plate, and forming the gate region by exposure and development;

step S7, removing the polysilicon outside the gate region by using a dry etching process, and removing the photoresist on the gate region by using a mixed solution of concentrated sulfuric acid and hydrogen peroxide to form a polysilicon gate;

step S8, coating photoresist on the polysilicon gate and the gate oxide layer, limiting an N + region on the photoresist by adopting an N + photomask or a photoetching plate, and forming an N + region in a back gate P region through exposure and development;

step S9, performing N + injection in the N + region to form an N + contact region, removing photoresist on the polysilicon gate and the gate oxide layer by using mixed solution of concentrated sulfuric acid and hydrogen peroxide, and forming an intermediate dielectric layer on the polysilicon gate and the gate oxide layer by a chemical vapor deposition process;

step S10, coating photoresist on the intermediate medium layer, limiting a D-end contact hole area on the photoresist by using a photomask or a photoetching plate of the D-end contact hole, and forming the D-end contact hole area through exposure and development;

step S11, forming a D-end contact hole in the D-end contact hole area by dry etching, wherein the D-end contact hole is of a trench structure, the trench is communicated with the N-type buried layer, a layer of Ti and TiN metal is sequentially deposited as a barrier layer by adopting a metal organic compound chemical vapor deposition process, and then the D-end contact hole is filled with metal tungsten by adopting a chemical vapor deposition process;

step S12, coating photoresist on the intermediate medium layer and the D-end contact hole, defining a G-end contact hole area and an S-end contact hole area on the photoresist by using a photomask or a photoetching plate of the contact hole, forming the G-end contact hole area and the S-end contact hole area by exposure and development, forming the G-end contact hole and the S-end contact hole by using dry etching on the G-end contact hole area and the S-end contact hole area, sequentially depositing a layer of Ti and TiN metal as a barrier layer by using a metal organic compound chemical vapor deposition process, and depositing metal tungsten by using a chemical vapor deposition process to fill the G-end contact hole and the S-end contact hole.

7. A production method according to claim 6,

the implantation ions of the N-type buried layer are arsenic or antimony, the implantation energy is 80-100 KeV, and the implantation dosage is 8E 15-9.5E 15cm^-2。

8. A production method according to claim 6,

the P-well implanted ions are boron ions and four times of rotation implantation is adopted, the implantation energy is 40-55 KeV, and the implantation dosage is 2.5E 13-3E 13cm^-2。

9. A production method according to claim 6,

the implanted ions in the N + contact region are As, the implantation energy is 70-80 KeV, and the implantation dose is 7.5E 15-8E 15cm^-2。

10. A production method according to claim 6,

the middle dielectric layer comprises undoped silicon glass and silicon glass containing boron and phosphorus, and the undoped silicon glass and the silicon glass containing boron and phosphorus are both formed by adopting a chemical vapor deposition process, wherein the thickness of the deposited undoped silicon glass is 1500-2000 angstroms, and the thickness of the deposited silicon glass containing boron and phosphorus is 7000-8000 angstroms.

Technical Field

The invention relates to the technical field of monolithic integration processes, in particular to a vertical double-diffusion metal oxide semiconductor field effect transistor and a preparation method thereof.

Background

The BCD (BIPOLAR-CMOS-DMOS) integration process is a single-chip integration process technology, and BIPOLAR transistors, CMOS (complementary metal oxide semiconductor field effect transistors) and DMOSFET (double-diffused metal oxide semiconductor field effect transistors) devices are simultaneously manufactured on the same chip. It combines the advantages of each, and has good performance when each is standing. The integrated BCD process can greatly reduce power consumption, improve system performance, save cost and have better reliability. Wherein, the DMOSFET device is composed of hundreds of single structure DMOSFET cells. The number of these cells is determined by the driving capability required by a chip, and the performance of DMOSFET directly determines the driving capability and chip area of the chip. The main technical indicators of DMOSFETs are: withstand voltage, on-resistance, threshold voltage, and the like.

There are two main types of DMOSFETs: a lateral double-diffused metal oxide semiconductor field effect transistor LDMOSFET and a vertical double-diffused metal oxide semiconductor field effect transistor VDMOSFET. The high-voltage device in the BCD is usually an LDMOSFET, but when the LDMOSFET needs to reach a high withstand voltage, a drift region (the impurity concentration of the drift region is low) needs to be designed in the structure, so that the drain region occupies a large area, and the on-resistance of the device is increased. The VDMOSFET has very high withstand voltage, but due to the vertical structure, the drain terminal is led out from the back surface, so that the VDMOSFET is not suitable for being combined with a BCD (bulk-coded decimal) integration process with a planar structure, and the VDMOSFET has poor compatibility.

The above information disclosed in this background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is well known to those of ordinary skill in the art.

Disclosure of Invention

The invention aims to provide a vertical double-diffusion metal oxide semiconductor field effect transistor and a preparation method thereof, which overcome the defects that a drain terminal area occupies a large area, the on-resistance is increased, a BCD (bipolar complementary metal oxide semiconductor) integration process compatible with a planar structure is compatible, and the withstand voltage is high.

In order to achieve the above purpose, the invention provides the following technical scheme:

the vertical double-diffused metal oxide semiconductor field effect transistor of the invention comprises,

a P-type substrate,

an N-type buried layer stacked on the upper surface of the P-type substrate, N-type ions implanted in the N-type buried layer,

the N-type epitaxial layer is laminated on the upper surface of the N-type buried layer, a P well for injecting P-type ions is arranged in the N-type epitaxial layer, the P well comprises a back gate P region and a partial pressure isolating ring P region, N + contact regions are respectively formed in the back gate P region, and the N-type ions are injected into the N + contact regions,

a gate oxide layer laminated on the upper surface of the N-type epitaxial layer, wherein a polysilicon gate is formed on the gate oxide layer,

an intermediate dielectric layer stacked on the gate oxide layer and the polysilicon gate,

a D-end contact hole which sequentially penetrates through the intermediate dielectric layer, the gate oxide layer, the N-type epitaxial layer and the N-type buried layer,

an S-terminal contact hole sequentially passing through the intermediate dielectric layer, the gate oxide layer and the N + contact region,

and the G end contact hole sequentially penetrates through the intermediate dielectric layer and the polysilicon gate.

In the vertical double-diffused metal oxide semiconductor field effect transistor, the D-end contact hole, the S-end contact hole and the G-end contact hole are filled with fillers.

In the vertical double-diffused metal oxide semiconductor field effect transistor, the filler comprises Ti, TiN and metal tungsten.

In the vertical double-diffused metal oxide semiconductor field effect transistor, at least one back gate P region and at least one voltage division isolation ring P region are provided, at least one D-end contact hole and at least one S-end contact hole are provided, and at least one G-end contact hole is provided.

In the vertical double-diffused metal oxide semiconductor field effect transistor, the D-end contact hole is a groove-shaped contact hole.

The preparation method of the vertical double-diffusion metal oxide semiconductor field effect transistor comprises the following steps,

step S1, selecting a P-type substrate with a crystal orientation of <100>, coating photoresist on the upper surface of the P-type substrate, limiting an NBL region of an N-type buried layer on the photoresist by adopting a photomask or a photoetching plate of the N-type buried layer, forming the NBL region through exposure and development, and performing N-type ion implantation in the NBL region to form the N-type buried layer region;

s2, performing high-temperature furnace tube junction pushing at 1000-1150 ℃ on the N-type buried layer region to form an N-type buried layer, and growing an N-type epitaxial layer of 5-6 microns on the upper surface of the N-type buried layer by adopting a vapor phase epitaxy process;

s3, growing a gate oxide layer of 500-600 angstroms on the upper surface of the N-type epitaxial layer by adopting a dry-wet-dry oxidation process, and depositing polycrystalline silicon by adopting a low-pressure chemical vapor deposition process so as to deposit a polycrystalline silicon layer of 3500-4500 angstroms on the gate oxide layer;

step S4, coating a photoresist on the polysilicon layer, defining a P-well ion implantation region on the photoresist by using a photomask or a reticle of a P-well, and simultaneously forming the P-well ion implantation region including a back gate P region and a partial pressure isolation ring P region by exposure and development;

s5, removing polycrystalline silicon in an ion implantation area of the P well by using dry etching, performing ion implantation on the P well, wherein the implantation bevel angle is 35-45 degrees, removing residual photoresist on the polycrystalline silicon layer by using mixed liquid of concentrated sulfuric acid and hydrogen peroxide to form the P well, and the P well comprises a back gate P area and a partial pressure isolation ring P area;

step S6, coating photoresist on the polysilicon layer and the P well, limiting a gate region on the photoresist by adopting a gate photomask or a photoetching plate, and forming the gate region by exposure and development;

step S7, removing the polysilicon outside the gate region by using a dry etching process, and removing the photoresist on the gate region by using a mixed solution of concentrated sulfuric acid and hydrogen peroxide to form a polysilicon gate;

step S8, coating photoresist on the polysilicon gate and the gate oxide layer, limiting an N + region on the photoresist by adopting an N + photomask or a photoetching plate, and forming an N + region in a back gate P region through exposure and development;

step S9, performing N + injection in the N + region to form an N + contact region, removing photoresist on the polysilicon gate and the gate oxide layer by using mixed solution of concentrated sulfuric acid and hydrogen peroxide, and forming an intermediate dielectric layer on the polysilicon gate and the gate oxide layer by a chemical vapor deposition process;

step S10, coating photoresist on the intermediate medium layer, limiting a D-end contact hole area on the photoresist by using a photomask or a photoetching plate of the D-end contact hole, and forming the D-end contact hole area through exposure and development;

step S11, forming a D-end contact hole in the D-end contact hole area by dry etching, wherein the D-end contact hole is of a trench structure, the trench is communicated with the N-type buried layer, a layer of Ti and TiN metal is sequentially deposited as a barrier layer by adopting a metal organic compound chemical vapor deposition process, and then the D-end contact hole is filled with metal tungsten by adopting a chemical vapor deposition process;

step S12, coating photoresist on the intermediate medium layer and the D-end contact hole, defining a G-end contact hole area and an S-end contact hole area on the photoresist by using a photomask or a photoetching plate of the contact hole, forming the G-end contact hole area and the S-end contact hole area by exposure and development, forming the G-end contact hole and the S-end contact hole by using dry etching on the G-end contact hole area and the S-end contact hole area, sequentially depositing a layer of Ti and TiN metal as a barrier layer by using a metal organic compound chemical vapor deposition process, and depositing metal tungsten by using a chemical vapor deposition process to fill the G-end contact hole and the S-end contact hole.

In the preparation method, implanted ions of the N-type buried layer are arsenic or antimony, the implantation energy is 80-100 KeV, and the implantation dosage is 8E 15-9.5E 15cm^-2。

In the preparation method, the P-well implanted ions are boron ions and four times of rotation implantation is adopted, the implantation energy is 40-55 KeV, and the implantation dosage is 2.5E 13-3E 13cm^-2。

In the preparation method, the implanted ions of the N + contact region are As, the implantation energy is 70-80 KeV, and the implantation dosage is 7.5E 15-8E 15cm^-2。

In the preparation method, the intermediate dielectric layer comprises undoped silicon glass and silicon glass containing boron and phosphorus, and the undoped silicon glass and the silicon glass containing boron and phosphorus are both formed by adopting a chemical vapor deposition process, wherein the thickness of the deposited undoped silicon glass is 1500-2000 angstroms, and the thickness of the deposited silicon glass containing boron and phosphorus is 7000-8000 angstroms.

In the above technical solution, the vertical double-diffused metal oxide semiconductor field effect transistor and the preparation method provided by the present invention have the following beneficial effects: the VDMOSFET and the traditional BCD integrated process are compatible, the drain terminal is an N-type buried layer in the BCD process, and the drain terminal is led out from the front side through a groove-type contact hole. Under the same withstand voltage, the structure can not only reduce the area of the chip and improve the utilization rate of the chip, but also reduce the on-resistance. In addition, the process of the structure needs to add a groove process to realize the drain terminal contact hole, the process is relatively simple, and the difficulty of the process cannot be increased.

Drawings

In order to more clearly illustrate the embodiments of the present application or technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present invention, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1 is a schematic diagram of a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a method for fabricating a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 3(A) is a schematic structural diagram of a method for fabricating a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 3(B) is a schematic structural diagram of a method for fabricating a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a method for fabricating a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 5 is a schematic structural diagram of a method for fabricating a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a method for fabricating a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a method for fabricating a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 8(A) is a schematic structural diagram of a vertical double diffused metal oxide semiconductor field effect transistor fabrication method according to an embodiment of the present invention;

FIG. 8(B) is a schematic structural diagram of a vertical double diffused metal oxide semiconductor field effect transistor fabrication method according to an embodiment of the present invention;

FIG. 8(C) is a schematic structural diagram of a method for fabricating a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a method for fabricating a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 10(A) is a schematic structural diagram of a vertical double diffused metal oxide semiconductor field effect transistor fabrication method according to an embodiment of the present invention;

FIG. 10(B) is a schematic structural diagram of a method for fabricating a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 11 is a schematic structural diagram of a method for fabricating a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 12(A) is a schematic structural diagram of a vertical double diffused metal oxide semiconductor field effect transistor fabrication method according to an embodiment of the present invention;

FIG. 12(B) is a schematic structural diagram of a vertical double diffused metal oxide semiconductor field effect transistor fabrication method according to an embodiment of the present invention;

FIG. 12(C) is a schematic structural diagram of a method for fabricating a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 13 is a schematic structural diagram of a method for fabricating a vertical double diffused metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

FIG. 14(A) is a schematic structural diagram of a vertical double diffused metal oxide semiconductor field effect transistor fabrication method according to an embodiment of the present invention;

FIG. 14(B) is a schematic structural diagram of a vertical double diffused metal oxide semiconductor field effect transistor fabrication method according to an embodiment of the present invention;

FIG. 15 is a schematic structural diagram of a vertical double diffused metal oxide semiconductor field effect transistor fabrication method according to an embodiment of the present invention;

FIG. 16(A) is a schematic structural diagram of a vertical double diffused metal oxide semiconductor field effect transistor fabrication method according to an embodiment of the present invention;

FIG. 16(B) is a schematic structural diagram of a vertical double diffused metal oxide semiconductor field effect transistor fabrication method according to an embodiment of the present invention;

fig. 17 is a schematic structural diagram of a method for manufacturing a vertical double diffused mosfet according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be described in detail and completely with reference to fig. 1 to 17 of the drawings of the embodiments of the present invention, and it is apparent that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the equipment or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

In order to make the technical solutions of the present invention better understood, those skilled in the art will now describe the present invention in further detail with reference to the accompanying drawings.

In one embodiment, as shown in fig. 1, a vertical double diffused metal oxide semiconductor field effect transistor includes,

a P-type substrate 1 having a high refractive index,

an N-type buried layer 4 laminated on the upper surface of the P-type substrate 1, the N-type buried layer 4 being implanted with N-type ions,

an N-type epitaxial layer 5 stacked on the upper surface of the N-type buried layer 4, a P-well for injecting P-type ions is arranged in the N-type epitaxial layer 5, the P-well comprises a back gate P region 8 and a partial pressure isolation ring P region 9, N + contact regions 10 are respectively formed in the back gate P region 8, N-type ions are injected into the N + contact regions 10,

a gate oxide layer 6 laminated on the upper surface of the N-type epitaxial layer 5, the gate oxide layer 6 having a polysilicon gate 7 formed thereon,

an intermediate dielectric layer 11 laminated on the gate oxide layer 6 and the polysilicon gate 7,

a D-end contact hole 12 which sequentially penetrates through the intermediate medium layer 11, the gate oxide layer 6, the N-type epitaxial layer 5 and the N-type buried layer 4,

an S-terminal contact hole 14 which penetrates the intermediate dielectric layer 11, the gate oxide layer 6 and the N + contact region 10 in sequence,

and the G-terminal contact hole 13 sequentially penetrates through the intermediate dielectric layer 11 and the polysilicon gate 7.

In the preferred embodiment of the vertical double-diffused mosfet, the D-terminal contact hole 12, the S-terminal contact hole 14 and the G-terminal contact hole 13 are filled with a filler.

In a preferred embodiment of the vertical double diffused mosfet, the filler comprises Ti, TiN and metal tungsten.

In the preferred embodiment of the vertical double-diffused metal oxide semiconductor field effect transistor, at least one of the back gate P region 8 and the voltage dividing isolation ring P region 9 is provided, at least one of the D-terminal contact hole 12 and the S-terminal contact hole 14 is provided, and at least one of the G-terminal contact hole 13 is provided.

In the preferred embodiment of the vertical double-diffused mosfet, the D-contact hole 12 is a trench-type contact hole.

In the preferred embodiment of the vertical double-diffused mosfet, the N-type buried layer 4 is a drain terminal, and is led out from the upper surface of the N-type buried layer 4 through the D-terminal contact hole 12.

The isolation region can be a local field oxygen isolation LOCOS (local oxidation of silicon) compatible with a CMOS (complementary metal oxide semiconductor) device in a BCD (bipolar complementary metal oxide semiconductor) device, and can also be a voltage division ring isolation of P-type ion injection compatible with a DMOSFET device. In one embodiment, the P-type grading ring isolation isolates other devices.

In one embodiment, as shown in fig. 1, in a vertical DMOSFET, taking two parallel NMOS (N-type metal oxide semiconductor field effect transistors) structures as an example, the vertical DMOSFET includes a P-type substrate 1, an N-type buried layer 4, an N-type epitaxial layer 5 and a gate oxide layer 6 are sequentially formed on the P-type substrate 1, and N-type ions are implanted into the N-type buried layer 4; a P well is formed in the N-type epitaxial layer 5 and comprises two back gate P regions 8 and two partial pressure isolation ring P regions 9, and P-type ions are injected into the P well; a polysilicon gate 7 is formed on the gate oxide layer 6, N + contact regions 10 are respectively formed in the two back gate P regions 8, and N-type ions are injected into the N + contact regions 10; an intermediate dielectric layer 11 is formed on the gate oxide layer 6 and the polysilicon gate 7; two D-end contact holes 12 penetrate through the intermediate medium layer 11, the gate oxide layer 6, the N-type epitaxial layer 5 and the N-type buried layer 4; the two D-end contact holes 12 are filled with fillers (Ti, TiN and metal tungsten), and the two S-end contact holes 14 penetrate through the gate oxide layer 6, the middle dielectric layer 11 and the N + contact area 10; the G-terminal contact hole 13 penetrates through the intermediate dielectric layer 11 and the polysilicon gate 7, and the G-terminal contact hole 13 and the two S-terminal contact holes 14 are filled with fillers (Ti, TiN and metal tungsten).

As shown in fig. 2 to 17, a method for manufacturing the vertical double diffused metal oxide semiconductor field effect transistor, taking two parallel NMOS (N-type metal oxide semiconductor field effect transistors) structures as an example, includes the following steps:

step S1, selecting a P-type substrate 1 with a crystal orientation of <100>, coating photoresist on the upper surface of the P-type substrate 1, limiting an NBL region of an N-type buried layer 4 on the photoresist by adopting a photomask or a photoetching plate of the N-type buried layer 4, forming the NBL region through exposure and development, and performing N-type ion implantation in the NBL region to form the N-type buried layer region;

step S2, performing high-temperature furnace tube push junction at 1000-1150 ℃ on the N-type buried layer region to form an N-type buried layer 4, and growing an N-type epitaxial layer 5 with the thickness of 5-6 microns on the upper surface of the N-type buried layer 4 by adopting a vapor phase epitaxy process;

step S3, growing a gate oxide layer 6 of 500-600 angstroms on the upper surface of the N-type epitaxial layer 5 by adopting a dry-wet-dry oxidation process, depositing polycrystalline silicon by adopting a low-pressure chemical vapor deposition process, and depositing a polycrystalline silicon layer 7A of 3500-4500 angstroms on the gate oxide layer 6;

step S4, coating a photoresist on the polysilicon layer 7A, defining a P-well ion implantation region on the photoresist by using a photomask or a reticle of a P-well, and simultaneously forming a P-well ion implantation region including a back gate P region 8 and a partial pressure isolation ring P region 9 by exposure and development;

step S5, removing polycrystalline silicon in an ion implantation area of the P well by using dry etching, performing ion implantation on the P well, wherein the implantation bevel angle is 35-45 degrees, removing residual photoresist on the polycrystalline silicon layer 7A by using mixed liquid of concentrated sulfuric acid and hydrogen peroxide to form the P well, and the P well comprises two back gate P areas 8 and two partial pressure isolation ring P areas 9;

step S6, coating photoresist on the polysilicon layer 7A and the P-well, defining a gate region on the photoresist by a gate mask or a photolithography mask, and forming the gate region by exposure and development;

step S7, removing the polysilicon outside the gate region by using a dry etching process, and removing the photoresist on the gate region by using a mixed solution of concentrated sulfuric acid and hydrogen peroxide to form a polysilicon gate 7;

step S8, coating photoresist on the polysilicon gate 7 and the gate oxide layer 6, defining an N + region on the photoresist by using an N + photomask or a photolithography mask, and forming an N + region in the back gate P region 8 by exposure and development;

step S9, performing N + injection in the N + region to form an N + contact region 10, removing photoresist on the polycrystalline silicon grid 7 and the gate oxide layer 6 by using a mixed solution of concentrated sulfuric acid and hydrogen peroxide, and forming an intermediate medium layer 11 on the polycrystalline silicon grid 7 and the gate oxide layer 6 by a chemical vapor deposition process;

step S10, coating photoresist on the intermediate medium layer 11, limiting a D-end contact hole area on the photoresist by using a photomask or a photoetching plate of the D-end contact hole 12, and forming the D-end contact hole area through exposure and development;

step S11, forming two D-end contact holes 12 in the D-end contact hole area by dry etching, wherein the D-end contact holes 12 are of a trench structure, the trench is communicated with the N-type buried layer 4, a layer of Ti and TiN metal is sequentially deposited by adopting a metal organic compound chemical vapor deposition process to serve as a barrier layer, and then a chemical vapor deposition process is used for depositing metal tungsten to fill the D-end contact holes 12;

step S12, photoresist is coated on the intermediate dielectric layer 11 and the D-end contact hole 12, a G-end contact hole 13 area and an S-end contact hole 14 area are limited on the photoresist by adopting a photomask or a photoetching plate of the contact hole, the G-end contact hole area and the S-end contact hole area are formed by exposure and development, the G-end contact hole 13 and the S-end contact hole 14 are formed by dry etching in the G-end contact hole area and the S-end contact hole area, a layer of Ti and TiN metal is sequentially deposited by adopting a metal organic compound chemical vapor deposition process to serve as a barrier layer, and then metal tungsten is deposited by adopting a chemical vapor deposition process to fill the G-end contact hole 13 and the S-end contact hole 14.

In a preferred embodiment of the method, the implanted ions of the N-type buried layer 4 are arsenic or antimony, the implantation energy is 80-100 KeV, and the implantation dose is 8E 15-9.5E 15cm^-2。

In a preferred embodiment of the preparation method, the P-well implanted ions are boron ions and four times of rotation implantation is adopted, the implantation energy is 40-55 KeV, and the implantation dose is 2.5E 13-3E 13cm^-2。

In a preferred embodiment of the one manufacturing method, the implanted ions of the N + contact region 10 are As, and the implantation energy is 7080KeV, the injection dosage is 7.5E 15-8E 15cm^-2。

In a preferred embodiment of the preparation method, the intermediate dielectric layer 11 comprises undoped silicate glass and silicate glass containing boron and phosphorus, both of which are formed by adopting a chemical vapor deposition process, wherein the thickness of the deposited undoped silicate glass is 1500-2000 angstroms, and the thickness of the deposited silicate glass containing boron and phosphorus is 7000-8000 angstroms.

In one embodiment, the method for preparing the vertical double-diffused metal oxide semiconductor field effect transistor DMOSFET comprises the following steps:

as shown in fig. 2, a P-type substrate 1 with a crystal orientation of <100> is selected;

fig. 3(a) and 3(B) respectively illustrate an N-type buried layer lithography process and an N-type buried layer ion implantation process; wherein the content of the first and second substances,

as shown in fig. 3(a), a photoresist 2 is coated on a P-type substrate 1, an NBL region of an N-type buried layer is defined on the photoresist 2 using a photomask (or reticle) 3 of the N-type buried layer, and the NBL region of the N-type buried layer is formed by exposure and development;

as shown in FIG. 3B, N-type ion implantation is performed to form an N-type buried layer region, wherein the implanted ions are arsenic or antimony, the implantation energy is 80-100 KeV, and the implantation dose is 8E 15-9.5E 15cm^-2；

As shown in fig. 4, performing a high temperature furnace tube push junction at 1000-1150 ℃ on the N-type buried layer region to form an N-type buried layer (NBL) 4; this enables the invention to be compatible with BCD integration processes;

as shown in fig. 5, a vapor phase epitaxy process is adopted on the upper surface of the N-type buried layer 4 to grow an N-type epitaxial layer (N-EPI) 5 of 5-6 um;

as shown in fig. 6, a gate oxide layer 6 with a thickness of 500-600 angstroms is grown on the N-type epitaxial layer 5 by adopting a dry-wet-dry oxidation process;

as shown in fig. 7, depositing polysilicon by LPCVD (low pressure chemical vapor deposition), depositing a polysilicon layer 7A of 3500 to 4500 angstroms on the gate oxide layer 6;

as shown in fig. 8(a), a photoresist 2 is coated on a polysilicon layer 7A, a P-well ion implantation region is defined on the photoresist 2 by using a photomask (or photolithography mask) 3 of a P-well, the P-well ion implantation region is formed by exposure and development, the P-well includes a back gate P region and a partial pressure isolation ring P region, and the processes of the two are the same and are formed simultaneously;

as shown in fig. 8(B), removing the polysilicon in the P-well ion implantation region by dry etching, and performing ion implantation on the P-well by a self-aligned large-angle implantation process;

the injection angle and the injection dosage of the P trap can be compatible with the BCD process, the injection bevel angle is 35-45 degrees, four times of rotation injection can be adopted, and the accurate injection position of the P trap is ensured. Referring to FIG. 8(C), the P-well implanted ions are boron ions, the implantation energy is 40-55 KeV, and the implantation dose is 2.5E 13-3E 13 cm-2;

as shown in fig. 9, the remaining photoresist on the polysilicon layer 7A is removed with a mixed solution of concentrated sulfuric acid and hydrogen peroxide to form a P well, i.e., a back gate P region 8 and a partial pressure isolation ring P region 9; the invention can ensure the accurate thickness of the photoresist in the subsequent process;

as shown in fig. 10(a), a photoresist 2 is coated on the polysilicon layer 7A and the P region 8 and the P region 9 in the P well, so as to ensure that the surface of the photoresist is flat and the thickness meets the process requirements; defining a gate region on the photoresist 2 by using a gate mask (or a reticle) 3, and forming the gate region by exposure and development;

as shown in fig. 10(B), polysilicon outside the gate region is removed by a dry etching process;

as shown in fig. 11, the photoresist on the gate region is removed by using a mixed solution of concentrated sulfuric acid and hydrogen peroxide to form a polysilicon gate 7;

as shown in fig. 12(a), a photoresist 2 is applied on a polysilicon gate electrode 7 and a gate oxide layer 6, an N + region is defined by an N + mask (reticle) 3, and an N + region is formed in a back gate P region by exposure and development; injecting N + (heavily doped N-type ions) into the N + region to form an N + contact region 10;

as shown in fig. 12(B), an N + ion implantation process is further performed, wherein the implanted ions are As, the implantation energy is 70 to 80KeV, the implantation dose is 7.5E15 to 8E15cm-2, and the N + ion implantation process is compatible with the BCD integration process;

as shown in fig. 12(C), the photoresist 2 on the polysilicon gate 7 and the gate oxide layer 6 is removed by using a mixed solution of concentrated sulfuric acid and hydrogen peroxide;

as shown in fig. 13, which illustrates the formation of an interlayer dielectric layer (ILD) 11; the middle dielectric layer 11 is made of two materials, namely USG (undoped silicate glass) and BPSG (silicate glass containing boron and phosphorus), and both are formed by adopting a chemical vapor deposition process, the USG is deposited to be about 1500-2000 angstroms thick, and the BPSG is deposited to be about 7000-8000 angstroms thick;

as shown in fig. 14(a), a photoresist 2 is coated on an intermediate dielectric layer (ILD) 11, a contact hole region of a D-terminal is defined on the photoresist 2 by using a photomask (or a reticle) 3 of the D-terminal contact hole, and the contact hole region of the D-terminal is formed by exposure and development;

as shown in fig. 14(B), two D-end contact holes 12 are formed in the contact hole region of the D-end by dry etching, the D-end contact holes are of a trench structure, the depth of the trench is 6.5-8 μm, the over-etching amount of the trench is required to be 15% -25%, and the trench is ensured to be communicated with an N-type buried layer (NBL) 4;

as shown in fig. 15, the D-side contact hole 12 is filled, a layer of Ti (thickness about 350 to 450 angstroms) and TiN (thickness about 500 to 600 angstroms) metals are sequentially deposited as a barrier layer by MOCVD (metal organic chemical vapor deposition), and then metal tungsten is deposited by CVD (chemical vapor deposition), wherein the thickness of the metal tungsten is substantially the same as the depth of the trench of the D-side contact hole;

as shown in fig. 16(a), a photoresist 2 is coated on the ILD11 and the D-terminal contact hole 12, a G-terminal contact hole region and an S-terminal contact hole region are defined on the photoresist 2 by using a mask (or a reticle) 3 of a CT (contact hole), and the G-terminal contact hole region and the S-terminal contact hole region are formed by exposure and development;

as shown in fig. 16(B), the G-terminal contact hole 13 and the S-terminal contact hole 14 are formed by dry etching on the G-terminal contact hole region and the S-terminal contact hole region;

as shown in fig. 17, the G-end contact hole 13 and the S-end contact hole 14 are filled, a layer of Ti (thickness about 350 to 450 angstroms) and TiN (thickness about 500 to 600 angstroms) metals are sequentially deposited as a barrier layer by MOCVD (metal organic compound chemical vapor deposition), and then metal tungsten is deposited by CVD (chemical vapor deposition), with a thickness of 3000 to 4000 angstroms;

the subsequent processes are conventional back-end processes such as metal layer deposition, lithography and etching, metal layer passivation, alloying, etc. And finally obtaining the vertical DMOSFET structure.

Finally, it should be noted that: the embodiments described are only a part of the embodiments of the present application, and not all embodiments, and all other embodiments obtained by those skilled in the art without making creative efforts based on the embodiments in the present application belong to the protection scope of the present application.

While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that the described embodiments may be modified in various different ways without departing from the spirit and scope of the invention. Accordingly, the drawings and description are illustrative in nature and should not be construed as limiting the scope of the invention.