阅读说明：本技术 一种基于多路径不对称输入反相器的高速高增益vco电路 (High-speed high-gain VCO circuit based on multi-path asymmetric input inverter ) 是由 吴朝晖 周泽鑫 李斌 郑彦祺 何晨晖 于 2021-07-16 设计创作，主要内容包括：本发明公开了一种基于多路径不对称输入反相器的高速高增益VCO电路,涉及新一代信息技术。针对现有技术中如何提高VCO功耗和速度的问题提出本方案,包括N个级联设置且组成振荡闭环的反相器模块；每路反相通道均包括一主反相器和一辅助反相器；主反相器每个输入端分别间隔一定级数连接前置反相器模块中同一反相通道的主反相器输出端；辅助反相器的输入端连接同一反相通道内主反相器若干个输入端中相位靠前的输入端,辅助反相器的输出端间隔一定级数连接后置反相器模块中另一反相通道内的主反相器输出端。优点在于减小VCO中每级的平均延时；在不增加功耗的前提下,实现环形振荡器差分输出行为的同时,提高VCO的振荡频率及增益。(The invention discloses a high-speed high-gain VCO circuit based on a multipath asymmetric input inverter, and relates to a new generation of information technology. The scheme is provided for solving the problem of how to improve the power consumption and the speed of the VCO in the prior art, and comprises N inverter modules which are arranged in a cascade mode and form an oscillation closed loop; each inverting channel comprises a main inverter and an auxiliary inverter; each input end of the main inverter is connected with the output end of the main inverter of the same inverting channel in the pre-inverter module at intervals of a certain number of stages; the input end of the auxiliary phase inverter is connected with the input end with the front phase in a plurality of input ends of the main phase inverter in the same inverting channel, and the output end of the auxiliary phase inverter is connected with the output end of the main phase inverter in the other inverting channel in the post-phase inverter module at intervals of a certain number of stages. The advantage is that the average delay per stage in the VCO is reduced; on the premise of not increasing power consumption, the differential output behavior of the ring oscillator is realized, and the oscillation frequency and gain of the VCO are improved.)

1. A high-speed high-gain VCO circuit based on a multipath asymmetric input inverter is characterized by comprising N inverter modules which are arranged in a cascade mode and form an oscillation closed loop;

the phase inverter module comprises two paths of phase-inverting channels with symmetrical structures, and the two paths of phase-inverting channels correspondingly input the phase-inverted differential signals; each inverting channel comprises a main inverter and an auxiliary inverter;

the main inverter comprises a plurality of input ends, and each input end is connected with the output end of the main inverter of the same inverting channel in the pre-inverter module at intervals of a certain number of stages;

the input end of the auxiliary phase inverter is connected with the input end, with the front phase, of the plurality of input ends of the main phase inverter in the same inverting channel, and the output end of the auxiliary phase inverter is connected with the output end of the main phase inverter in the other inverting channel in the post-phase inverter module at intervals of a certain number of stages.

2. The high-speed high-gain VCO circuit based on multi-path asymmetric input inverters as claimed in claim 1, wherein the input terminal of the auxiliary inverter is connected to the input terminal with the most phase among the input terminals of the main inverter in the same inverting path.

3. The multi-path asymmetric input inverter based high speed high gain VCO circuit of claim 2 wherein the main inverter comprises four inputs.

4. The high-speed high-gain VCO circuit based on the multi-path asymmetric input inverter as claimed in claim 3, wherein said first input terminal, said second input terminal and said fourth input terminal of said main inverter are connected to said pre-inverter module at intervals of progressively varying stages; and the second input and the third input are common.

5. The high-speed, high-gain VCO circuit based on multi-path asymmetric input inverters, according to claim 4, wherein said first, second and fourth inputs of said main inverter are connected to said pre-inverter block at odd incremental intervals.

6. The high-speed high-gain VCO circuit based on multi-path asymmetric input inverters, according to claim 5, wherein said main inverter has a first input terminal connected to said previous inverter module, a second input terminal connected to said previous inverter module after being in common with said third input terminal, and a fourth input terminal connected to said previous five-stage inverter module.

7. The high-speed high-gain VCO circuit based on the multi-path asymmetric input inverter as claimed in claim 6, wherein said main inverter comprises a first PMOS transistor (P1), a second PMOS transistor (P2), a first NMOS transistor (N1) and a second NMOS transistor (N2);

the grid electrode of the first PMOS tube (P1) is a first input end of the main phase inverter, and the source electrode of the first PMOS tube is connected with a control voltage;

the grid electrode of the second PMOS tube (P2) is a second input end of the main phase inverter, and the source electrode of the second PMOS tube is connected with a control voltage;

the grid electrode of the first NMOS tube (N1) is a third input end of the main phase inverter, and the source electrode is grounded;

the grid electrode of the second NMOS tube (N2) is the fourth input end of the main phase inverter, and the source electrode is grounded;

the common drain electrode of the first PMOS tube (P1), the second PMOS tube (P2), the first NMOS tube (N1) and the second NMOS tube (N2) is used as the output end of the main phase inverter.

8. The high-speed high-gain VCO circuit based on multi-path asymmetric input inverters as claimed in claim 1, wherein the output terminal of said auxiliary inverter is connected to a subsequent inverter module.

9. The high-speed high-gain VCO circuit based on the multi-path asymmetric input inverter as claimed in claim 8, wherein said auxiliary inverter comprises a third PMOS transistor (P3) and a third NMOS transistor (N3) with common gate and common drain; the common gate is used as the input end of the auxiliary phase inverter, and the common drain is used as the output end of the auxiliary phase inverter; the source electrode of the third PMOS pipe (P3) is connected with the control voltage, and the source electrode of the third NMOS pipe (N3) is grounded.

10. The high-speed high-gain VCO circuit based on multi-path asymmetric input inverters according to claims 1 to 9, wherein the number N of cascade of inverter modules is greater than or equal to 5, and N is prime number.

Technical Field

The invention relates to a VCO circuit structure, in particular to a high-speed high-gain VCO circuit based on a multipath asymmetric input inverter.

Background

As the feature size of MOS transistors is gradually reduced with the continuous progress of CMOS process, the design of conventional modules for analog-to-digital (a/D) converters, such as operational amplifiers, transconductors and comparators, faces more and more challenges. In addition, these analog circuits have poor process mobility for other process technology nodes.

With the continuous reduction of the feature size of the CMOS process, the excellent characteristics of the digital circuit are continuously highlighted, the speed of the transistor is continuously increased, the unit integration density is higher, so that the logic delay is continuously reduced, the time resolution is continuously improved, and the digital circuit becomes smaller, faster and more efficient. Therefore, with a small CMOS process size, it is very beneficial to process signals digitally and in the time domain to obtain a low-cost, low-power consumption and high-performance analog-to-digital converter. This has spurred the development of voltage-to-time domain based conversion techniques, the primary representative of which is a Voltage Controlled Oscillator (VCO) based a/D converter.

In a monolithic integrated system, a conventional capacitance-to-digital conversion scheme converts a capacitance value into a voltage value by charging and discharging a capacitor and using a charge amplifier, and then converts an analog voltage value into a digital value by using an a/D converter for output. The above scheme has the following problems: the detection range is limited due to the continuous reduction of the process size and the limitation on the voltage threshold, and the dynamic range is reduced; the reduction of the process size enables the circuit to be more sensitive to the parasitic phenomenon, influences the conversion precision and is not suitable for complex and high-parasitic detection environment; the charge amplifier may cause charge leakage due to non-ideal switching, which reduces the detection accuracy. Each of the above factors reduces the overall performance of the capacitance-to-digital converter. The power consumption and speed of the VCO limit the overall performance of the VCO-based high-order ADC.

Disclosure of Invention

The present invention is directed to a high-speed high-gain VCO circuit based on a multi-path asymmetric input inverter, so as to solve the above problems in the prior art.

The invention discloses a high-speed high-gain VCO circuit based on a multipath asymmetric input inverter, which comprises N inverter modules which are arranged in a cascade mode and form an oscillation closed loop; the phase inverter module comprises two paths of phase-inverting channels with symmetrical structures, and the two paths of phase-inverting channels correspondingly input the phase-inverted differential signals; each inverting channel comprises a main inverter and an auxiliary inverter; the main inverter comprises a plurality of input ends, and each input end is connected with the output end of the main inverter of the same inverting channel in the pre-inverter module at intervals of a certain number of stages; the input end of the auxiliary phase inverter is connected with the input end, with the front phase, of the plurality of input ends of the main phase inverter in the same inverting channel, and the output end of the auxiliary phase inverter is connected with the output end of the main phase inverter in the other inverting channel in the post-phase inverter module at intervals of a certain number of stages.

The input end of the auxiliary phase inverter is connected with the input end with the forefront phase in a plurality of input ends of the main phase inverter in the same inverting channel.

The master inverter includes four inputs.

The first input end, the second input end and the fourth input end of the main inverter are respectively connected with the pre-inverter module at intervals and in progressive change; and the second input and the third input are common.

And the first input end, the second input end and the fourth input end of the main phase inverter are respectively connected with the pre-inverter module at intervals of odd progressive change.

The first input end of the main phase inverter is connected with the previous-stage phase inverter module, the second input end and the third input end are connected with the previous-stage phase inverter module after being in a point-sharing mode, and the fourth input end is connected with the previous-fifth-stage phase inverter module.

The main phase inverter comprises a first PMOS tube, a second PMOS tube, a first NMOS tube and a second NMOS tube; the grid electrode of the first PMOS tube is a first input end of the main phase inverter, and the source electrode of the first PMOS tube is connected with control voltage; the grid electrode of the second PMOS tube is a second input end of the main phase inverter, and the source electrode of the second PMOS tube is connected with control voltage; the grid electrode of the first NMOS tube is a third input end of the main phase inverter, and the source electrode of the first NMOS tube is grounded; the grid electrode of the second NMOS tube is the fourth input end of the main phase inverter, and the source electrode of the second NMOS tube is grounded; and the common drain electrode of the first PMOS tube, the second PMOS tube, the first NMOS tube and the second NMOS tube is used as the output end of the main phase inverter.

And the output end of the auxiliary phase inverter is connected with the latter-stage phase inverter module.

The auxiliary phase inverter comprises a third PMOS tube and a third NMOS tube which share a grid and a drain; the common gate is used as the input end of the auxiliary phase inverter, and the common drain is used as the output end of the auxiliary phase inverter; the source electrode of the third PMOS tube is connected with the control voltage, and the source electrode of the third NMOS tube is grounded.

The cascade number N of the inverter modules is more than or equal to 5, and in order to ensure stability, the total cascade number N is generally far larger than the number of input paths and is a prime number.

The high-speed high-gain VCO circuit based on the multipath asymmetric input inverter has the advantages that the multipath asymmetric input inverter is used, slower PMOS input signals are allowed to arrive earlier, and the average delay of each stage in the VCO is reduced; the multiple input signals to the inverter module further improves the delay per stage. The output of the inverter module of the later stage is precharged using a "feed forward" coupled auxiliary inverter. On the premise of not increasing power consumption, the differential output behavior of the ring oscillator is realized, and the oscillation frequency and gain of the VCO are improved.

Drawings

Fig. 1 is a schematic diagram of a high-speed high-gain VCO circuit according to the present invention.

Fig. 2 is a schematic structural diagram of an inverter module with serial number i according to the present invention.

FIG. 3 is a logic diagram of the port connection between the inverter module with serial number i and other inverter modules according to the present invention.

FIG. 4 is a schematic diagram of the structure of each main inverter according to the present invention.

FIG. 5 is a schematic diagram of the structure of each auxiliary inverter according to the present invention.

Fig. 6 is a schematic structural diagram of a first embodiment of the present invention.

Reference numerals:

INV 11-first main inverter, INV 12-first auxiliary inverter;

INV 21-second main inverter, INV 22-second auxiliary inverter;

A_i,1to A_i,4-a first output to a fourth output of an inverter module with sequence number i;

B_i,1to B_i,8-a first input to an eighth input of an inverter module with sequence number i;

P1-P3-first to third PMOS tubes;

n1 to N3-first to third NMOS transistors.

Detailed Description

As shown in fig. 1, the high-speed high-gain VCO circuit based on the multi-path asymmetric input inverter according to the present invention includes more than 5 inverter modules which are arranged in cascade and constitute an oscillation closed loop. The phase inverter module comprises two opposite-phase channels with symmetrical structures, and the two opposite-phase channels correspondingly input opposite-phase differential signals.

Each inverting channel includes a main inverter and an auxiliary inverter. As shown in fig. 2, the first inversion path includes a first main inverter INV11 and a first auxiliary inverter INV12, and the second inversion path includes a second main inverter INV21 and a second auxiliary inverter INV 22. The first main inverter INV11 and the second main inverter INV21 have the same structure, and the first auxiliary inverter INV12 and the second auxiliary inverter INV22 have the same structure.

Each inverter module includes eight inputs and four outputs: for example, the first main inverter INV11 in the inverter module with serial number i includes a first input terminal B_i,1A second input terminal B_i,2A third input terminal B_i,3And a fourth input terminal B_i,4(ii) a The second main inverter INV21 includes a fifth input terminal B_i,5A sixth input terminal B_i,6A seventh input terminal B_i,7And an eighth input terminal B_i,8. The output end of the first main inverter INV11 is the first output end A of the inverter module_i,1. Input terminal of the first auxiliary inverter INV12 anda first input terminal B_i,1Common point, the output end is the second output end A of the phase inverter module_i,2. The output end of the second main inverter INV21 is the fourth output end A of the inverter module_i,4. An input end and an eighth input end B of the second auxiliary inverter INV22_i,8Common point, the output end is the third output end A of the phase inverter module_i,3。

The input logic of each inverter module is the same, and each input end of the main inverter is mainly used for receiving output signals of the pre-inverter modules with different levels. Such as the particular input logic shown in fig. 3, the first through fourth inputs are in the first inverting path and the fifth through eighth inputs are in the second inverting path. The first input end is connected with the previous-stage inverter module, the second input end and the third input end can be arranged in a concurrent mode and then connected with the previous-stage inverter module, and the fourth input end is connected with the previous-fifth-stage inverter module. The output end of the auxiliary phase inverter positioned in the first phase inversion channel is connected with the output end of the main phase inverter in the second phase inversion channel in the subsequent phase inverter module. Since the inverter module inputs and outputs are both differential signals, the connection logic of the second inverting path is arranged symmetrically to the first inverting path. The multipath asymmetric input referred to in the present invention refers to multipath and asymmetry within the same antiphase channel.

In the logic schematic, (i-1), (i-2), etc., are to be understood as the reciprocal first and second order, i.e. A, against the signal propagation direction with the origin of the inverter module with the serial number i_(i-1),1Is the first output end of the previous phase inverter module; similarly, (i +1) should be understood as being one step up in the direction of signal propagation, i.e. A_(i+1),4Is the fourth output terminal of the latter stage inverter module. When i is 1, i-4 will become a negative number, and since the VCO circuit of the present invention is a closed loop, one skilled in the art should unambiguously determine that the sequence number when i-4 is not a positive number should be i-4+ N, where N is the total number of cascades. Similarly, when i +1 is greater than N, the corresponding sequence number should be determined to be i + 1-N. Under the inventive concept disclosed in the present invention, one skilled in the art can make different skip level changes to the input logic according to the specific cascade number and the actual oscillation requirement,should be considered as belonging to the equivalent scheme of the invention.

The invention provides a specific structure of the main inverter, as shown in fig. 4: the main phase inverter comprises a first PMOS pipe P1, a second PMOS pipe P2, a first NMOS pipe N1 and a second NMOS pipe N2. The grid electrode of the first PMOS pipe P1 is a first input end of the main phase inverter, and the source electrode is connected with a control voltage. The grid electrode of the second PMOS pipe P2 is the second input end of the main phase inverter, and the source electrode is connected with the control voltage. The grid electrode of the first NMOS pipe N1 is the third input end of the main phase inverter, and the source electrode is grounded. The gate of the second NMOS transistor N2 is the fourth input terminal of the main inverter, and the source is grounded. The common drain electrode of the first PMOS pipe P1, the second PMOS pipe P2, the first NMOS pipe N1 and the second NMOS pipe N2 is used as the output end of the main phase inverter.

The invention provides a specific structure of the auxiliary inverter, as shown in fig. 5: the auxiliary phase inverter comprises a third PMOS pipe P3 and a third NMOS pipe N3 which share a gate and a drain. And the common gate is used as the input end of the auxiliary phase inverter, and the common drain is used as the output end of the auxiliary phase inverter. The source of the third PMOS transistor P3 is connected to the control voltage, and the source of the third NMOS transistor N3 is grounded.

The high-speed high-gain VCO circuit based on the multipath asymmetric input inverter has the following working principle: asymmetrically connecting the PMOS and NMOS input signals to different delay stage outputs allows the input signals to reach the slower PMOS transistors earlier, thereby reducing the average delay of the inverter modules per stage. By establishing a plurality of connections, i.e. a plurality of path inputs, in each stage of inverter module, the driving strength of the output node of each stage of inverter module can be enhanced, thereby reducing the average delay and gain of each stage of inverter module. Aligning only the edges of the differential delay output is done relative to conventional coupled inverters so that the differential delay will switch at the same time. By adopting the feedforward coupled auxiliary phase inverter, output signals of differential phase inverter modules can be switched simultaneously, the output end of the subsequent phase inverter module can be charged in advance, the power consumption of the coupled phase inverter is efficiently utilized, and the average delay and gain of each stage of phase inverter module are further improved.

In the high-speed high-gain VCO circuit based on the multipath asymmetric input inverter, in order to ensure stability, the total cascade number N is far larger than the number of input paths and is a prime number. In the embodiment of the present invention, the number of paths is 2. For forming a closed-loop structure, the closed loop can be realized only by N being more than or equal to 5. For a more intuitive illustration, the lowest odd-numbered stage, i.e., N-5, is used as an embodiment, and the structure is shown in fig. 6.

It will be apparent to those skilled in the art that various other changes and modifications may be made in the above-described embodiments and concepts and all such changes and modifications are intended to be within the scope of the appended claims.