阅读说明：本技术 碳化硅半导体器件的制造方法和碳化硅半导体器件 (Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device ) 是由 大西徹 朽木克博 山本建策 于 2019-01-29 设计创作，主要内容包括：碳化硅半导体器件的制造方法可以包括：在碳化硅衬底上形成栅极绝缘膜；在栅极绝缘膜上形成栅电极。栅极绝缘膜的形成可以包括通过在氮气氛下热氧化碳化硅衬底而在碳化硅衬底上形成氧化物膜。(The method of manufacturing a silicon carbide semiconductor device may include: forming a gate insulating film on the silicon carbide substrate; a gate electrode is formed on the gate insulating film. The forming of the gate insulating film may include forming an oxide film on the silicon carbide substrate by thermally oxidizing the silicon carbide substrate under a nitrogen atmosphere.)

1. A method of manufacturing a silicon carbide semiconductor device, the method comprising:

forming a gate insulating film on the silicon carbide substrate; and

forming a gate electrode on the gate insulating film,

wherein

The forming of the gate insulating film includes forming an oxide film on the silicon carbide substrate by thermally oxidizing the silicon carbide substrate under a nitrogen atmosphere.

2. The manufacturing method according to claim 1,

the thickness of the oxide film is equal to or greater than 4nm and equal to or less than 45 nm.

3. The manufacturing method according to claim 1,

the formation of the oxide film is performed under the nitrogen atmosphere including nitric oxide gas.

4. The manufacturing method according to claim 3,

the formation of the oxide film is performed under the conditions that the gas concentration of the nitric oxide gas is equal to or more than 10% and the thermal oxidation temperature is equal to or more than 1300 degrees celsius.

5. The manufacturing method according to claim 1,

the forming of the gate insulating film further includes forming a deposited film of an insulator on the oxide film.

6. The manufacturing method according to claim 5,

chemical vapor deposition or atomic layer deposition is used for the formation of the deposited film.

7. The manufacturing method according to claim 5,

the deposited film has a higher dielectric constant than the oxide film.

8. A silicon carbide semiconductor device comprising:

a silicon carbide substrate;

a gate insulating film provided on the silicon carbide substrate; and

a gate electrode disposed on the gate insulating film,

wherein

The gate insulating film includes:

an oxide film disposed on the silicon carbide substrate; and

a deposited film disposed on the oxide film.

9. The silicon carbide semiconductor device according to claim 8, wherein

The thickness of the oxide film is thinner than the thickness of the deposited film.

10. The silicon carbide semiconductor device according to claim 9, wherein

The thickness of the oxide film is equal to or greater than 4nm and equal to or less than 45 nm.

11. The silicon carbide semiconductor device according to claim 8, wherein

The deposited film has a higher dielectric constant than the oxide film.

Technical Field

The technology disclosed herein relates to a method for manufacturing a silicon carbide semiconductor device. Further, the technology disclosed herein relates to a silicon carbide semiconductor device.

Background

Silicon carbide semiconductor devices have been developed. To form an insulated gate, a method of manufacturing a silicon carbide semiconductor device includes forming a gate insulating film on a silicon carbide substrate, and forming a gate electrode on the gate insulating film.

Japanese patent No. 5608840 describes a technique of forming a gate insulating film composed of an oxide film by thermally oxidizing a silicon carbide substrate. However, when the oxide film is formed by thermally oxidizing the silicon carbide substrate, a part of carbon in the silicon carbide substrate cannot be sublimated to remain in the oxide film. In particular, carbon remaining in the oxide film within a few nanometers from the interface between the silicon carbide substrate and the oxide film is considered to cause generation of charge traps. Such charge traps are considered to cause fluctuations in threshold voltage when a positive bias is applied to the gate electrode.

Japanese patent No. 5608840 describes a technique of performing a nitriding treatment after forming an oxide film by thermally oxidizing a silicon carbide substrate. Japanese patent No. 5608840 states that the nitriding process can reduce charge traps generated by carbon remaining at the interface between the silicon carbide substrate and the oxide film. However, in the nitriding treatment after the formation of the oxide film, there are problems that: since the film thickness of the formed oxide film is large, carbon remains at the interface between the silicon carbide substrate and the oxide film, and carbon is regenerated since the silicon carbide substrate is oxidized. Therefore, the technique in japanese patent No. 5608840 has difficulty in favorably reducing the charge traps in the oxide film of the insulated gate.

The present invention aims to provide a technique for manufacturing a silicon carbide semiconductor device in which charge traps in an oxide film of an insulated gate are reduced.

Disclosure of Invention

The method for manufacturing a silicon carbide semiconductor device disclosed in the present invention may include: forming a gate insulating film on the silicon carbide substrate; and forming a gate electrode on the gate insulating film. The forming of the gate insulating film may include forming an oxide film on the silicon carbide substrate by thermally oxidizing the silicon carbide substrate under a nitrogen atmosphere. In this manufacturing method of the silicon carbide semiconductor device, an oxide film is formed by thermally oxidizing the silicon carbide substrate under a nitrogen atmosphere. Therefore, carbon in the silicon carbide substrate combines with nitrogen, becomes carbon nitride gas, and advantageously sublimates, thereby suppressing carbon from remaining in the oxide film and reducing charge traps in the oxide film.

Drawings

[ FIG. 1]

Fig. 1 schematically shows a cross-sectional view of a main portion of a silicon carbide semiconductor device according to an embodiment.

[ FIG. 2]

Fig. 2 schematically shows an enlarged cross-sectional view of a main portion in the vicinity of a channel of an insulated gate of a silicon carbide semiconductor device according to the present embodiment.

[ FIG. 3]

Fig. 3 shows a flowchart of a process of manufacturing an insulated gate of the silicon carbide semiconductor device according to the present embodiment.

[ FIG. 4]

Fig. 4 shows the relationship between the CV hysteresis and the thickness of the oxide film of the insulated gate in the silicon carbide semiconductor device according to the present embodiment.

[ FIG. 5]

Fig. 5 shows CV hysteresis when an insulated gate is formed on a polar plane and a non-polar plane in each of the silicon carbide semiconductor device according to the present embodiment and the silicon carbide semiconductor device having a conventional structure.

[ FIG. 6]

Fig. 6 shows the relationship between the CV hysteresis of the interface between the silicon carbide substrate and the oxide film and the nitrogen concentration under the condition of changing the NO direct oxidation.

[ FIG. 7]

Fig. 7 shows a nitrogen concentration distribution in the thickness direction in the vicinity of the interface between the silicon carbide substrate and the oxide film in each of the silicon carbide semiconductor device according to the present embodiment and the silicon carbide semiconductor device having the conventional structure.

[ FIG. 8]

Fig. 8 shows the interface state density of the interface between the silicon carbide substrate and the oxide film in each of the silicon carbide semiconductor device according to the present embodiment and the silicon carbide semiconductor device having the conventional structure.

[ FIG. 9]

Fig. 9 shows a flat band (flat band) voltage of an insulated gate in each of the silicon carbide semiconductor device according to the present embodiment and the silicon carbide semiconductor device having a conventional structure.

[ FIG. 10]

Fig. 10 shows the amount of fluctuation of the threshold voltage after applying a positive bias stress to the gate electrode based on the threshold voltage before application in each of the silicon carbide semiconductor device according to the present embodiment and the silicon carbide semiconductor device having the conventional structure. (note that in the present invention, the "amount of fluctuation of the threshold voltage after applying a bias to the gate electrode" is calculated based on the threshold voltage before application, and therefore the description of "based on the threshold voltage before application" will be omitted hereinafter).

[ FIG. 11]

Fig. 11 shows the fluctuation amount of the threshold voltage after applying the negative bias stress to the gate electrode based on the threshold voltage before application in the silicon carbide semiconductor device according to the present embodiment.

[ FIG. 12]

Fig. 12 shows the areal density of traps in the oxide film in the vicinity of the interface between the silicon carbide substrate and the oxide film in each of the silicon carbide semiconductor device according to the present embodiment and the silicon carbide semiconductor device having the conventional structure.

Detailed Description

Representative, non-limiting examples of the present invention will now be described in more detail with reference to the accompanying drawings. This detailed description is merely intended to introduce those skilled in the art to further details for practicing preferred aspects of the present invention and is not intended to limit the scope of the invention. In addition, each of the additional features and teachings disclosed below may be used alone or in combination with other features and teachings to provide improved silicon carbide semiconductor devices, and methods of using and manufacturing silicon carbide semiconductor devices.

Furthermore, combinations of features and steps disclosed in the following detailed description may not be necessary to practice the invention in the broadest sense, and are instead taught merely to particularly describe representative examples of the invention. Furthermore, the various features of the representative examples described above and below, as well as the various independent and dependent claims, may be combined in ways that are not specifically and explicitly enumerated in order to provide additional useful embodiments of the present teachings.

All features disclosed in the specification and/or the claims are intended to be disclosed independently of each other and of the composition of the features in the embodiments and/or the claims for the purpose of original written disclosure and for the purpose of restricting the claimed subject matter. Further, for purposes of original written disclosure, as well as to limit claimed subject matter, the identification of a full range of values or groups of entities is intended to disclose each possible intermediate value or intermediate entity.

As shown in fig. 1, the silicon carbide semiconductor device 1 is a power semiconductor element called a MOSFET (metal oxide semiconductor field effect transistor), and includes a silicon carbide substrate 10, a drain electrode 22 covering a rear surface of the silicon carbide substrate 10, a source electrode 24 covering a part of a front surface of the silicon carbide substrate 10, and a planar-type insulated gate 30 provided at a part of the front surface of the silicon carbide substrate 10. The silicon carbide substrate 10 includes n⁺Type drain region 11, n^-Drift region 12, p-type body region 13, n⁺Source regions 14 and p⁺A profile contact region 15.

The drain region 11 is provided in the back layer portion of the silicon carbide substrate 10, and is provided on the back surface of the silicon carbide substrate 10. The drain region 11 also serves as a base substrate for epitaxial growth of the drift region 12, which will be described later. The drain region 11 is in ohmic contact with a drain electrode 22 covering the back surface of the silicon carbide substrate 10.

The drift region 12 is disposed on the drain region 11, and includes an opening portion 12a in contact with a portion of the bottom surface of the insulated gate 30. The drift region 12 is formed by performing crystal growth on the front surface of the drain region 11 using an epitaxial growth technique.

A body region 13 is disposed on the drift region 12 and in a front layer portion of the silicon carbide substrate 10. The body regions 13 are provided with opening portions 12a interposed between the drift regions 12, and each body region 13 is in contact with a portion of the bottom surface of the insulated gate 30. The body region 13 is formed by introducing aluminum into a front layer portion of the silicon carbide substrate 10 using an ion implantation technique.

The source regions 14 are respectively provided on the body regions 13, are provided in a front layer portion of the silicon carbide substrate 10, and are exposed at the front surface of the silicon carbide substrate 10. The source region 14 is separated from the drift region 12 by a body region 13. The source region 14 is formed by introducing nitrogen or phosphorus into the front layer portion of the silicon carbide substrate 10 using an ion implantation technique. The source region 14 is in ohmic contact with a source electrode 24 covering the front surface of the silicon carbide substrate 10.

The body contact regions 15 are respectively provided on the body regions 13, are provided in a front layer portion of the silicon carbide substrate 10, and are exposed at the front surface of the silicon carbide substrate 10. The body contact region 15 contacts the body region 13. The body contact region 15 is formed by introducing aluminum into a front layer portion of the silicon carbide substrate 10 using an ion implantation technique. The body contact region 15 is in ohmic contact with the source electrode 24 covering the front surface of the silicon carbide substrate 10.

The insulated gate 30 is provided at a part of the front surface of the silicon carbide substrate 10, and includes a gate insulating film 32 and a gate electrode 34. The gate insulating film 32 is provided on the front surface of the silicon carbide substrate 10, and is in contact with the front surface of the silicon carbide substrate 10. The gate electrode 34 is disposed on the front surface of the gate insulating film 32, and is in contact with the gate insulating film 32. The gate electrode 34 is opposed to a part of each body region 13 between the corresponding source region 14 and the opening portion 12a of the drift region 12 via the gate insulating film 32. In the silicon carbide semiconductor device 1, the portion of the body region 13 between the source region 14 and the opening portion 12a of the drift region 12 serves as a channel.

Fig. 2 schematically shows an enlarged cross-sectional view of a main portion of the insulated gate 30. Fig. 2 is an enlarged cross-sectional view of a main portion in the vicinity of the channel in the body region 13. As shown in fig. 2, the gate insulating film 32 includes an oxide film 32a and a deposited film 32b, and is constituted by a two-layer structure.

The oxide film 32a is in contact with the front surface of the silicon carbide substrate 10, and is disposed between the silicon carbide substrate 10 and the deposited film 32 b. As described below, the oxide film 32a is formed by using thermal oxidation, and is composed of silicon oxide.

The deposited film 32b is in contact with the front surface of the oxide film 32a, and is disposed between the oxide film 32a and the gate electrode 34. The deposition film 32b is formed by using vapor deposition such as Chemical Vapor Deposition (CVD), as described below, and is composed of silicon oxide. In this example, the thickness T2 of the deposited film 32b is greater than the thickness T1 of the oxide film 32 a.

The sum (T1+ T2) of the thickness T1 of the oxide film 32a and the thickness T2 of the deposited film 32b, that is, the thickness of the gate insulating film 32 is equal to or greater than 50nm and equal to or less than 100 nm. The thickness of the gate insulating film 32 in this range can ensure a desired gate capacitance while ensuring the withstand voltage of the gate insulating film 32.

The deposited film 32b may be composed of an insulator having a higher dielectric constant than silicon oxide, instead of silicon oxide. By the deposition film 32b constituting the high dielectric constant insulator, the gate capacitance of the gate insulating film 32 can be easily ensured, and therefore the thickness T1 of the oxide film 32a can be reduced. Examples of the high dielectric constant insulator include an SiON-based insulator and an Al-based insulator₂O₃The insulator of (1). Further, the deposition film 32b may be formed by using atomic layer deposition (ALT) instead of CVD.

Fig. 3 shows a manufacturing process of the insulated gate 30 of the silicon carbide semiconductor device 1. First, the oxide film 32a is formed on the front surface of the silicon carbide substrate 10 by using thermal oxidation (hereinafter referred to as "NO direct oxidation") under a nitrogen monoxide atmosphere (S1). Next, the deposited film 32b is formed on the front surface of the oxide film 32a by using CVD (S2). Then, the gate electrode 34 is formed on the front surface of the deposition film 32b (S3). Through these steps, the insulated gate 30 of the silicon carbide semiconductor device 1 is formed.

Fig. 4 shows the relationship between the thickness T1 (see fig. 2) and CV hysteresis (hystersis) of the oxide film 32a formed by direct oxidation using NO. Here, an expression shown below is established, wherein Q_OTShowing a charge trap in the gate insulating film 32, C_OXThe capacitance of the gate insulating film 32 is shown, and dV is CV lag.

Q_OT＝C_OX×dV(1)

As shown in expression 1, the charge trap Q in the gate insulating film 32_OTProportional to the CV lag dV. As shown in fig. 4, it was found that in the case where the thickness T1 of the oxide film 32a of the gate insulating film 32 was equal to or more than 4nm and equal to or less than 45nm, the CV hysteresis dV was suppressed to be low, and the charge trap Q was_OTIs suppressed low.

When the oxide film 32a is formed on the front surface of the silicon carbide substrate 10 and remains within several nanometers from the interface between the silicon carbide substrate 10 and the oxide film 32a, the charge traps Q_OTIs believed to result from the failure of some of the carbon in the silicon carbide substrate 10 to sublime. In the present embodiment, as described above, the oxide film 32a is formed by direct oxidation using NO. Therefore, when the oxide film 32a is formed on the front surface of the silicon carbide substrate 10, a part of carbon in the silicon carbide substrate 10 combines with nitrogen in the oxynitride, becomes carbon nitride gas, and favorably sublimates, thereby suppressing carbon from remaining in the oxide film 32 a. Thus, the charge trap Q in the oxide film 32a_OTIs considered to be suppressed low. In particular, setting the thickness T1 of the oxide film 32a to be equal to or greater than 4nm can reduce the amount of carbon remaining within several nanometers from the interface between the silicon carbide substrate 10 and the oxide film 32a, and can thereby effectively suppress the charge trap Q_OTIs generated. However, setting the thickness T1 of the oxide film 32a to be greater than 45nm is considered to inhibit sublimation of carbon in the silicon carbide substrate 10. Therefore, the thickness T1 of the oxide film 32a is desirably in the range of equal to or greater than 4nm and equal to or less than 45 nm.

Further, the formation of the oxide film 32a by direct oxidation using NO can terminate dangling bonds of silicon in the silicon carbide substrate 10 without using an excessive amount of nitrogen. For example, in the conventional technique, after a gate insulating film is formed on a silicon carbide substrate, a nitridation treatment is performed to terminate dangling bonds. In this case, there are problems in that: since excessive nitrogen is introduced into the interface between the silicon carbide substrate and the gate insulating film, and since the introduced nitrogen oxide oxidizes the silicon carbide substrate, the amount of residual carbon increases. Further, there is a fear that nitrogen introduced into the interface between the silicon carbide substrate and the gate insulating film may become a source of hole traps and may increase the fluctuation amount of the threshold voltage after applying a negative bias voltage to the gate electrode. On the other hand, with the technique of this embodiment using NO direct oxidation, excess nitrogen is discharged without being introduced into the interface between the silicon carbide substrate 10 and the gate insulating film 32. Thereby preventing the above-mentioned problems caused by excessive nitrogen.

Some characteristics of the insulated gate 30 including the oxide film 32a formed by direct oxidation using NO will be described below. The conventional structure mentioned below is an example of an insulated gate including a gate insulating film formed by performing a nitriding process after forming an oxide film using only CVD. The thickness of the oxide film in the conventional structure was 80 nm.

(dependence on planar orientation)

Silicon carbide has different atomic arrangements depending on the plane orientation, and thus it has a non-polar plane (m-plane or a-plane) and a polar plane (Si-plane or C-plane). As shown in fig. 5, it was found that the present embodiment shows lower CV hysteresis than the conventional structure in the case of polar and non-polar planes. In the data shown in fig. 5, the insulated gate 30 of the present embodiment includes the oxide film 32a having a thickness T1 of 10 nm.

(production conditions for NO direct Oxidation)

Fig. 6 shows the relationship between the CV hysteresis at the interface between the silicon carbide substrate 10 and the oxide film 32a and the nitrogen concentration under the manufacturing conditions in which the NO direct oxidation (the gas concentration of nitrogen oxide and the thermal oxidation temperature) varies. The nitrogen concentration was measured by using secondary ion mass spectrometry. As shown in fig. 6, it was found that the insulated gate 30 in the present embodiment shows a lower CV hysteresis than the conventional structure under any manufacturing conditions. Further, it was found that in the present embodiment, under the manufacturing conditions in which the gas concentration of the nitrogen oxide gas is equal to or greater than 10% and the thermal oxidation temperature is equal to or greater than 1300 degrees celsius, the nitrogen concentration at the interface is much lower than that in the conventional structure. Thus, in the technique using NO direct oxidation, it is suggested that nitrogen required for dangling bonds of silicon in the silicon carbide substrate 10 be absorbed without shortage or excess, and therefore excess nitrogen is not introduced into the interface between the silicon carbide substrate 10 and the gate insulating film 32. In the data shown in fig. 6, the insulated gate 30 of the present embodiment includes the oxide film 32a having a thickness T1 of 10 nm.

(Nitrogen concentration depth profile)

Fig. 7 shows a nitrogen concentration distribution in the depth direction of the silicon carbide substrate 10 and the gate insulating film 32. A depth of about 78nm corresponds to the silicon carbide substrate 10 (denoted as SiC in fig. 7) and the gate insulating film 32 (denoted as SiO in fig. 7)₂) The depth of the interface therebetween. As a result in fig. 6, it was also found in the data shown in fig. 7 that the nitrogen concentration in the depth direction in the vicinity of the interface between the silicon carbide substrate 10 and the gate insulating film 32 of the present embodiment is lower than that in the conventional structure. In the data shown in fig. 7, the insulated gate 30 of the present embodiment includes the oxide film 32a having a thickness T1 of 10 nm.

(interface State Density)

Fig. 8 shows the interface state density measured by the raman method. The interface state density is believed to be related to the mobility of carriers through the channel. As shown in fig. 8, the interface state density in the present example was found to be comparable to that in the conventional structure. Therefore, it is suggested that the technique using NO direct oxidation can sufficiently reduce defects at the interface between the silicon carbide substrate 10 and the gate insulating film 32. In the data shown in fig. 8, the insulated gate 30 of the present embodiment includes the oxide film 32a having a thickness T1 of 10 nm.

(Flat belt voltage)

Fig. 9 shows the measured flat band voltage. The flat band voltage is considered to be related to the threshold voltage. As shown in fig. 9, the flat band voltage in the present embodiment was found to be comparable to that in the conventional structure. In the data shown in fig. 9, the insulated gate 30 of the present embodiment includes the oxide film 32a having a thickness T1 of 10 nm.

(amount of fluctuation of threshold voltage due to Positive bias stress)

FIG. 10 shows the fluctuation amount of the threshold voltage after applying a positive bias stress to gate electrode 34. the applied positive bias is 25 volts. As shown in FIG. 10, the fluctuation amount of the threshold voltage in the present embodiment is found to be smaller than that in the conventional structure. the present embodiment has 2.1 × 10¹²cm^-2eV^-1And interface state of 10cm²/V_SConventional structure has a mobility of 2.1 × 10¹²cm^-2eV^-1And an interface state of 9.8cm²/V_SMobility of (2). Thus, the present embodiment is not different from the conventional structure in terms of interface state and mobility. Meanwhile, it is found that the fluctuation amount of the threshold voltage under the positive bias stress is suppressed in the present embodiment.

(amount of fluctuation of threshold voltage due to negative bias stress)

Fig. 11 shows the fluctuation amount of the threshold voltage after applying the negative bias stress to gate electrode 34. The negative bias applied is-10 volts. As shown in fig. 11, it was found that the fluctuation amount of the threshold voltage in the present embodiment is very small. As described above, there is a fear that nitrogen introduced into the interface between the silicon carbide substrate and the gate insulating film may be a source of hole traps, and the fluctuation amount of the threshold voltage may increase after applying negative bias stress to the gate electrode. On the other hand, in the technique using NO direct oxidation, excessive nitrogen is not introduced into the interface between the silicon carbide substrate 10 and the gate insulating film 32. Therefore, it is proposed to suppress the fluctuation amount of the threshold voltage under the negative bias stress.

(trap area density)

Fig. 12 shows the areal density of charge traps measured by using the capacitance transient method in the oxide film 32a in the vicinity of the interface between the silicon carbide substrate 10 and the oxide film 32 a. As shown in fig. 12, it was found that the areal density of the traps in the present embodiment is smaller than that in the conventional structure.

Based on these results, the silicon carbide semiconductor device 1 of the present embodiment includes at least the following features.

(1) The technique using NO direct oxidation reduces charge traps in the oxide film 32a, whereby the fluctuation amount of the threshold voltage under the forward bias stress can be suppressed.

(2) The technique using NO direct oxidation suppresses introduction of excessive nitrogen into the gate insulating film 32, whereby the fluctuation amount of the threshold voltage under negative bias stress can be suppressed.

(3) The present embodiment has an interface state density between the silicon carbide substrate 10 and the oxide film 32a comparable to that in the conventional structure and a sufficiently low defect density.

Some of the features of the above-described embodiments will be listed here. It should be noted that the respective technical elements are independent of each other and used alone or in combination. Their combination is not limited to those described in the originally filed claims.

As the silicon carbide semiconductor device disclosed herein, a MOSFET (metal oxide semiconductor field effect transistor) and an IGBT (insulated gate bipolar transistor) are exemplified. The method for manufacturing a silicon carbide semiconductor device disclosed in the present invention may include: forming a gate insulating film on the silicon carbide substrate; and forming a gate electrode on the gate insulating film. The insulated gate including the insulating film and the gate electrode may be of a planar type disposed on the front surface of the silicon carbide substrate. Alternatively, the insulated gate may be of the channel type, which is disposed in a channel in a front-layer portion of the silicon carbide substrate. The forming of the gate insulating film may include forming an oxide film on the silicon carbide substrate by thermally oxidizing the silicon carbide substrate under a nitrogen atmosphere.

In the above manufacturing method, the thickness of the oxide film may be equal to or greater than 4nm and equal to or less than 45 nm. By setting the thickness of the oxide film within such a range, carbon can be favorably suppressed from remaining in the oxide film, with the result that charge traps in the oxide film can be favorably reduced.

In the above manufacturing method, the formation of the oxide film may be performed under a nitrogen atmosphere including a nitric oxide gas. Thermal oxidation under a nitrogen atmosphere comprising nitric oxide gas may advantageously terminate dangling bonds of silicon in the silicon carbide substrate.

In the above manufacturing method, the formation of the oxide film may be performed under the condition that the gas concentration of the nitric oxide gas is equal to or more than 10% and the thermal oxidation temperature is equal to or more than 1300 degrees celsius. Forming the oxide film under such manufacturing conditions can suppress an excessive amount of nitrogen from being introduced into the oxide film. Thereby, the fluctuation amount of the threshold voltage after applying the negative bias stress to the gate electrode can be suppressed.

In the above manufacturing method, the forming of the gate insulating film may further include forming a deposited film of an insulator on the oxide film. By forming such a deposited film, the thickness of the oxide film can be reduced while ensuring the thickness required for the gate insulating film. Since the thickness of the oxide film can be reduced, carbon of the silicon carbide substrate can be favorably sublimated when the oxide film is formed by thermal oxidation. Chemical vapor deposition or atomic layer deposition may be used for the formation of the deposited film.

In the above manufacturing method, the deposited film may have a higher dielectric constant than the oxide film. By the deposition film constituting such a high dielectric constant insulator, the gate capacitance of the gate insulating film can be secured by the deposition film, whereby the thickness of the oxide film can be reduced. Since the thickness of the oxide film can be reduced, carbon of the silicon carbide substrate can be favorably sublimated when the oxide film is formed by thermal oxidation.

The silicon carbide semiconductor device disclosed in the present invention may include a silicon carbide substrate, a gate insulating film provided on the silicon carbide substrate, and a gate electrode provided on the gate insulating film. The insulated gate including the gate insulating film and the gate electrode may be of a planar type disposed on the front surface of the silicon carbide substrate. Alternatively, the insulated gate may be of the channel type, which is disposed in a channel in a front-layer portion of the silicon carbide substrate. The gate insulating film may include an oxide film provided on the silicon carbide substrate and a deposited film provided on the oxide film.

In the above silicon carbide semiconductor device, the thickness of the oxide film may be thinner than that of the deposited film. Further, the thickness of the oxide film may be equal to or greater than 4nm and equal to or less than 45 nm. Carbon can be favorably suppressed from remaining in the oxide film whose thickness is adjusted to this range, with the result that charge traps in the oxide film can be favorably reduced.

In the above silicon carbide semiconductor device, the deposited film may have a higher dielectric constant than the oxide film. By the deposition film constituting such a high dielectric constant insulator, the gate capacitance of the gate insulating film can be secured by the deposition film, whereby the thickness of the oxide film can be reduced. Carbon can be favorably suppressed from remaining in the oxide film reduced in thickness, and as a result, charge traps in the oxide film can be favorably reduced.

Specific examples of the present invention have been described in detail, however, these are merely exemplary indications and thus do not limit the scope of the claims. The techniques described in the claims include modifications and variations to the specific examples described above. The technical features described in the specification and the drawings can be technically used alone or in various combinations and are not limited to the combinations initially claimed. Further, the techniques described in the specification and drawings can achieve a plurality of objectives at the same time, and their technical meaning is to achieve any of these objectives.