Method and system for providing multi-level distributed decision feedback equalization
阅读说明：本技术 提供多级分布式判定反馈均衡的方法和系统 (Method and system for providing multi-level distributed decision feedback equalization ) 是由 阿明·塔亚丽 于 2018-12-07 设计创作，主要内容包括：对两组或更多组节点进行预充电,以将与该两组或更多组节点连接的多输入求和锁存器的差分输出设置于预充电状态,所述两组或更多组节点包括一组数据信号节点和一组DFE校正节点；响应于采样时钟,生成差分数据电压以及总差分DFE校正信号；以及根据所述差分数据电压信号和总差分DFE校正信号的和将所述多输入求和锁存器的差分输出驱动至两种可能输出状态当中的一种来生成数据判定结果,以及随后通过将所述多输入求和锁存器的差分输出在锁存状态下保持由所述采样时钟决定的时间长度来保持所述数据判定结果。(Precharging two or more sets of nodes to place differential outputs of a multi-input summing latch connected to the two or more sets of nodes in a precharged state, the two or more sets of nodes including a set of data signal nodes and a set of DFE correction nodes; generating a differential data voltage and a total differential DFE correction signal in response to a sampling clock; and driving the differential output of the multiple-input summing latch to one of two possible output states in accordance with the sum of the differential data voltage signal and the total differential DFE correction signal to generate a data decision result, and then holding the data decision result by holding the differential output of the multiple-input summing latch in a latched state for a length of time determined by the sampling clock.)
1. A method, comprising:
setting differential outputs of a multi-input summing latch to a precharged state by precharging two or more sets of nodes connected to the multi-input summing latch, the two or more sets of nodes including (i) a set of data signal nodes, and (ii) a set of decision feedback equalization correction nodes;
generating a differential data voltage signal by discharging the set of data signal nodes according to the received differential input voltage signal and generating an overall differential decision feedback equalization correction signal by discharging the set of decision feedback equalization correction nodes according to a sum of a plurality of decision feedback equalization correction factors in response to a sampling clock; and
driving the differential output of the multiple-input summing latch to one of two possible output states to generate a data decision result as a function of a sum of the differential data voltage signal and the total differential decision feedback equalization correction signal, and then holding the data decision result by holding the differential output of the multiple-input summing latch in a latched state for a length of time determined by the sampling clock.
2. The method of claim 1, further comprising generating a pair of differential speculative decision feedback equalization terms.
3. The method of claim 2, wherein each differential speculative decision feedback equalization term of the pair of differential speculative decision feedback equalization terms is applied to the sum of the differential data voltage signal and the total differential decision feedback equalization correction signal, respectively, to generate a pair of speculative data decision results, wherein generating the data decision result comprises: one of the pair of speculative data decision results is selected in response to completion of a previous data decision.
4. The method of claim 3, wherein each of the differential speculative decision feedback equalization terms is applied to the sum of the differential data voltage signal and the total differential decision feedback equalization correction signal via the differential data voltage signal.
5. The method of claim 3, wherein each of said differential speculative decision feedback equalization terms is applied to said sum of said differential data voltage signal and said total differential decision feedback equalization correction signal via said differential decision feedback equalization correction signal.
6. The method of claim 1, further comprising providing the data decision result to an output latch, wherein the output latch outputs the data decision result as an entire signaling interval.
7. The method of claim 1, wherein the differential data voltage signal and the total differential decision feedback equalization correction signal are buffered through one or more complementary metal oxide semiconductor inverters.
8. The method of claim 1, wherein the set of data signal nodes is connected to an output of a first amplification stage and the set of decision feedback equalization correction nodes is connected to a second amplification stage.
9. The method of claim 8, further comprising generating a plurality of currents in parallel through a plurality of differential transistor pairs in parallel with each other to apply a gain to the received differential input voltage signal via the first amplification processing stage, each differential transistor pair of the plurality of differential transistor pairs receiving the differential input voltage signal, wherein the applied gain represents a rate of discharge of the set of data signal nodes.
10. The method of claim 1, wherein the sum of the differential data voltage signal and the total differential decision feedback equalization correction signal is generated by providing like-polarity terms of the differential voltage signal and the total differential decision feedback equalization correction signal to respective ones of respective transistor pairs that are connected in parallel with each other, wherein the transistors within each transistor pair provide respective currents that are summed through a common node connecting the transistors of the transistor pairs.
11. An apparatus, comprising:
a discrete-time integration processing stage having two or more sets of nodes including (i) a set of data signal nodes, and (ii) a set of decision feedback equalization correction nodes, wherein the discrete-time integration processing stage is to:
setting differential outputs of a multi-input summing latch to a precharged state by precharging the two or more sets of nodes connected to the multi-input summing latch; and
generating a differential data voltage signal by discharging the set of data signal nodes in accordance with the received differential input voltage signal and generating an overall differential decision feedback equalization correction signal by discharging the set of decision feedback equalization correction nodes in accordance with a sum of a plurality of decision feedback equalization correction factors in response to a sampling clock,
wherein the multi-input summing latch is configured to drive the differential output of the multi-input summing latch to one of two possible output states to generate a data decision result based on a sum of the differential data voltage signal and the total differential decision feedback equalization correction signal, the multi-input summing latch further configured to subsequently hold the data decision result by holding the differential output of the multi-input summing latch in a latched state for a length of time determined by the sampling clock.
12. The apparatus of claim 11, wherein the discrete-time integration processing stage is further operative to generate a pair of differential speculative decision feedback equalization terms.
13. The apparatus of claim 12, wherein the discrete-time integration processing stage is to generate a pair of speculative data decision results by applying each of the pair of differential speculative decision feedback equalizations to the sum of the differential data voltage signal and the total differential decision feedback equalisation correction signal, respectively;
wherein the apparatus comprises a second multi-input summing latch for generating a respective speculative data decision result of the pair of speculative data decision results;
wherein the apparatus further comprises a multiplexer to select one of the pair of speculative data decision results as the data decision result in response to completion of a previous data decision.
14. The apparatus of claim 13, wherein each of the differential speculative decision feedback equalization terms is applied to the sum of the differential data voltage signal and the total differential decision feedback equalization correction signal via the differential data voltage signal.
15. The apparatus of claim 13, wherein each of the differential speculative decision feedback equalization terms is applied to the sum of the differential data voltage signal and the total differential decision feedback equalization correction signal via the differential decision feedback equalization correction signal.
16. The apparatus of claim 11, further comprising an output latch connected to an output of the multiple-input summing latch, wherein the output latch is to receive the data decision result from the multiple-input summing latch and output the data decision result as a data decision for an entire signaling interval.
17. The apparatus of claim 11, further comprising one or more complementary metal oxide semiconductor inverters to buffer the differential data voltage signal and the total differential decision feedback equalization correction signal.
18. The apparatus of claim 11, wherein the discrete-time integration processing stage comprises a first amplification processing stage having the set of data signal nodes and a second amplification processing stage having the set of decision feedback equalization correction nodes.
19. The apparatus of claim 18, the first amplification processing stage comprising a plurality of differential transistor pairs in parallel with each other, the differential transistor pairs to receive the received differential input voltage signal and responsively generate a plurality of currents in parallel through the plurality of differential transistor pairs in parallel with each other, wherein the applied gain is indicative of a rate of discharge of the set of data signal nodes.
20. The apparatus of claim 11, the multiple-input summing latch to sum the differential data voltage signal and the total differential decision feedback equalization correction signal by providing like-polarity terms of the differential voltage signal and the total differential decision feedback equalization correction signal to respective transistors of respective transistor pairs that are connected in parallel with each other, wherein the transistors in each transistor pair provide respective currents that are summed through a common node connecting the transistors in the transistor pair.
Background
Data communication between electronic devices such as integrated circuits within a system is typically constrained by the transmission behavior of interconnecting transmission media such as wires, printed circuit traces, or optical fibers. Transmission line effects, including attenuation, signal reflection, and frequency dependent propagation characteristics, can cause distortion of the transmitted signal, thus requiring corrective action.
Among other things, linear circuit correction measures include amplification of the received signal and frequency domain signal correction, for example, using Continuous Time Linear Equalization (CTLE).
Data correlation equalization is a technique well known in the art. Generally, such time-domain guided equalization methods focus on compensating for the effects of inter-symbol interference (ISI) of the received signal. Such ISI results from the effect of residual electrical effects of a previously transmitted signal remaining in the communication transmission medium on the amplitude or time of the current symbol interval. For example, the presence of one or more transmission line media with abnormal impedance may cause signal reflections. Wherein the signal will be partially reflected by the one or more anomalies as it propagates through the medium, and the reflected signal reaches the receiver with a delay in time in superposition with the directly transmitted signal that has not been reflected.
The transmitter side may employ digital correction measures such as pre-equalization via Finite Impulse Response (FIR) filtering, while the receiver side may employ methods including Feed Forward Equalization (FFE) and Decision Feedback Equalization (DFE).
In decision feedback equalization, a history of previously received data values is maintained by the receiver and then processed by the transmission line model to infer the expected effect of each such historical data value on the currently received signal. The transmission line model may be pre-calculated, derived from measurements, or generated by trial and error, and may cover the effects of one or more previous data intervals. The amount of correction predicted for the effect of the one or more previous data intervals is collectively referred to as the DFE correction amount, either explicitly combined with the received data signal prior to received sampling of the resulting corrected signal or implicitly combined by modifying the reference level used for comparison of the received data signal by the received data sampler or comparator by the DFE correction amount.
Disclosure of Invention
When the decision feedback equalization method is applied to a high-speed data receiver, a plurality of DFE correction terms corresponding to the influence of a certain previous reception unit interval need to be combined, and thus may become complicated. Furthermore, difficulties are further increased because such applications typically utilize multiple substantially parallel processing stages to pipeline a given received data bit or extend its available detection time. These difficulties may include: it is difficult to calculate DFE corrections in time and distribute them to the various parallel processing stages in time; when applying the correction amount, adverse side effects such as detector amplification effect or gain reduction occur.
Thus, in the methods and systems described herein: precharging two or more sets of nodes to place differential outputs of latches connected to the two or more sets of nodes in a precharged state, the two or more sets of nodes including (i) a set of data signal nodes and (ii) a set of DFE correction nodes; generating, in response to a sampling clock, a differential data voltage signal by discharging the set of data signal nodes in accordance with a received differential input voltage signal, and generating an overall differential DFE correction signal by discharging the set of DFE correction nodes in accordance with a sum of a plurality of DFE correction factors; and driving the differential output of the latch to one of two possible output states in accordance with the sum of the differential data voltage signal and the total differential DFE correction signal to generate a data decision result, and then holding the data decision result by holding the differential output of the latch in a latched state for a length of time determined by the sampling clock.
The methods and apparatus described herein enable efficient computation and distribution of DFE correction information in a high speed data receiver system, and application of DFE correction without significant impact on detector gain.
Drawings
Fig. 1 is an embodiment of one channel of a data receiver employing decision feedback equalization and multiple parallel processing stages.
Fig. 2 shows further details of one embodiment of combining multiple DFE corrections with multiple parallel processing stages.
Fig. 3 is a schematic diagram of a multiple input summing circuit.
Fig. 4 is a schematic diagram of a circuit that calculates multiple DFE correction terms and outputs summed correction results.
Fig. 5 is a schematic diagram of a NOR-based multiple-input summing latch according to some embodiments.
Fig. 6 shows another embodiment using the circuits of fig. 3, 4 and 5.
Fig. 7 shows another embodiment of a parallel processing stage.
Fig. 8 and 9 show two other embodiments of a parallel processing stage.
FIG. 10 illustrates one embodiment of a system employing the elements described herein.
FIG. 11 is a schematic diagram of a NAND based multiple input summing latch according to some embodiments.
Fig. 12 is a timing diagram of data determination across two signaling intervals in accordance with some embodiments.
Figures 13A and 13B are block diagrams of NOR-based and NAND-based multi-input summing latches according to some embodiments.
Fig. 14 is a block diagram of an architecture for extending retention time by connecting a NOR-based multiple-input summing latch with a NOR-based latch, according to some embodiments.
FIG. 15 is a flow chart of a method according to some embodiments.
Detailed Description
In recent years, the signaling rate of high speed communication systems has reached gigabits per second, such that a single transmission unit interval is measured in picoseconds. To meet such stringent timing requirements, circuit delays must be minimized by minimizing node capacitance and eliminating unnecessary processing elements. Even the settling time of the analog comparator, and other secondary circuit characteristics, may be an important factor in the available time budget.
For example, decision feedback equalization systems of prior art data communication receivers store historical values of one or more detected data values for a previously received unit interval, and apply DFE compensation values to the received signal after calculating them from these historical values to facilitate detection of the current unit interval. For purposes of illustration, in short, the calculation may include: multiplying the data value of each previous unit interval by a preset scaling factor; each of the scaling results, each representing the potential impact of a successive previous unit interval on the current received signal, is then summed to generate a composite DFE compensation value representing the cumulative predicted impact of all such previous unit intervals. In a typical receiver design, this DFE compensation value is combined with the current received signal input to produce a correction signal that more accurately represents the received data value, which may then be time sampled and amplitude sampled to obtain the detected received data value.
Those skilled in the art will appreciate that the DFE compensation values generated in accordance with the above-described method can only be fully determined after the completion of the detection of the data values in the previous unit interval. Thus, as the data rate increases, there must be some point at which the information needed to generate the first term of the DFE compensation value (i.e., the received data value of the previous unit interval) does not have sufficient time to apply to the detection of the next unit interval. Indeed, at the highest data rates used in current practice, this situation may occur for a number of previous unit intervals, since the detection time required for a single data value may correspond to the duration of a number of unit intervals. Accordingly, embodiments typically forego this "closed loop" DFE approach for one or more of the most recent unit intervals, and instead utilize an "open loop" or "guess" approach to generate one or more elements of such most recent unit interval DFE compensation values.
Fig. 1 shows an embodiment of a data receiver for a speculative DFE for a previous receive unit interval. This example includes receiver front ends (110 and 120) and a complete data path for one received data bit (130, 140, 150, 160). In a complete receiver implementation, the single front end is also typically shared with the data path of the other data bits. In some embodiments, DFE computation subsystem 170 and clock data recovery subsystem 180 may be shared between multiple data paths, or may be shared exclusively by a particular data path.
In the illustrated, non-limiting example, four receive line signals are taken from the communication channel, which may represent two pairs of differential signals, or a four-wire data stream carrying three data bits encoded in orthogonal differential vector signaling codes (ODVS) as described in Cronie. As described in Holden 1, the continuous-time linear equalizer 110 frequency-dependently amplifies the received line signal, and the multiple-input comparator (MIC)120 optionally decouples ODVS encoding by combining the amplified line signals and obtains a detected data signal. In differential reception embodiments, each such MIC has two valid inputs and functions as a differential line receiver, whereas in single-ended receiver embodiments, the receive operation is performed directly on the respective line signals, avoiding the use of any MIC function.
One such embodiment operates to transmit a unit interval of approximately 35 picoseconds, corresponding to a data rate of approximately 28 gigabaud (GBd). To support such data rates, the exemplary receiver provides two parallel processing stages 130 and 140 in each received signal data path, each of which detects data received from a pair of differential lines or ODVS subchannels in alternating unit intervals. At the data rate, the interleaved parallel processors allow each processing stage to capture and detect each received data bit for two unit intervals or 70 picoseconds.
Transmission line characteristics associated with the communication system indicate that Decision Feedback Equalization (DFE) may need to span up to ten receive unit intervals. The high data rate makes it extremely difficult to achieve timely transmission of the associated first DFE correction term for the previously received data value in reality. Thus, the example of fig. 1 employs a "speculative" or "open-loop" DFE processing stage in which each detector first captures the result under the assumption that the previous data value was "1" or "0", respectively, and, after determining the previous data value, selects the correct result for use.
The operation of each parallel processing stage is the same. For 130, integrating sample processing stages 131 and 133 simultaneously capture the combined result of the received signal amplitude and DFE correction amount at the rising edge of sampling clock Clk 000. In this example employing a single speculative DFE element, the DFE correction amounts applied to 131 and 133 differ only by their temporally closest terms, corresponding to the speculative correction amounts assumed by the previous data bit being a "1" or a "0", respectively. The interleaver 135 obtains the value of the previous data bit after it has been detected by another processing stage 140 and directs the appropriate speculative detection result 132 or 134 to the data output 138 of the processing stage 130.
The operation of parallel processing stage 140 is the same except that sampling is done at the rising edge of the sampling clock Clk180 (the next receive unit interval of Clk 000) and multiplexer 145 then selects one of 142 and 144 as data output 148 using the value of the previous data bit detected by processing stage 130. The high-speed multiplexer 150 then combines the alternating unit interval received values 138 and 148 into a full-speed received data stream 155. In other embodiments, the received values may also be maintained as a parallel low-speed data stream.
The DFE compensation subsystem 170 calculates the total DFE correction amount DFEl, DFE2, DFE3, DFE4 for the two processing stages by maintaining a history of received data values. In other embodiments, the DFE correction amount may also be calculated separately for each processing stage, or indeed for each sampler, although the invention is not limited thereto. Wherein each term H of the calculated DFE correction amountNBoth derived from historical data values X _ N received in the Nth previous reception unit interval and a scaling factor K derived from a signal propagation model of the transmission mediumNThe product of (a). For computational simplicity, each term of the total differential DFE correction signal is treated as a zero-based differential correction amount relative to the sampler normal detection threshold. Computationally, this means that data "1" corresponds to the "+ 1" multiplier for a given scale factor, while data "0" corresponds to the "-1" multiplier for that same scale factor.
In at least one embodiment, the resulting DFE correction amounts are represented as analog differential signals that are arranged such that when the two signals in the pair are interchanged, the correction term corresponding to data "1" becomes the correction term corresponding to data "0". The DFE correction amount may also itself or subsequently be combined with a preset, adjustable or fixed offset or bias level, which may in some embodiments be individually targeted to a particular sampler to enable compensation for device variations. Thus, in one such embodiment, for example, sampler 131 and sampler 141 may differ from each other in the sum of all DFE correction amounts and preset offset levels used to compensate for signal amplitude and device variation, respectively, of these two circuit elements.
In the first example, the time T ═ 0 represents the current reception unit interval of the processing stage 140, and this reception finally enables detection of the data value X (T ═ 0). For convenience of description, the data value is hereinafter abbreviated as X _ 0. Similarly, T ═ 1 represents the unit interval preceding the above-described reception time, which is processed by 130 to generate the data value X (T ═ 1), hereinafter referred to as X _1 (the chronological description which indicates sequential processing within a single data path instance should not be confused with the "D0, D1, D2 … …" commonly used when describing data bits received simultaneously within multiple data path instances.
H1～H10Representing different components of the total DFE correction amount described above. In the following examples, the received data is binary data, and thus each component is determined by the product of a coefficient or correction factor K and either +1 (for data "1") or-1 (for data "0"). In practical implementations, such coefficients depend on network propagation and detection characteristics and may vary from line to line, differential pair, ODVS subchannel, and/or physical sampler instance to physical sampler instance.
DFE1＝(K1×1)+(K2×X_2)+....+(K10× X _10) +
DFE2＝(K1×-1)+(K2×X_2)+....+(K10× X _10) + C2 formula 2
DFE3＝(K1×1)+(K2×X_2)+....+(K10× X _10) +
DFE4＝(K1×-1)+(K2×X_2)+....+(K10× X _10) +
For example, the only difference between the total correction amount DFE3 and DFE4 applied to 141 and 143, respectively, within processing stage 140 is the first DFE correction term (H) corresponding to the previous unit interval (H)1) Is marked withSign, and any adjustment or calibration differences contained in the bias constants C1 and C2. As a loop of the speculative DFE processing of this first term, the first correction term of
Fig. 2 is a more detailed diagram of a multi-stage receiver implementation employing a speculative DFE. Consistent with the above example, the same received data bits sampled at alternating receive unit intervals are detected by the same processing stages 230 and 240.
For many common amplifier topologies, as is known in the art, the additional addition of a signal input will result in a reduction in signal gain, which reduction ratio for N-input amplifiers is typicallyThus, when nine or more DFE correction terms are directly combined with the received signal input within a single amplifier, the amount of gain that can be applied to the received signal will be greatly reduced. To minimize such a reduction in signal gain, the required summation operation is divided by three different circuits.
Where each non-speculative DFE correction term is calculated 248 as described above, the summation of the outputs 249 is shown in equation 5:
Hsum＝(K2×D2)+....+(K10×D10)
Fig. 4 is a schematic diagram of one embodiment of a circuit for performing this calculation and the first summation operation, which consists of nine
At 410,
The remaining eight identical processing stages 420 … … 490 perform similar calculations as 410 using factors K3-K10 and historical data values X _3 … … X _10, respectively. Since all processing stages run in parallel on the output nodes Σ H + and Σ H-, the resulting differential output represents the summation result of all nine calculation terms.
In FIG. 2, the DFE correction factors (K factors) required for the calculation of
The resulting DFE sum correction 249 serves as an input to a second summing circuit, shown as samplers 242 and 244. Fig. 3 circuit 330 illustrates a suitable sampler implementation in which the differential inputs Vdata and Σ H are summed at the rising edge of the sampling clock Ck.
The results captured by the samplers 242 and 244 represent the speculative results under the assumption that the data value of the previous unit interval is "1" (corresponding to 242) or "0" (corresponding to 244). Therefore, the signals input to these samplers must be corrected by the first DFE correction term H1Are offset by suitably different values.
To generate such values, the received input signal 125 is processed by a third summing circuit, shown in fig. 2 as amplifiers 241 and 243, each for adding a speculative DFE correction factor K1The two correction factors differ only in the sign of the resulting correction. Where DAC 250 is used to provide a correction factor 255. The circuit 310 shown in FIG. 3 is one suitable for use in FIG. 2241 and 243 are schematic diagrams of suitable embodiments. The two circuit examples differ only in the way the control signal X _0 is set: in 241, X _0 is hardwired to a logic "1"; at 243, X _0 is hardwired to a logic "0". The signal gains of the different input elements of 310 may be modified by adjusting the current contributions of the different signal paths (e.g., differential pair 313/314 and differential pair 320/321) to the summation result. In one embodiment, the adjustment is achieved by scaling the relative sizes of the transistors. In another embodiment, the adjustment is achieved by connecting multiple instances of the same transistor element in parallel. Such an implementation employing multiple instances of identical transistor elements is illustrated in fig. 10, where the gain of the input signal Vin is made 6 by providing the input signal Vin to six mutually parallel identical current-mode output samplers, while the speculative DFE components + H1 and-H1 are provided to three mutually parallel identical current-mode output samplers, and each of the known DFE factors X2H2 … … X10H10 is connected to a respective identical current-mode output sampler. Since each identical current-mode output sampler provides an equal amount of current, a plurality of such samplers connected in parallel with each other can provide a current-mode summation result on a common output node.
As described above, the speculative detection result is analyzed by selecting a valid sampling result by the multiplexer 245 controlled by the data value obtained in the previous unit interval X _ 1. In some embodiments, a full-speed serial stream may be generated in data historian unit 210 by adding multiplexer 270. In an alternative embodiment, the data streams from different processing stages may also be operated on directly, without being converted to a single stream by a multiplexing operation.
In one embodiment, the data value X _1 detected by the processing stage 230 during the previous unit interval is obtained directly from the processing stage 230 for minimizing circuit propagation delay, rather than from the data historian unit 210. Likewise, the data value X _2 detected by the processing stage 240 in the previous unit interval is also available to it in that processing stage and generates H2The DFE correction term. As an optionLatch 246 is illustrated as capturing and holding an output data value for H by 2482Thereby increasing a time margin when the DFE sum correction amount 249 is generated. In some embodiments, similar pipelined latches are also used to increase the time margin of the X _1 data value that controls the select operation of multiplexer 245.
Hereinafter, for purposes of description, the signal VA +/VA-may correspond to a differential data voltage signal generated from at least the received differential input voltage signal Vin (shown as Vdata +/Vdata in FIG. 3), while VB +/VB-corresponds to a total differential DFE correction signal formed from the summation results of the DFE correction factor H2 … … H10 (shown as Σ H + and Σ H-) in FIGS. 3 and 4. Some embodiments may not use speculative DFE terms + H1 and-H1, while alternative embodiments may use speculative DFEs in various arrangements as described below.
In some embodiments, as shown in fig. 6, an apparatus includes a discrete-time integration processing stage. In fig. 6, the discrete-time integration processing stage includes
In some embodiments, as shown in fig. 6, the discrete-time integration processing stage is also used to generate a pair of differential speculative DFE terms K1+ and K1-. In such embodiments, the discrete integration processing stage may generate a pair of speculative data decision results by applying each differential speculative DFE term of the pair of differential speculative DFE terms to a result of summing the differential data voltage signal and a total differential DFE correction signal, respectively. In fig. 6, the speculative term is applied to the received differential input voltage signal and the speculative data decision result is received by two
In some embodiments, second latch 635 (and also latch 645 in speculative DFE embodiments) is configured to receive the data decision result and provide the data decision result as a data decision output for the entire signaling interval.
In some embodiments, the differential data voltage signal and the total differential DFE correction signal are buffered by one or more CMOS inverters.
In some embodiments, the discrete-time integration processing stage includes a first amplification processing stage including the set of data signal nodes, and a second amplification processing stage including the set of DFE correction nodes. In fig. 6, the first amplification processing stage may include
Fig. 6 shows an alternative embodiment functionally equivalent to the processing stage 240 of fig. 2, which contains multiple-
VA++VB+
VA-+VB-
Q+
Q-
1
1
0 (precharge state)
0 (precharge state)
1
0
0
1
0
1
1
0
0
0
Latch and storage
Latch and storage
Table I: NOR-based multiple-input summing latch
VA++VB+
VA-+VB-
Q+
Q-
1
1
Latch and storage
Latch and
1
0
0
1
0
1
1
0
0
0
1 (Pre-charge state)
1 (Pre-charge state)
Table II: NAND-based multiple-input summing latch
In the NOR-based multiple-input summing latch of FIG. 5, (VA) since the set of nodes holding VA +/-and VB +/-are precharged++VB+) And (VA)_The value of + VB-) is initially "1", thereby keeping the differential output Q +/Q-in state "00". Although the precharge and latch states of the NOR-based and NAND-based multi-input summing latches are opposite to each other, the outputs of the data decision states "01" and "10" are identical. Although there are four possible states in the table above, it should be noted that the two input combinations of decision states "01" and "10" correspond to a summation result with a faster rate of fall. This is because the integrators in
Fig. 12 is a timing diagram of two unit intervals in tandem for a circuit employing a NOR-based multiple-input summing latch as shown in fig. 5. As shown, a set of data signal nodes holding VA +/-and a set of DFE correction signal nodes holding VB +/-are in a precharged state, and the output Q +/Q-of the NOR-based multiple
In some embodiments, cross-coupled NOR-based prior art set/reset latches 635 and 645 are provided downstream of the multi-input summing
In some embodiments, each one differential input of the multi-input summing
In an alternative embodiment, the MOSFET structure of fig. 3 and 4 may be reversed and a pair of pre-discharge nodes may be charged using a current source. In such embodiments, the node is first discharged to state "00" and then both nodes can begin to charge under the action of the current source in response to the sampling clock until state "11" is reached. In such embodiments, the differential data voltage and the total DFE correction signal may be applied directly to the NAND-based multi-input summing latch, or through a CMOS inverter to the NOR-based multi-input summing latch, similar to that described above.
It is noted that various configurations of discrete integrators 310 and 330 may be used and may be coupled to various types of multiple-input summing latches through different configurations of CMOS inverters. For example, in fig. 6, CMOS inverters (not shown) may be incorporated at the inputs of the multiple-
Although the above examples do not describe the use of speculative DFE terms H _ l +/it is noted that these speculative DFE terms may be incorporated into the structure shown in figure 3 and any of figures 6-10. That is, the speculative DFE terms may be introduced into various different processing stages while the operation of the multiple-input summing latch and any downstream latching devices remains unchanged. For example, as shown in FIG. 8, the speculative DFE term may be applied to the received differential input voltage Vin and may be part of VA +/VA-; alternatively, the speculative DFE term can be incorporated into VB +/VB-by applying the correction factor to the historical DFE, as in the configuration shown in FIG. 9.
The function of the clocked samplers is performed by
Fig. 7 shows the whole process of the above embodiment. Wherein each DFE correction factor HN(in this example, N ═ 1 … … 10) was determined by applying the correction factor KNMultiplied by the corresponding historical data value X _ N. Thus, as shown, taking DAC 721 as an example, the DAC is used to generate correction factor K2 and generate DFE correction term H2 for sampler 730 by multiplying 711 it by historical data value X _ 2. As shown, the samplers 730 and 760 are used to detect two speculative assumptions, that is, the previous unit interval data X _1 is "1" (corresponding to 730) and "0" (corresponding to 760), respectively. For the sake of generality, 730 and 760 are shown as generating input correction terms that differ only by the assumed value of the H1 correction term, respectively. As shown, the values from DACs 721-729 may be shared between 730 and 760, but each sampler 730 and 760 uses its own multiplier, respectively. As shown, sampler 730 includes a set of multipliers 710-719, and sampler 760 includes multipliers 750-759. As shown in fig. 4, each multiplier may be an arrangement of multiple transistors. Consistent with the previous example, the selection of valid speculative detection values is shown with multiplexer 770.
Fig. 8 and 9 show two other embodiments similar to the embodiment of fig. 7, the summing and integrating sampling operations of which differ to highlight different operational aspects of the embodiment.
In fig. 8, all non-speculative DFE correction terms are summed 820 and the resulting total correction is then combined with the sum of the input signal Vin and the speculative DFE correction 810 within the multiple-input summing latch 840. In addition, a similar combining operation is also performed between total correction 820 and the sum of Vin and complementary speculative DFE correction 830 within multiple-input summing latch 870. The multiple-input summing latches 840 and 870 perform the following functions: summing positive and negative differential input signals, respectively (e.g., Vin plus speculative DFE correction plus DFE sum correction); the more negative of the two sums is obtained. The differential outputs of 840 and 870 are then latched with existing latches 850 and 880.
Multiplexer 860 selects one of the two speculative results based on the actual received previous data value, as described above. By sharing the sum of the non-speculative corrections among speculative samplers, circuit complexity may be reduced, keeping samplers 810 and 830 with fewer inputs, and applying greater gain to these inputs. In one embodiment, 810 and 830 provide a 6-fold gain to Vin and a 3-fold gain to the term of speculative H1.
All the illustrated integrate-and-hold samplers use the same basic design as described above. In one embodiment, 810 and 830 follow the design of 330 in FIG. 3, while 820 follows the design of FIG. 4. Multiple input summing latch implementations 840 and 870 are shown in fig. 5, while downstream latches 850 and 880 are shown in the fig. 14 configuration, using prior art cross-coupled NOR gate set/reset latches. As mentioned above, as an alternative, an unbuffered CMOS inverter may be inserted at each differential input of the two input summing latch, and accordingly, circuit substitution may be made with the substitution circuit shown in fig. 11.
Fig. 9 shows another variant of the design of fig. 7 and 8. In fig. 9, all the speculative and non-speculative DFE correction terms are summed separately, where 920 is used for the sum of the speculative term with X _1 ═ 1 "and 930 is used for the sum of the speculative term with X _1 ═ 0". These summed corrections and amplified input signal 910 are combined by two input summing latches 940 (corresponding to a guess value of "1") and 970 (corresponding to a guess value of "0") to generate a threshold comparison result. These results are then latched by 950 and 980 for multiplexer 960 to select the correct speculative result. As such, the gain may be increased by having only one input to the integrating sample processing stage 910. In one embodiment, the processing stage achieves a 9 times Vin gain by employing nine differential transistor pairs in parallel in Vin. In another embodiment, a 6-fold gain of the speculative DFE correction term is achieved in a similar manner.
Consistent with the above example, an unbuffered CMOS inverter may be inserted at each differential input of the two input summing latch, and accordingly, the alternative circuit 1100 shown in fig. 11 may be substituted for the circuit of fig. 5.
The fig. 7, 8, 9 embodiments have the common advantage that only a single clocked sampling operation need be performed substantially simultaneously for all entries. This is of great significance in applications where time offsets between signals cause problems.
Fig. 10 illustrates an embodiment of a system employing the above-described elements. Where parallel differential pair elements for gain adjustment between signal paths are explicitly shown, the summing operations, for example, identified in fig. 8 as elements 810, 820, 830, are shown in data processing flow representation and each individual summing operation is shown as a summing bus. Each of the summing operations includes the same number (nine in this non-limiting example) of differential pair elements to reduce the time offset between different summing results by consistent loading conditions with each other. Since the result of a two-input summing latch (e.g., as shown in fig. 5) is determined by the one of the summing results (sum of a + and B +) and (sum of a-and B-) that falls first below the other, it is advantageous to reduce its input bias.
FIG. 15 is a flow diagram of a
In some embodiments, the method further comprises: generating a pair of differential speculative DFE terms: + H1 and-H1. In such embodiments, each differential speculative DFE term of the pair of differential speculative DFE terms may be applied to a result of a summation of the differential data voltage signal and the total differential DFE correction signal, respectively, to generate a pair of speculative data decision results. In such embodiments, generating the data determination comprises: one of the pair of speculative data decision results is selected in response to a previous data decision.
In some embodiments, the differential speculative DFE terms are applied to the summation result by the differential data voltage signal, while in alternative embodiments, the differential speculative DFE terms may also be applied to the summation result by the differential DFE correction signal. Fig. 6-10 illustrate various structures for applying speculative DFE terms.
In some embodiments, the method further comprises: the data decision result is provided to a second latch (e.g.,
In some embodiments, the set of data signal nodes is coupled to the output of the first amplification processing stage 241/243, wherein the set of DFE correction nodes is coupled to the second
In some embodiments, the summed result of the differential data voltage signal and the total differential DFE correction signal is generated by providing like-polarity terms of the differential voltage signal and the total differential DFE correction signal to respective transistors of respective transistor pairs connected in parallel with each other, the transistors within each transistor pair providing respective currents that are summed via a common node connecting the transistors within the transistor pair. By connecting the differential data voltage signals and the total differential DFE correction signal to parallel transistors grouped by like polarity terms, VA + is added to VB + and VA-is added to VB + as shown in fig. 5.
For convenience of description, the above examples suggest that the setting or adjustment of the control signal or level is accomplished by a DAC. The DAC may employ an R-2R resistor ladder, a single resistor chain, binary weighted resistors or capacitor summation, or other methods known in the art. Other embodiments may also employ other methods known in the art to generate settable or adjustable output signal levels including settable current sources, adjustable resistive or capacitive signal output limits, and selectively enable a number of parallel drive elements to incrementally affect the output signal levels, respectively.
To clearly illustrate all of the elements of the above embodiments, two substantially parallel processing stages are described above that each execute a single speculative DFE processing stage. However, the invention is not so limited and the elements described are equally applicable to embodiments employing more or fewer parallel processing stages. Likewise, the present invention is not limited to a single speculative DFE processing stage, and the elements are equally applicable to implementations that employ additional speculative DFE processing stages or that do not employ speculative or open-loop DFEs at all.
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