阅读说明：本技术 半导体集成电路装置及振荡电路装置 (Semiconductor integrated circuit device and oscillation circuit device ) 是由 浦川刚 于 2020-08-18 设计创作，主要内容包括：实施方式提供一种能够抑制专有面积的半导体集成电路装置及振荡电路装置。本实施方式的半导体集成电路装置具备电感器元件,所述电感器元件具有第1电感器部分、第2电感器部分及第3电感器部分。所述第1电感器部分设置在第1配线层的第1区域,具有第1端部,且包含单层绕线线圈。所述第2电感器部分设置在与所述第1区域不同的所述第1配线层的第2区域,具有第2端部,且包含单层绕线线圈。所述第3电感器部分设置在与所述第1配线层在第1方向上相隔配置的第2配线层,具有第3端部及第4端部。所述第3电感器部分的所述第3端部与所述第1电感器部分的所述第1端部电连接,所述第3电感器部分的所述第4端部与所述第2电感器部分的所述第2端部电连接。所述第3电感器部分还具备以对所述电感器元件供给电力的方式设置的第5端部。(Embodiments provide a semiconductor integrated circuit device and an oscillation circuit device capable of suppressing a dedicated area. The semiconductor integrated circuit device of the present embodiment includes an inductor element having a1 st inductor portion, a2 nd inductor portion, and a 3 rd inductor portion. The 1 st inductor section is disposed in a1 st area of the 1 st wiring layer, has a1 st end portion, and includes a single-layer winding coil. The 2 nd inductor part is disposed at a2 nd area of the 1 st wiring layer different from the 1 st area, has a2 nd end portion, and includes a single-layer winding coil. The 3 rd inductor section is provided in a2 nd wiring layer arranged apart from the 1 st wiring layer in a1 st direction, and has a 3 rd end section and a 4 th end section. The 3 rd end of the 3 rd inductor portion is electrically connected with the 1 st end of the 1 st inductor portion, and the 4 th end of the 3 rd inductor portion is electrically connected with the 2 nd end of the 2 nd inductor portion. The 3 rd inductor part further includes a 5 th end part provided to supply power to the inductor element.)

1. A semiconductor integrated circuit device, characterized in that: an inductor element having a1 st inductor portion, a2 nd inductor portion, and a 3 rd inductor portion,

the 1 st inductor section is disposed in the 1 st area of the 1 st wiring layer, has a1 st end portion, and includes a single-layer wound coil,

the 2 nd inductor section is provided in a2 nd area of the 1 st wiring layer different from the 1 st area, has a2 nd end portion, and includes a single-layer winding coil,

the 3 rd inductor part is provided in a2 nd wiring layer arranged at a distance from the 1 st wiring layer in a1 st direction and has a 3 rd end part and a 4 th end part,

the 3 rd end of the 3 rd inductor portion is electrically connected with the 1 st end of the 1 st inductor portion, the 4 th end of the 3 rd inductor portion is electrically connected with the 2 nd end of the 2 nd inductor portion, and

the 3 rd inductor part further includes a 5 th end portion capable of supplying power to the inductor element.

2. The semiconductor integrated circuit device according to claim 1, wherein: the 3 rd inductor part in the 3 rd region of the 2 nd wiring layer corresponding to the 1 st region of the 1 st wiring layer is arranged in a manner of overlapping with at least one part of the 1 st inductor part when viewed from the 1 st direction, and

the 3 rd inductor section in the 4 th region of the 2 nd wiring layer corresponding to the 2 nd region of the 1 st wiring layer is provided so as to overlap at least a part of the 2 nd inductor section when viewed from the 1 st direction.

3. The semiconductor integrated circuit device according to claim 1 or 2, further comprising:

a1 st via hole provided so as to extend in the 1 st direction, electrically connecting the 3 rd end portion of the 3 rd inductor portion and the 1 st end portion of the 1 st inductor portion; and

a2 nd via hole provided to extend in the 1 st direction and electrically connecting the 4 th end portion of the 3 rd inductor portion and the 2 nd end portion of the 2 nd inductor portion.

4. The semiconductor integrated circuit device according to claim 1 or 2, wherein: the 1 st inductor portion also has a 6 th end,

the 2 nd inductor portion also has a 7 th end,

the inductor element also has a 4 th inductor portion and a 5 th inductor portion,

the 4 th inductor section is provided at least one of an outer periphery of at least a part of the 2 nd inductor section and an outer periphery of at least a part of the 3 rd inductor section in a 4 th region of the 2 nd wiring layer corresponding to the 2 nd region of the 1 st wiring layer when viewed from the 1 st direction, and has an 8 th end portion,

the 5 th inductor section is provided on at least one of an outer periphery of at least a part of the 1 st inductor section and an outer periphery of at least a part of the 3 rd inductor section in a 3 rd region of the 2 nd wiring layer corresponding to the 1 st region of the 1 st wiring layer when viewed from the 1 st direction, has a 9 th end portion, and

the 8 th end of the 4 th inductor portion is electrically connected with the 6 th end of the 1 st inductor portion, and the 9 th end of the 5 th inductor portion is electrically connected with the 7 th end of the 2 nd inductor portion.

5. The semiconductor integrated circuit device according to claim 4, wherein: the 4 th inductor section has:

a 6 th inductor section provided in an outer periphery of at least a part of the 2 nd inductor section in the 1 st wiring layer;

a 7 th inductor section provided in the 2 nd wiring layer at an outer periphery of at least a part of the 3 rd inductor section in the 4 th region; and

a 3 rd via hole provided to extend in the 1 st direction, electrically connecting the 6 th inductor portion and the 7 th inductor portion;

the 5 th inductor section has:

an 8 th inductor section provided in an outer periphery of at least a part of the 1 st inductor section in the 1 st wiring layer;

a 9 th inductor section provided in the 2 nd wiring layer at an outer periphery of at least a part of the 3 rd inductor section in the 3 rd region; and

and a 4 th via hole extending in the 1 st direction and electrically connecting the 8 th inductor part and the 9 th inductor part.

6. The semiconductor integrated circuit device according to claim 1 or 2, wherein: the 1 st inductor part and the 2 nd inductor part are symmetrically arranged with respect to an imaginary central line between the 1 st inductor part and the 2 nd inductor part when viewed from the 1 st direction, and

the 3 rd inductor part is disposed symmetrically with respect to the center line when viewed from the 1 st direction.

7. The semiconductor integrated circuit device according to claim 6, wherein: the 5 th end is disposed in the 3 rd inductor portion and on the centerline.

8. The semiconductor integrated circuit device according to claim 1 or 2, wherein: the curvature of the 1 st inductor part on the side close to the 2 nd inductor part is larger than that of the 1 st inductor part on the side far from the 2 nd inductor part, and

the curvature of the 2 nd inductor part on the side closer to the 1 st inductor part is larger than the curvature of the 2 nd inductor part on the side farther from the 1 st inductor part.

9. The semiconductor integrated circuit device according to claim 1 or 2, wherein: the line width of the 1 st inductor part on the side close to the 2 nd inductor part is thinner than the line width of the 1 st inductor part on the side far from the 2 nd inductor part, and

the line width of the 2 nd inductor part on the side close to the 1 st inductor part is thinner than the line width of the 2 nd inductor part on the side far from the 1 st inductor part.

10. The semiconductor integrated circuit device according to claim 1 or 2, wherein: when a current flows through the inductor element, a direction of the current of the 1 st inductor segment on a side close to the 2 nd inductor segment is opposite to a direction of the current of the 2 nd inductor segment on a side close to the 1 st inductor segment.

11. The semiconductor integrated circuit device according to claim 1 or 2, wherein: the 1 st inductor portion and the 2 nd inductor portion are disposed symmetrically with respect to an imaginary line between the 1 st inductor portion and the 2 nd inductor portion when viewed from the 1 st direction.

12. An oscillation circuit device, comprising:

the semiconductor integrated circuit device according to any one of claims 1 to 11;

a power supply section that supplies power to the inductor element via the 5 th end portion of the 3 rd inductor portion; and

a capacitor having a 10 th end and an 11 th end;

the 1 st inductor portion is further provided with a 12 th end portion,

the 2 nd inductor part further has a 13 th end part

The 10 th end of the capacitor is electrically connected with the 12 th end of the 1 st inductor portion, and the 11 th end of the capacitor is electrically connected with the 13 th end of the 2 nd inductor portion.

Technical Field

Embodiments of the present invention relate to a semiconductor integrated circuit device and an oscillation circuit device.

Background

As the oscillation circuit, an LC (inductor-capacitor) type oscillation circuit using LC resonance, a ring type oscillation circuit using an inverter circuit, or the like may be used. It is known that an LC type oscillation circuit has a low phase noise characteristic and low power consumption in a high frequency band, as compared with a ring type oscillation circuit.

In an LC type oscillation circuit including an inductor, a circuit area may be increased due to a large exclusive area of the inductor.

Disclosure of Invention

Embodiments provide a semiconductor integrated circuit device and an oscillation circuit device capable of suppressing an increase in a footprint.

The semiconductor integrated circuit device of the present embodiment includes an inductor element having a1 st inductor portion, a2 nd inductor portion, and a 3 rd inductor portion. The 1 st inductor section is disposed in a1 st area of the 1 st wiring layer, has a1 st end portion, and includes a single-layer winding coil. The 2 nd inductor part is disposed at a2 nd area of the 1 st wiring layer different from the 1 st area, has a2 nd end portion, and includes a single-layer winding coil. The 3 rd inductor section is provided in a2 nd wiring layer arranged apart from the 1 st wiring layer in a1 st direction, and has a 3 rd end section and a 4 th end section. The 3 rd end of the 3 rd inductor portion is electrically connected with the 1 st end of the 1 st inductor portion, and the 4 th end of the 3 rd inductor portion is electrically connected with the 2 nd end of the 2 nd inductor portion. The 3 rd inductor part further includes a 5 th end part provided to supply power to the inductor element.

Drawings

Fig. 1 is a circuit diagram showing a configuration of an oscillation circuit device according to embodiment 1.

Fig. 2 is a perspective view showing an inductor element according to embodiment 1.

Fig. 3 is a plan view showing the structure of the inductor element according to embodiment 1.

Fig. 4(a) and (B) are plan views showing the inductor element of fig. 3 in a divided manner.

Fig. 5 is a graph showing an example of a relationship between a Q value (Quality Factor) and a specific area.

Fig. 6 is a circuit diagram showing a configuration of an oscillation circuit device according to variation 1.

Fig. 7 is a plan view showing the structure of an inductor element according to variation 2.

Fig. 8 is a plan view showing the structure of the inductor element according to embodiment 2.

Fig. 9(a) and (B) are plan views showing the inductor element of fig. 8 in a divided manner.

FIG. 10 is a graph showing an example of the relationship between the Q value and the exclusive area.

Fig. 11 is a plan view showing a configuration of an inductor element according to a modification of embodiment 2.

Detailed Description

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present embodiment does not limit the present invention. In the following embodiments, the vertical direction of the semiconductor substrate means a relative direction in a case where the surface on which the semiconductor element is provided is directed upward, and may be different from a vertical direction along the gravitational acceleration. The drawings are schematic or conceptual views, and the ratios and the like of the respective portions are not necessarily the same as in reality. In the description and drawings, the same elements as those described above with respect to the appearing drawings are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(embodiment 1)

The configuration of the oscillation circuit device 1 according to embodiment 1 will be described with reference to fig. 1. Fig. 1 is a circuit diagram showing a configuration of an oscillation circuit device 1 according to embodiment 1. The oscillation circuit device 1 generates a signal of a predetermined frequency by LC resonance.

The oscillation circuit device 1 includes a semiconductor integrated circuit device 2, a capacitor 20, a power supply connection portion 30, a current source 40, a semiconductor switch 50, a semiconductor switch 60, an output terminal 70, and an output terminal 80. The oscillation circuit device 1 is configured as a bilaterally symmetric differential circuit. The semiconductor integrated circuit device 2 includes an inductor element 10 and an end portion 10 t.

The semiconductor integrated circuit device 2 is formed on a substrate provided with a plurality of wiring layers (multilayer wiring layers). The substrate is, for example, a semiconductor substrate. The multilayer wiring layer may be a wiring layer having an interlayer insulating film.

The inductor element 10 constitutes a part of an LC type oscillation circuit together with the capacitor 20. The inductor element 10 has one end (1 st end) connected to the node N1 via the wiring L1 and the other end (2 nd end) connected to the node N2 via the wiring L2.

The end portion 10t is provided so as to supply power to the inductor element 10 when a current or a voltage is applied thereto. The end portion 10t is connected to a wiring L3. The end portion 10t is a terminal such as a center tap. The inductor element 10 may have an end portion 10 t.

The inductor element 10 and the end portion 10t will be described in detail below with reference to fig. 2, 3, 4(a) and 4 (B).

The capacitor 20 has one end (1 st end) electrically connected to one end of the inductor element 10 and the other end (2 nd end) electrically connected to the other end of the inductor element 10. The capacitor 20 has one end connected to the node N1 and the other end connected to the node N2. The capacitance of the capacitor 20 is variable.

The power supply connection portion 30 as a power supply portion supplies power from a power supply (not shown) to the inductor element 10 via the end portion 10 t. The power supply connection portion 30 applies a voltage Vdd, for example.

The current source 40 is disposed between the power supply connection portion 30 and the end portion 10 t. The current source 40 is, for example, a constant current source.

The semiconductor switch 50 is a Transistor such as a Field Effect Transistor (FET), for example. The semiconductor switch 50 has a gate connected to the node N4, a drain connected to the node N3, and a source connected to the node N5. The node N3 is connected to the node N1, the node N4 is connected to the node N2, and the node N5 is connected to a line at ground potential.

The semiconductor switch 60 is a transistor such as an FET, for example. The semiconductor switch 60 has a gate connected to the node N3, a drain connected to the node N4, and a source connected to the node N5.

The output terminal 70 is connected to the drain of the semiconductor switch 50 and the gate of the semiconductor switch 60. The output terminal 70 is connected to the node N3. The output terminal 70 is, for example, a signal output terminal of the oscillation circuit device 1.

The output terminal 80 is connected to the drain of the semiconductor switch 60 and the gate of the semiconductor switch 50. Output terminal 80 is connected to node N4. The output terminal 80 is, for example, a signal output terminal of the oscillation circuit device 1.

The output terminals 70 and 80 output anti-phase signals (differential signals).

Fig. 2 is a perspective view showing the structure of the inductor element 10 according to embodiment 1. The end portion 10t is omitted in fig. 2. Arrow a shows an example of the direction of current flow.

The semiconductor integrated circuit device 2 (oscillation circuit device 1) is formed on a substrate having a plurality of wiring layers. That is, the semiconductor integrated circuit device 2 (oscillation circuit device 1) further includes a substrate.

Inductor element 10 includes inductor portion 11, inductor portion 12, inductor portion 13, via portion V1, and via portion V2.

The inductor section 11 is disposed at a region AR1 of the wiring layer WL 1. The inductor portion 11 is provided, for example, so that a part thereof becomes a single-layer wound coil (single-turn coil) formed of polygonal or annular wiring. The inductor portion 11 has one end (1 st end) 111 and the other end (2 nd end) 112. In the example shown in fig. 2, one end 111 of inductor portion 11 is connected to via V1, and the other end 112 of inductor portion 11 is connected to wiring L1. The inductor portion 11 is made of a conductive material such as copper, aluminum, cobalt, or ruthenium.

The inductor section 12 is disposed at a region AR2 of the wiring layer WL1 different from the region AR 1. The inductor portion 12 is provided, for example, so that a part thereof becomes a single-layer wound coil formed of polygonal or annular wiring. The inductor portion 12 has one end (1 st end) 121 and the other end (2 nd end) 122. In the example shown in fig. 2, one end 121 of inductor portion 12 is connected to via V2, and the other end 122 of inductor portion 12 is connected to wiring L2. The material of the inductor portion 12 may be the same as the inductor portion 11, for example.

The inductor section 13 is provided in a region AR3 and a region AR4 of the wiring layer WL2 arranged apart from the wiring layer WL1 in the lamination direction. The region AR3 is a region of the wiring layer WL2 corresponding to the region AR1 of the wiring layer WL1 when viewed from the lamination direction. The region AR4 is a region of the wiring layer WL2 corresponding to the region AR2 of the wiring layer WL1 when viewed from the lamination direction. The area AR3 and the area AR4 are not illustrated in fig. 2, but illustrated in fig. 4 (B). The inductor portion 13 constitutes 1 inductor element 10 together with the inductor portion 11 and the inductor portion 12. Inductor portion 13 has an end portion 131 electrically connected to one end 111 of inductor portion 11, and an end portion 132 electrically connected to one end 121 of inductor portion 12. In the example shown in fig. 2, the end 131 is connected to the through hole V1, and the end 132 is connected to the through hole V2. The material of the inductor portion 13 may be the same as the inductor portions 11, 12, for example. The inductor portions 11 to 13 are, for example, wirings formed on a substrate.

More specifically, a part of the inductor section 13 in the region AR3 of the wiring layer WL2 is provided so as to overlap a part of the inductor section 11 when viewed from the lamination direction. In more detail, a portion of the inductor portion 13 overlapping with the inductor portion 11 has, for example, a polygonal shape or a ring shape. In addition, the inductor section 13 in the region AR3 of the wiring layer WL2 is provided in a manner magnetically coupled to the inductor section 11. That is, in the overlapping portion of the inductor portion 11 and the inductor portion 13, the direction in which the current flows is substantially the same, and the inductance can be increased by the mutual inductance. (coupled to each other in a manner that mutually enhances the magnetic flux). The overlapping portion in the inductor portion 13 is provided in such a manner that the inductor portion 11 is extended in the lamination direction to increase the number of windings. This can increase the Q value by increasing the inductance with a short line length. The Q value is a parameter representing the antenna performance or quality of the inductor element 10. Further, details of the inductor element 10 viewed from the lamination direction will be described below with reference to fig. 3 to 4 (B).

In addition, the other part of the inductor section 13 in the region AR4 of the wiring layer WL2 is provided so as to overlap with a part of the inductor section 12 when viewed from the lamination direction. In more detail, the other portion of the inductor portion 13 overlapping with the inductor portion 12 has, for example, a polygonal shape or a ring shape. In addition, the inductor section 13 in the region AR4 of the wiring layer WL2 is provided in such a manner as to be magnetically coupled to the inductor section 12. That is, in the overlapping portion of the inductor portion 12 and the inductor portion 13, the direction in which the current flows is substantially the same, and the inductance can be increased by the mutual inductance. As shown in fig. 2, the overlapping portion of the inductor portion 13 is provided so that the inductor portion 12 extends in the lamination direction to increase the number of windings. This can increase the Q value by increasing the inductance with a short line length. Further, details of the inductor element 10 viewed from the lamination direction will be described below with reference to fig. 3 to 4 (B).

The through hole V1 is provided so as to extend in the lamination direction. The through hole portion V1 electrically connects the end portion 131 of the inductor portion 13 with the one end 111 of the inductor portion 11. Therefore, the via portions V1 connect the inductor portions 11 and 13 provided on the different wiring layers WL1 and WL2, respectively. In the example shown in fig. 2, the through hole portion V1 includes a plurality of (e.g., 2) through hole portions. However, the number of the through hole portions V1 is not limited thereto. For example, as the distance that inductor portion 11 overlaps inductor portion 13 is longer, more via portions V1 are provided, and the resistance due to via portions V1 can be suppressed. The via portion V1 is made of a conductive material such as tungsten or cobalt.

The through hole V2 is provided so as to extend in the lamination direction. The through hole portion V2 electrically connects the end portion 132 of the inductor portion 13 with the one end 121 of the inductor portion 12. Therefore, the via portions V2 connect the inductor portions 12 and 13 provided on the different wiring layers WL1 and WL2, respectively. The number of the through-hole portions V2 may be the same as the through-hole portions V1. The material of the through hole portion V2 may be the same as the through hole portion V1, for example.

Fig. 3 is a plan view showing the structure of the inductor element 10 according to embodiment 1.

As shown in fig. 3, when viewed from the lamination direction, a part of the inductor portion 11 and a part of the inductor portion 13 overlap each other so as to form a winding, and a part of the inductor portion 12 and a part of the inductor portion 13 overlap each other so as to form a winding.

Fig. 4(a) and 4(B) are plan views showing the inductor element 10 of fig. 3 in a divided manner. Fig. 4(a) shows the inductor portions 11, 12 provided in the wiring layer WL 1. Fig. 4(B) shows the inductor section 13 provided in the wiring layer WL 2. The wirings L1 and L2 shown in fig. 4(a) are connected to the wirings L1a and L2a shown in fig. 4(B) via through holes or the like.

One end of inductor element 10 connected to wiring L1 corresponds to the other end 112 of inductor section 11, and the other end of inductor element 10 connected to wiring L2 corresponds to the other end 122 of inductor section 12.

In the example shown in fig. 4, the resonance current flows through wiring L1, the other end 112 and the one end 111 of inductor portion 11, the end 131 and the end 132 of inductor portion 13, the one end 121 and the other end 122 of inductor portion 12, and wiring L2 in this order as indicated by arrow a.

As shown in fig. 4(a), the inductor portions 11 and 12 are arranged symmetrically with respect to the center line CL of the inductor portions 11 and 12 when viewed from the lamination direction. That is, the inductor portions 11 and 12 are provided in a shape that is bilaterally symmetrical (reflection symmetrical or line symmetrical with respect to the center line CL) to each other. Here, the center line CL is an imaginary line.

As shown in fig. 4(B), the inductor portions 13 are disposed substantially symmetrically with respect to the center line CL when viewed from the lamination direction. That is, the inductor portion 13 is provided in a substantially bilaterally symmetric shape.

In addition, as shown in fig. 4(B), the end portion 10t is provided at a specific position of the inductor portion 13. In more detail, the end portion 10t is provided in the inductor portion 13 on the center line CL. Thus, the higher the symmetry of the inductor element 10, the more the symmetry of the differential signal waveform can be ensured, and the common mode noise caused by waveform delay or asymmetry can be further suppressed.

As shown by arrows a1 and a2 in fig. 4(a), at the position where inductor portion 11 and inductor portion 12 are closest to each other, the direction of the current flowing through inductor portion 11 and the direction of the current flowing through inductor portion 12 are opposite to each other. Therefore, between the inductor portion 11 and the inductor portion 12, the magnetic field generated in the inductor portion 11 and the magnetic field generated in the inductor portion 12 weaken each other. The larger the separation distance D between the inductor portion 11 and the inductor portion 12, the larger the inductance of the inductor element 10, and the larger the Q value. However, the larger the separation distance D, the larger the exclusive area of the inductor element 10. Therefore, the separation distance D may be set within a range satisfying the required characteristics.

FIG. 5 is a graph showing an example of the relationship between the Q value and the exclusive area. In fig. 5, the vertical axis represents the Q value, and the horizontal axis represents the exclusive area. Fig. 5 shows the results of the electromagnetic field simulation. Fig. 5 shows an example of data on an inductor used in a 28GHz oscillation circuit. The data points of the triangle represent the data of the inductor device 10 of embodiment 1. The data points in the circle represent data for a differential type spiral inductor wound 2 times. The data points of the quadrangle indicate data of the 1-time wound inductor. In the example shown in FIG. 5, 5 triangle data points are plotted. This is because the simulation was performed by changing the conditions such as the diameter of the coil portion of the inductor, the wiring width, and the separation distance D. In addition, 4 circular data points are also simulated and drawn with the conditions changed. In addition, the data points of 3 quadrangles are also simulated and drawn by changing the conditions.

As shown in fig. 5, the inductor element 10 according to embodiment 1 can suppress the area occupied by the inductor element while maintaining the Q value as compared with the differential spiral inductor wound 2 times and the inductor wound 1 time. The Q value is preferably 10 or more, for example.

As described above, according to embodiment 1, the inductor sections 11, 12 are provided in the wiring layer WL1, and the inductor section 13 is provided in the wiring layer WL2 arranged apart from the wiring layer WL1 in the lamination direction. In addition, an end 131 of the inductor portion 13 is electrically connected to the one end 111 of the inductor portion 11, and an end 132 of the inductor portion 13 is electrically connected to the one end 121 of the inductor portion 12. That is, the inductor portions 11, 12, 13 constitute 1 inductor element 10. With this configuration, the inductor element 10 of embodiment 1 can maintain the Q value and suppress the footprint.

By reducing the footprint of the inductor element 10, chip cost can be cut. In addition, TAT (Turn Around Time) for facilitating the configuration can be reduced. Further, interference between other package or other substrate wiring and the inductor element 10 can be suppressed. This is because the influence of a magnetic field generated by a current flowing through a substrate wiring or the like can be suppressed by suppressing the area of the inductor element 10.

The inductor element 10 may be formed in a rectangular shape when viewed from the lamination direction. This improves the degree of freedom in the arrangement of other components such as pads for wire bonding.

As an inductor element of the LC type oscillation circuit, a differential type spiral inductor may be used. The differential type spiral inductor wound 2 times can obtain high inductance by mutual inductance between the outer-peripheral wiring and the inner-peripheral wiring. However, in this configuration, the parasitic capacitance between the wirings (between the windings) in the in-plane direction (the direction perpendicular to the lamination direction) tends to increase. If the parasitic capacitance is large, the inductance decreases, and the Q value becomes small. In addition, since the area of the wiring portion in the in-plane direction is increased, the parasitic capacitance with the substrate or the upper and lower layers of wiring is increased. The result of this case is that the Q value becomes small. Further, the potential changes from one end of the inductor element to the other end. In the differential spiral inductor wound 2 times, the inter-wire potential difference that causes mutual inductance may be large, and the parasitic capacitance may be large. For this reason, the Q value also becomes small. Further, magnetic coupling corresponding to the thickness of the wiring is formed between the wirings in the in-plane direction in which mutual inductance occurs.

In contrast, in embodiment 1, as shown in fig. 3, in the lamination direction, a part of the inductor portion 11 overlaps a part of the inductor portion 13, and a part of the inductor portion 12 overlaps a part of the inductor portion 13. That is, the area of the wiring portion in the in-plane direction is small. This reduces the parasitic capacitance in the lamination direction of the interposer in the overlapping portion of the inductor portion 13 and the inductor portion 11. In addition, since the inductor portions 11 to 13 are wound 1 time in the in-plane direction, the parasitic capacitance in the in-plane direction is small. Further, since the overlapping portion of the inductor portion 11 and the inductor portion 13 is located on the side of the region AR1 in the wiring of the inductor element 10, the potential difference at the overlapping portion is small, and the parasitic capacitance is small. Also, the same is true of the overlapping portion of the inductor portion 12 and the inductor portion 13 on the area AR2 side. Generally, the width of the wiring is larger than the thickness of the wiring, and therefore, the coupling of the inductor in the lamination direction is stronger than the coupling of the inductor in the in-plane direction. Therefore, a larger inductance can be obtained by the overlapping in the lamination direction. Thus, in the inductor element 10 according to embodiment 1, since the parasitic capacitance is small and the inductance is large, the footprint can be reduced while maintaining a high Q value.

The inductor parts 11 to 13 described above are provided in the 2-layer wiring layers WL1 and WL2, but the present invention is not limited thereto, and may be provided in 3 or more wiring layers. For example, polygonal or ring-shaped inductor sections similar to the inductor sections 11, 12 may be provided on at least 1 intermediate wiring layer between the wiring layer in which the inductor sections 11, 12 are provided and the wiring layer in which the inductor section 13 is provided. The inductor parts of the intermediate wiring layer are also connected to the inductor parts 11 to 13 via the through holes, and 1 inductor element 10 is configured. This can further improve the inductance. In addition, the dedicated area can be reduced without significantly reducing the inductance. In addition, the inductor portion 13 may not be provided with an overlapping portion with the inductor portion of the adjacent wiring layer depending on the position of the via portion.

(modification 1)

Fig. 6 is a circuit diagram showing the configuration of an oscillation circuit device 1a according to variation 1. The variation 1 is different from embodiment 1 in that the current source 40 is disposed at a different position.

The end portion 10t is connected to the power supply connection portion 30. In addition, the current source 40 is disposed between the node N5 and ground.

The oscillation circuit device 1a and the semiconductor integrated circuit device 2 of modification 1 can obtain the same effects as those of embodiment 1.

(modification 2)

Fig. 7 is a plan view showing the structure of an inductor element 10a according to variation 2. The modification 2 is different from the embodiment 1 in the connection position between the inductor portion 11 and the wiring L1 and the connection position between the inductor portion 12 and the wiring L2. These connection positions may be any positions as long as they are within a range in which the characteristics of the inductor portions 11 and 12 can be maintained. That is, the connection position may be changed within a range where the inductor portions 11, 12, 13 overlap when viewed from the lamination direction.

The oscillation circuit device 1b and the semiconductor integrated circuit device 2 of modification example 2 can obtain the same effects as those of embodiment 1.

(embodiment 2)

Fig. 8 is a plan view showing the structure of an inductor element 10b according to embodiment 2. The difference between the embodiment 2 and the embodiment 1 is that inductor portions 14 and 15 are further provided on the outer peripheries of the inductor portions 11, 12 and 13. Note that the inductor portions 11, 12, and 13 shown in fig. 8 are shown with the inductor portions 11, 12, and 13 shown in fig. 2 to 4(B) turned upside down in the drawing. In other words, the inductor portions 11, 12, and 13 shown in fig. 8 are arranged such that the inductor portions 11, 12, and 13 shown in fig. 2 to 4(B) are rotated by 180 degrees with respect to the center of the inductor element 10B. That is, the inductor portions 11, 12, and 13 shown in fig. 8 and the inductor portions 11, 12, and 13 shown in fig. 2 to 4(B) are point-symmetric with respect to the center of the inductor element 10B. Thus, inductor portion 11 is disposed in area AR2, and inductor portion 12 is disposed in area AR 1. Similarly, inductor portion 13 is electrically connected to inductor portion 11 in region AR4 and to inductor portion 12 in region AR 3.

In addition, as explained below, the inductor portions 11, 12, 13 are in a shape that is pointed toward the center portion of the inductor element 10 b. However, the present invention is not limited to this, and may be polygonal or annular as in embodiment 1.

Fig. 9(a) and 9(B) are plan views showing inductor element 10B of fig. 8 in a divided manner. Further, the inductor section 13a shown in fig. 9(a) is provided in a position where the end portion 10t shown in fig. 8 is provided in the wiring layer WL2 among the wiring layers WL 1. The inductor portion 13a is connected to the inductor portion 13 via a through hole portion.

The inductor element 10b further includes inductor portions 14 and 15 and connection lines 14a and 15 a. The inductor portions 11 to 13, the inductor portions 14 and 15, and the connecting wires 14a and 15a constitute 1 inductor element 10 b.

The inductor portion 14 is provided at least one of the outer periphery of at least a part of the inductor portion 12 and the outer periphery of at least a part of the inductor portion 13 in the area AR 3. In more detail, the inductor portion 14 is provided at least one of the side opposite to the inductor portion 11 in the outer periphery of the inductor portion 12 and a part of the outer periphery of the inductor portion 13 in the area AR 3. The inductor portion 14 is, for example, a polygonal or ring-shaped wiring, a wiring having a partial shape (for example, about a half), a U-shape wiring, or the like. The inductor portion 14 includes one end (1 st end) 141 electrically connected to the other end 112 of the inductor portion 11, and the other end (2 nd end) 142 electrically connected to the wiring L1.

In addition, the inductor portion 14 is provided so as to be magnetically coupled to at least one of the inductor portion 12 and the inductor portion 13 in the region AR 3. That is, in the inductor portion 14, the inductor portion 12, and the inductor portion 13 in the area AR3, the directions in which the currents flow are substantially the same, and the inductance can be increased by the mutual inductance.

Inductor portion 14 has inductor portion 16, inductor portion 17, and via portion V3 (not shown).

The inductor section 16 is disposed in the wiring layer WL1 at the outer periphery of at least a part of the inductor section 12. The inductor section 16 is magnetically coupled to the inductor section 12 in a direction perpendicular to the lamination direction, that is, in-plane direction of the wiring layer WL 1. This can improve the inductance of the inductor element 10 b. The inductor portion 16 may be made of the same material as the inductor portions 11-13, for example.

The inductor section 17 is provided in the wiring layer WL2 at the outer periphery of at least a part of the inductor section 13 in the region AR 3. The inductor section 17 is magnetically coupled to a part of the inductor section 13 in a direction perpendicular to the lamination direction, that is, in-plane direction of the wiring layer WL 2. This can improve the inductance of the inductor element 10 b. The inductor portion 17 may be made of the same material as the inductor portions 11 to 13, for example. The inductor portion 17 is connected to the connection wiring 14 a.

The via portion V3 is provided so as to extend in the lamination direction, and electrically connects the inductor portion 16 and the inductor portion 17. The through hole portions V3 are provided in plural along the inductor portions 16, 17, that is, in the entire region where the inductor portions 16, 17 overlap. In addition, 1 via portion V3 may be provided continuously along the inductor portions 16, 17. This increases the thickness of the inductor portion 14 in the lamination direction, and reduces the wiring resistance. As a result, the Q value of the inductor element 10b can be increased. The material of the through hole portion V3 may be the same as the through hole portions V1, V2, for example.

The inductor portion 15 is provided at least one of the outer periphery of at least a part of the inductor portion 11 and the outer periphery of at least a part of the inductor portion 13 in the area AR 4. In more detail, the inductor portion 15 is provided at least one of the side opposite to the inductor portion 12 in the outer periphery of the inductor portion 11 and a part of the outer periphery of the inductor portion 13 in the area AR 4. The inductor portion 15 is, for example, a polygonal or ring-shaped wiring, a wiring having a partial shape (for example, about a half), a U-shape wiring, or the like. The inductor portion 15 includes one end (1 st end) 151 electrically connected to the other end 122 of the inductor portion 12, and the other end (2 nd end) 152 electrically connected to the wiring L2.

In addition, the inductor portion 15 is provided so as to be magnetically coupled to at least one of the inductor portion 11 and the inductor portion 13 in the region AR 4. That is, in the inductor portion 15, the inductor portion 11, and the inductor portion 13 in the area AR4, the directions in which the currents flow are substantially the same, and the inductance can be increased by the mutual inductance.

Inductor portion 15 has inductor portion 18, inductor portion 19, and via portion V4 (not shown).

The inductor section 18 is disposed in the wiring layer WL1 at the outer periphery of at least a part of the inductor section 11. The inductor section 18 is magnetically coupled to the inductor section 11 in a direction perpendicular to the lamination direction, that is, in-plane direction of the wiring layer WL 1. This can improve the inductance of the inductor element 10 b. The inductor portion 18 may be made of the same material as the inductor portions 11-13, for example. The inductor portion 18 is connected to the connection wiring 15 a.

The inductor section 19 is provided in the wiring layer WL2 at the outer periphery of at least a part of the inductor section 13 in the region AR 4. The inductor section 19 is magnetically coupled to a part of the inductor section 13 in a direction perpendicular to the lamination direction, that is, in-plane direction of the wiring layer WL 2. This can improve the inductance of the inductor element 10 b. The inductor portion 19 can be made of the same material as the inductor portions 11-13, for example.

The via portion V4 is provided so as to extend in the lamination direction, and electrically connects the inductor portion 18 and the inductor portion 19. The through hole portions V4 are provided in plural along the inductor portions 18, 19. In addition, 1 via portion V4 may be provided continuously along the inductor portions 18, 19. This increases the thickness of the inductor portion 15 in the lamination direction, and reduces the wiring resistance. As a result, the Q value can be increased. The material of the through hole portion V4 may be the same as the through hole portion V1, for example.

The connection wiring 14a electrically connects one end 141 of the inductor portion 14(17) to the other end 112 of the inductor portion 11. In the example shown in fig. 9(B), the connection wiring 14a is provided in the wiring layer WL 2. The connection wiring 14a has an end portion 143 connected to the other end 112 of the inductor portion 11 via a through hole V5 (not shown). The connection wiring 14a is formed continuously with the inductor portion 14.

The connection wiring 15a electrically connects one end 151 of the inductor portion 15(18) to the other end 122 of the inductor portion 12. In the example shown in fig. 9(a), the connection wiring 15a is provided on the wiring layer WL 1. The connection line 15a is formed continuously with the inductor portion 12 and the inductor portions 15(18) without using a through hole portion.

The connection wiring 14a and the connection wiring 15a are provided in different wiring layers WL1 and WL2, and intersect each other when viewed from the stacking direction. That is, the connection line 14a and the connection line 15a are provided so as to intersect each other without being electrically connected to each other.

One end of inductor element 10b connected to line L1 corresponds to the other end 142 of inductor section 14, and the other end of inductor element 10b connected to line L2 corresponds to the other end 152 of inductor section 15.

The other configurations of the oscillation circuit device 1 and the semiconductor integrated circuit device 2 according to embodiment 2 are the same as the corresponding configurations of the oscillation circuit device 1 and the semiconductor integrated circuit device 2 according to embodiment 1, and therefore, detailed descriptions thereof are omitted.

The inductor element 10b of embodiment 2 can obtain a larger inductance than that of embodiment 1 by the inductor portions 14 and 15.

For example, in the 14GHz band, the inductance must be increased as compared with the 28GHz band shown in embodiment 1. The reason for this is that if the inductance of the inductor element 10b is L and the capacitance of the capacitor 20 is C, the LC resonance frequency f is expressed by equation 1.

The inductor element 10b of embodiment 2 can increase the inductance, and can be used, for example, in a frequency band below the sub-millimeter wave band.

FIG. 10 is a graph showing an example of the relationship between the Q value and the exclusive area. In fig. 10, the vertical axis represents the Q value, and the horizontal axis represents the exclusive area. Fig. 10 shows the results of the electromagnetic field simulation. Fig. 10 shows an example of data on an inductor used in a 14GHz oscillation circuit. The data points of the triangle represent the data of the inductor element 10b of embodiment 2. The circular data points represent data for the differential spiral inductor.

As shown in fig. 10, the inductor element 10b according to embodiment 2 can maintain the Q value and reduce the footprint as compared with the differential spiral inductor. The Q value is preferably 10 or more, for example.

The oscillation circuit device 1 and the semiconductor integrated circuit device 2 according to embodiment 2 can obtain the same effects as those of embodiment 1.

Further, as shown in fig. 8, the curvature of the inductor portion 11 on the side close to the inductor portion 12 is larger than the curvature of the inductor portion 11 on the side far from the inductor portion 12. In addition, the curvature of the inductor portion 12 on the side closer to the inductor portion 11 is larger than the curvature of the inductor portion 12 on the side farther from the inductor portion 11. That is, in the inductor portions 11, 12, portions opposed to each other are tapered. Thereby, the magnetic coupling of the inductor portion 11 and the inductor portion 12 becomes weak. As a result, the distance D between the inductor portions 11 and 12 is not changed (increased), and the decrease in inductance can be suppressed. With this configuration, the inductor element 10a of embodiment 2 can maintain the Q value and reduce the footprint. Further, such a change in curvature may also be applied to embodiment 1.

In addition, the same is true with respect to the curvature of the inductor portion 13. That is, in the region AR4, the curvature of the inductor portion 13 on the side close to the inductor portion 14(17) is larger than the curvature of the inductor portion 13 on the side away from the inductor portion 14 (17). In addition, in the region AR3, the curvature of the inductor portion 13 on the side close to the inductor portion 15(19) is larger than the curvature of the inductor portion 13 on the side away from the inductor portion 15 (19). Further, such a change in curvature may also be applied to embodiment 1.

Fig. 11 is a plan view showing a configuration of an inductor element 10c according to a modification of embodiment 2. Not only the curvature, but also the reduction in inductance can be suppressed by changing the line width. That is, the line width of the inductor portion 11 on the side close to the inductor portion 12 is thinner than the line width of the inductor portion 11 on the side far from the inductor portion 12. In addition, the line width of the inductor portion 12 on the side close to the inductor portion 11 is thinner than the line width of the inductor portion 12 on the side far from the inductor portion 11. If the line width is too small, the value of the wiring resistance increases, and therefore, the line width may be set so as to fall within a range satisfying the required characteristics. Further, such a variation in line width can also be applied to embodiment 1. In addition, two operations of curvature change and line width change may be performed.

In addition, the same applies to the line width of the inductor portion 13. That is, in the region AR4, the line width of the inductor portion 13 on the side close to the inductor portion 14(17) is thinner than the line width of the inductor portion 13 on the side far from the inductor portion 14 (17). In addition, in the region AR3, the line width of the inductor portion 13 on the side close to the inductor portion 15(19) is smaller than the line width of the inductor portion 13 on the side far from the inductor portion 15 (19). Further, such a variation in line width can also be applied to embodiment 1.

Further, the thickness of the wiring is increased by the via portions V1 and V2 shown in fig. 2. Therefore, the through-hole portions V1, V2 are preferably provided offset from the positions where the inductor portion 11 is closest to the inductor portion 12.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in various other forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalent scope thereof.

(remarks)

Hereinafter, the contents of the above embodiments are noted.

(Note 1)

A semiconductor integrated circuit device, wherein said 3 rd inductor part in said 3 rd region is provided in such a manner as to be magnetically coupled with said 1 st inductor part, and

the 3 rd inductor part in the 4 th region is provided in a manner of being magnetically coupled with the 2 nd inductor part.

(Note 2)

A semiconductor integrated circuit device, wherein said 4 th inductor portion is provided in such a manner as to be magnetically coupled to at least one of said 2 nd inductor portion and said 3 rd inductor portion in said 4 th region, and

the 5 th inductor portion is provided in a manner magnetically coupled to at least one of the 1 st inductor portion and the 3 rd inductor portion in the 3 rd region.

(Note 3)

A semiconductor integrated circuit device further includes:

a1 st connection wiring electrically connecting the one end of the 4 th inductor portion and the other end of the 1 st inductor portion; and

a2 nd connection wiring electrically connecting the one end of the 5 th inductor portion and the other end of the 2 nd inductor portion; and is

The 1 st connecting wire and the 2 nd connecting wire are provided in mutually different wiring layers and are provided so as to intersect when viewed from the 1 st direction.

(Note 4)

A semiconductor integrated circuit device, wherein a curvature of the 3 rd inductor portion in the 3 rd region on a side closer to the 2 nd inductor portion is larger than a curvature of the 3 rd inductor portion in the 3 rd region on a side farther from the 2 nd inductor portion when viewed from the 1 st direction, and

the curvature of the 3 rd inductor part in the 4 th region on the side closer to the 1 st inductor part as viewed from the 1 st direction is larger than the curvature of the 3 rd inductor part in the 4 th region on the side farther from the 1 st inductor part.

(Note 5)

A semiconductor integrated circuit device, wherein a line width of the 3 rd inductor part in the 3 rd region on a side close to the 2 nd inductor part is thinner than a line width of the 3 rd inductor part in the 3 rd region on a side far from the 2 nd inductor part when viewed from the 1 st direction, and

a line width of the 3 rd inductor portion in the 4 th region on a side closer to the 1 st inductor portion as viewed from the 1 st direction is thinner than a line width of the 3 rd inductor portion in the 4 th region on a side farther from the 1 st inductor portion.

[ description of symbols ]

1 oscillating circuit device

2 semiconductor integrated circuit device

10 inductor element

10t end

11 inductor part

12 inductor part

13 inductor part

131 end portion

132 end portion

14 inductor part

14a connecting wiring

15 inductor part

15a connecting wiring

16 inductor part

17 inductor part

18 inductor part

19 inductor part

20 capacitor

Area of AR1

Area of AR2

V1 through hole part

V2 through hole part

V3 through hole part

V4 through hole part

WL1 wiring layer

WL2 wiring layer