阅读说明：本技术 存储器系统及操作存储器系统的方法 (Memory system and method of operating the same ) 是由 边谕俊 于 2019-11-01 设计创作，主要内容包括：本公开提供一种存储器系统及操作该存储器系统的方法。该存储器系统可以包括：存储器装置,包括多个存储块；控制器,被配置为管理多个存储块中的每一个的读取计数值,并生成与读取计数值对应的级别信息；以及主机,被配置为基于级别信息输出用于请求存储器装置的垃圾收集操作的主机命令。(The present disclosure provides a memory system and a method of operating the same. The memory system may include: a memory device comprising a plurality of memory blocks; a controller configured to manage a read count value of each of the plurality of memory blocks and generate level information corresponding to the read count value; and a host configured to output a host command for requesting a garbage collection operation of the memory device based on the level information.)

1. A memory system, comprising:

a memory device comprising a plurality of memory blocks;

a controller that manages a read count value of each of the plurality of memory blocks and generates level information corresponding to the read count value; and

a host outputting a host command for requesting a garbage collection operation of the memory device based on the level information.

2. The memory system according to claim 1, wherein the memory unit is a single memory unit,

wherein when a read count value of a memory block on which a read operation has been performed among the plurality of memory blocks is equal to or greater than a first preset value, the controller controls the memory device to perform a read reclaim operation on the memory block, and

wherein the controller generates the level information based on the read count value when the read count value of the storage block is less than the first preset value.

3. The memory system of claim 2, wherein the controller comprises:

a processor to generate a command queue in response to the host command and to control the read reclaim operation or generate the level information based on a read count value of each of the plurality of memory blocks; and

a flash control circuit to control the memory device to perform the read reclamation operation or the garbage collection operation in response to the command queue.

4. The memory system of claim 3, wherein the processor comprises:

a flash translation layer generating the command queue corresponding to the read operation or the garbage collection operation in response to the host command and mapping a logical address received with the host command to a physical address of the memory device; and

a read reclamation control block managing a read count value of the memory block on which the read operation has been performed, and controlling the read reclamation operation or generating the level information based on the read count value.

5. The memory system of claim 4, wherein the read reclaim control block comprises:

a read count storage block that manages a read count value of each of the plurality of storage blocks, and increments and counts the read count value of the storage block on which the read operation has been performed;

a target block selection block which selects the memory block as a victim block when the read count value of the memory block is equal to or greater than the first preset value;

a read count level determination block that generates the level information when a read count value of the storage block is smaller than the first preset value, the level information including any one level determined based on the read count value of the storage block among a plurality of levels; and

and the read recovery control unit controls the flash memory control circuit to execute the read recovery operation on the sacrificial block.

6. The memory system according to claim 5, wherein when the level information is generated from the read count level determination block, the flash translation layer checks a logical address corresponding to the memory block on which the read operation has been performed, matches the level information with the checked logical address, and outputs the level information matching the logical address to the host.

7. The memory system according to claim 1, wherein the controller outputs the level information to the host together with a command response signal of the host command.

8. The memory system of claim 1, wherein the host comprises:

a host processor generating the host command and a logical address and outputting the host command and the logical address to the controller; and

a garbage collection control block increasing a read count value of each of logical addresses, among the logical addresses, for which a read operation has been completed, and selecting a logical address at which the garbage collection operation is to be performed according to the read count value of the logical address,

wherein the host processor generates the host command for requesting the garbage collection operation when the number of logical addresses selected by the garbage collection control block is equal to or greater than a preset value.

9. The memory system of claim 8, wherein the garbage collection control block weights a read count value for each of the logical addresses based on the level information.

10. The memory system according to claim 8, wherein the garbage collection control block selects one of the logical addresses as an urgent logical address based on the level information.

11. The memory system of claim 10, wherein the host processor immediately generates the host command for requesting the garbage collection operation when the emergency logical address is selected by the garbage collection control block.

12. A memory system, comprising:

a memory device comprising a plurality of memory blocks;

a controller which controls the memory device to perform a read reclamation operation based on a read count value of a memory block in which a read operation has been completed or generates level information based on the read count value of the memory block; and

a host that manages a read count value of each of logical addresses corresponding to memory blocks that have completed the read operation based on the level information.

13. The memory system according to claim 12, wherein the host generates a host command corresponding to a garbage collection operation of the memory device based on the read count value of each of the logical addresses and outputs the host command.

14. The memory system of claim 12, wherein the controller comprises:

a processor generating a command queue in response to a host command and controlling the read reclamation operation or generating the level information based on a read count value of each of the plurality of memory blocks; and

a flash control circuit responsive to the command queue to control the memory device to perform the read reclaim operation or a garbage collection operation.

15. The memory system of claim 12, wherein the host comprises:

a host processor generating a host command and outputting the host command to the controller together with a logical address at which the read operation is to be performed; and

a garbage collection control block increasing a read count value of a corresponding logical address if the read operation has been completed, and selecting a logical address at which a garbage collection operation is to be performed according to the read count value of the logical address,

wherein the host processor generates the host command corresponding to the garbage collection operation when the number of logical addresses selected by the garbage collection control block is equal to or greater than a preset value.

16. The memory system of claim 15, wherein the garbage collection control block weights a read count value for each of the logical addresses based on the level information.

17. The memory system as set forth in claim 15,

wherein the garbage collection control block selects one of the logical addresses as an urgent logical address based on the level information, and

wherein the host processor immediately generates the host command corresponding to the garbage collection operation when the emergency logical address is selected by the garbage collection control block.

18. A method of operating a memory system, comprising:

performing a read reclamation operation based on a first read count value of a memory block having completed a read operation, or generating level information of the first read count value;

managing a second read count value of each of logical addresses corresponding to memory blocks that have completed the read operation based on the level information; and is

Performing a garbage collection operation based on the second read count value of each of the logical addresses.

19. The method of claim 18, wherein the managing comprises: increasing a second read count value of a first logical address, among the logical addresses, at which the read operation has been performed, and weighting the second read count value of each of the logical addresses based on the level information.

20. The method of claim 19, wherein the first and second portions are selected from the group consisting of,

wherein the garbage collection operation is performed when the number of logical addresses each having the second read count value equal to or greater than a preset value among the logical addresses is equal to or greater than a preset number, and

wherein the garbage collection operation is immediately performed on at least one logical address determined as an urgent logical address based on the level information among the logical addresses.

Technical Field

Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a memory system and a method of operating the same.

Background

More recently, computer environment paradigms have turned into pervasive computing where computer systems can be used anytime and anywhere. Therefore, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has been rapidly increasing. Generally, such portable electronic devices use a memory system employing a memory device, in other words, use a data storage device. The data storage device is used as a primary memory device or a secondary memory device of the portable electronic device.

The data storage device using the memory device provides advantages in that stability and durability are excellent, information access speed is increased, and power consumption is reduced because there is no mechanical driving part. Examples of the data storage device having these advantages may include a Universal Serial Bus (USB) memory device, a memory card having various interfaces, a Solid State Drive (SSD), and the like.

Memory devices are classified into volatile memory devices and nonvolatile memory devices.

The nonvolatile memory device, although having relatively low read and write speeds, can retain data stored therein even in the event of power interruption. Therefore, when data that needs to be retained regardless of whether the memory device is connected to a power supply needs to be stored, a nonvolatile memory device is used. Representative examples of non-volatile memory devices include Read Only Memory (ROM), mask ROM (mrom), programmable ROM (prom), erasable programmable ROM (eprom), electrically erasable programmable ROM (eeprom), flash memory, phase change random access memory (PRAM), magnetic ram (mram), resistive ram (rram), ferroelectric ram (fram), and the like. Flash memories are classified into NOR type memories and NAND type memories.

Disclosure of Invention

Various embodiments of the present disclosure relate to a memory system capable of controlling a garbage collection operation and a read reclamation operation to perform the garbage collection operation and the read reclamation operation without overlapping each other, and a method of operating the memory system.

Embodiments of the present disclosure may provide a memory system including: a memory device having a plurality of memory blocks; a controller configured to manage a read count value of each of the plurality of memory blocks and generate level information corresponding to the read count value; and a host configured to output a host command for requesting a garbage collection operation of the memory device based on the level information.

Embodiments of the present disclosure may provide a memory system including: a memory device comprising a plurality of memory blocks; a controller configured to control the memory device to perform a read reclamation operation based on a read count value of a memory block in which a read operation has been completed or to generate level information based on the read count value of the memory block; and a host configured to manage a read count value of each of logical addresses corresponding to the memory blocks having completed the read operation based on the level information.

Embodiments of the present disclosure may provide a method of operating a memory system, the method comprising: performing a read reclamation operation based on a first read count value of a memory block having completed a read operation, or generating level information of the first read count value; managing a second read count value of each of logical addresses corresponding to the memory blocks having completed the read operation based on the level information; and performing a garbage collection operation based on the second read count value of each of the logical addresses.

Embodiments of the present disclosure may provide a method of operating a memory system, the method comprising: performing a read reclamation operation on a memory block of which the physical read count is equal to or greater than the RRC threshold value among the memory blocks; setting a logical read count for each memory block by weighting (weighting) one or more partial groups of the logical read count based on the physical read count for each memory block, wherein the physical read count corresponding to each partial group falls within a respective range relative to the RRC threshold; and performing a garbage collection operation on one or more memory blocks, among the memory blocks, each of which logical read count is equal to or greater than the GC threshold.

Drawings

Fig. 1 is a block diagram illustrating a memory system according to an embodiment of the present disclosure.

Fig. 2 is a block diagram showing a configuration of the controller of fig. 1.

Fig. 3 is a block diagram illustrating a read reclamation control block of fig. 2.

Fig. 4 is a diagram describing the semiconductor memory of fig. 1.

Fig. 5 is a diagram illustrating the memory block of fig. 4.

Fig. 6 is a diagram illustrating a memory block having a three-dimensional structure according to an embodiment of the present disclosure.

Fig. 7 is a diagram illustrating a memory block having a three-dimensional structure according to an embodiment of the present disclosure.

FIG. 8 is a flow chart illustrating operation of a memory system according to an embodiment of the present disclosure.

Fig. 9 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

Fig. 10 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

Fig. 11 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

Fig. 12 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

Detailed Description

The specific structural and functional descriptions of the embodiments of the present disclosure that are incorporated in this specification or application are intended to describe the embodiments of the present disclosure only. The examples should not be construed as being limited to the descriptions disclosed in this specification or application.

The present disclosure will now be described in detail based on examples. This disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein but should be construed to cover modifications, equivalents, or alternatives falling within the spirit and scope of the present disclosure. It will be understood, however, that the description is not intended to limit the disclosure to those exemplary embodiments, and that the disclosure is not intended to cover the exemplary embodiments, but rather, to cover various alternatives, modifications, equivalents, and other embodiments, which may fall within the spirit and scope of the disclosure.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Similarly, a second element may also be referred to as a first element.

It will be understood that when an element is referred to as being "coupled" or "connected" to another element, it can be directly coupled or connected to the other element or intervening elements may be present between the two elements. In contrast, it will be understood that when an element is referred to as being "directly coupled" or "directly connected" to another element, there are no intervening elements present. Other expressions such as "between … …", "directly between … …", "adjacent to … …" or "directly adjacent to … …" describing the relationship between elements should be interpreted in the same way.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. In this disclosure, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," "including," "has," "having," and the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

A detailed description of known functions and configurations by those skilled in the art will be omitted so as not to obscure the subject matter of the present disclosure. This is intended to omit unnecessary description in order to make the subject matter of the present disclosure clear.

Various embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, which illustrate preferred embodiments of the present disclosure so that those skilled in the art can easily implement the technical concepts of the present disclosure.

Fig. 1 is a block diagram illustrating a memory system 1000 according to an embodiment of the present disclosure.

Referring to fig. 1, a memory system 1000 may include a memory device 1100, a controller 1200, and a host 1300. The memory device 1100 may include a plurality of semiconductor memories 100. The plurality of semiconductor memories 100 may be divided into a plurality of groups. Although the host 1300 has been shown and described as being included in the memory system 1000 in the present embodiment, the memory system 1000 may include only the controller 1200 and the memory device 1100, and the host 1300 may be provided outside the memory system 1000.

In fig. 1, a plurality of banks of the memory device 1100 are shown to communicate with the controller 1200 through the first to nth channels CH1 to CHn, respectively. Each semiconductor memory 100 will be described below with reference to fig. 4.

Each of the plurality of sets of semiconductor memories 100 may communicate with the controller 1200 through one common channel. The controller 1200 may control the plurality of semiconductor memories 100 of the memory device 1100 through the plurality of channels CH1 through CHn.

The controller 1200 is coupled between the host 1300 and the memory device 1100. The controller 1200 may access the memory device 1100 in response to a request from the host 1300. For example, in response to a Host command Host _ CMD received from the Host 1300, the controller 1200 may control a read operation, a write operation, an erase operation, or a background operation of the memory device 1100. During a write operation, the Host 1300 may transfer data and an address together with the Host command Host _ CMD. During a read operation, the Host 1300 may transfer an address along with the Host command Host _ CMD. The address may be a logical address. After a read operation, a write operation, or an erase operation has been performed in response to the Host command Host _ CMD, the controller 1200 may output a command response signal CMD _ response corresponding to the result of the completed operation to the Host 1300.

After the read operation, the controller 1200 may check a read count value of a memory block in the memory device 1100, on which the read operation has been performed, and perform a read reclaim (hereinafter, referred to as "RRC") operation on the corresponding memory block based on the check result. Further, the controller 1200 may generate level information level _ info based on the read count value of the checked memory block and transfer the level information level _ info to the host 1300. The level information level _ info indicates a ratio of a read count value of each of the memory blocks with respect to a read count threshold value of the RRC operation. The level information level _ info may be output to the host 1300 together with the command response signal CMD _ response.

The host 1300 may include a host processor 1310 and a garbage collection control block 1320.

The Host processor 1310 may generate at least one Host command Host _ CMD corresponding to a user request and transmit the Host command Host _ CMD to the controller 1200. Further, the Host processor 1310 may generate a Host command Host _ CMD for performing a garbage collection (hereinafter, referred to as "GC") operation on the logical address selected by the garbage collection control block 1320, and transmit the generated Host command Host _ CMD to the controller 1200 together with the selected logical address. When the number of logical addresses selected by the garbage collection control block 1320 is equal to or greater than a preset value, the Host processor 1310 may generate a Host command Host _ CMD corresponding to a GC operation of the selected logical addresses. Further, if information on a logical address selected as the urgent logical address by the garbage collection control block 1320 is received, the Host processor 1310 may immediately generate a Host command Host _ CMD corresponding to the GC operation of the urgent logical address and output the Host command Host _ CMD to the controller 1200 together with the urgent logical address. In other words, if there is at least one logical address selected as the urgent logical address, it is possible to immediately generate a Host command Host _ CMD corresponding to the GC operation and output the Host command Host _ CMD to the controller 1200.

The garbage collection control block 1320 may manage a read count value for each of a plurality of logical addresses, a weighted read count value for some logical addresses, and update the read count value based on the level information level _ info received from the controller 1200. The garbage collection control block 1320 may select logical addresses each having a read count value equal to or greater than a second preset value and transmit information on the selected logical addresses to the host processor 1310. Further, the garbage collection control block 1320 may select a logical address, which is required to immediately perform the GC operation, as an urgent logical address based on the level information level _ info, and transmit information about the urgent logical address to the host processor 1310.

The controller 1200 and the memory device 1100 may be integrated into a single semiconductor device. In an embodiment, the controller 1200 and the memory device 1100 may be integrated into a single semiconductor device to form a memory card. For example, the controller 1200 and the memory device 1100 may be integrated into a single semiconductor device and form a memory card such as the following: personal Computer Memory Card International Association (PCMCIA), Compact Flash (CF) card, smart media card (SM or SMC), memory stick, multimedia card (MMC, RS-MMC or micro MMC), SD card (SD, mini SD, micro SD or SDHC) or Universal Flash (UFS).

The controller 1200 and the memory device 1100 may be integrated into a single semiconductor device to form a Solid State Drive (SSD). The SSD may include a storage device configured to store data in the semiconductor memory 100.

In an embodiment, the memory system 1000 may be provided as one of various elements of an electronic device such as: a computer, an ultra mobile pc (umpc), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an electronic reader, a Portable Multimedia Player (PMP), a game machine, a navigation device, a black box, a digital camera, a three-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting/receiving information in a wireless environment, one of various devices for forming a home network, one of various electronic devices for forming a computer network, one of various electronic devices for forming a telematics network, an RFID device, one of various elements for forming a computing system, and the like.

In embodiments, memory device 1100 or memory system 1000 may be embedded in various types of packages. For example, memory device 1100 or memory system 1000 may be packaged in types such as: package on package (PoP), Ball Grid Array (BGA), Chip Scale Package (CSP), Plastic Leaded Chip Carrier (PLCC), plastic dual in-line package (PDIP), Die in package (Die in Wafer Pack), Die in Wafer Form (Die in Wafer Form), Chip On Board (COB), ceramic dual in-line package (CERDIP), plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat Pack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer scale manufacturing package (WFP), or Wafer scale processing stack package (WSP).

Fig. 2 is a block diagram illustrating a configuration of the controller 1200 of fig. 1 according to an embodiment of the present disclosure.

Referring to fig. 2, the controller 1200 may include a host control circuit 1210, a processor 1220, a buffer memory 1230, an error correction circuit 1240, a flash memory control circuit 1250, and a bus 1260.

Bus 1260 may provide a channel between the components of controller 1200.

The host control circuit 1210 may control data transfer between the host 1300 and the buffer memory 1230 of fig. 1. For example, the host control circuit 1210 may control an operation of buffering data input from the host 1300 to the buffer memory 1230. In an embodiment, the host control circuit 1210 may control an operation of outputting data buffered in the buffer memory 1230 to the host 1300. In addition, the host control circuit 1210 may control an operation of outputting a command response signal and level information generated from the processor 1220 to the host 1300.

The host control circuitry 1210 may include a host interface.

The processor 1220 may control the overall operation of the controller 1200 and perform logical operations. Processor 1220 may communicate with host 1300 of FIG. 1 through host control circuitry 1210 and with memory device 1100 of FIG. 1 through flash control circuitry 1250. Processor 1220 may control the operation of memory system 1000 by using buffer memory 1230 as an operation memory, cache memory, or buffer. Processor 1220 may rearrange a plurality of host commands received from host 1300 based on priority and generate a command queue, and may control flash control circuit 1250 based on the command queue. Further, the processor 1220 may manage respective read count values of a plurality of memory blocks included in the memory device 1100, and control the flash memory control circuit 1250 to perform an RRC operation on a memory block of which the read count value is equal to or greater than a first preset value (e.g., a read count threshold value of the RRC operation). In addition, the processor 1220 may generate level information of logical addresses corresponding to the plurality of memory blocks based on respective read count values of the plurality of memory blocks.

When a Host command Host _ CMD corresponding to the GC operation is received from the Host 1300, the processor 1220 may check a physical address corresponding to a logical address received together with the Host command Host _ CMD, and generate a command queue and control the flash control circuit 1250 to perform the GC operation on a memory block corresponding to the checked physical address.

Processor 1220 may include a flash translation layer (hereinafter, referred to as "FTL") 1221 and a read reclaim control block 1222.

The FTL1221 may operate based on firmware. The firmware may be stored in the buffer memory 1230, an additional memory (not shown) directly coupled to the processor 1220, or a memory space defined in the processor 1220. During a write operation, FTL1221 may map a corresponding physical address to a logical address input from host 1300 of fig. 1. Further, during a read operation, FTL1221 may check a physical address mapped to a logical address input from host 1300. Here, the mapping operation may be performed based on the mapping data stored in the buffer memory 1230. During an operation of generating level information after a read operation, FTL1221 may check a logical address corresponding to an associated memory block, match the level information with the checked logical address, and output the level information to host 1300.

FTL1221 may generate a command queue for controlling flash control circuitry 1250 in response to host commands received from host 1300.

After the read operation has been completed, the read reclamation control block 1222 may increase a read count value of a memory block on which the read operation has been performed, and may control the flash control circuit 1250 to select a memory block of which the read count value is equal to or greater than a first preset value (e.g., a read count threshold value for an RRC operation) as a victim block and perform an RRC operation on the selected memory block.

The read reclamation control block 1222 may generate level information including any one level among a plurality of levels determined according to a read count value of a memory block having completed a read operation and a first preset value. For example, when the read count value is less than 70% of the first preset value, the level information may be generated as a first level; when the read count value is equal to or greater than 70% and less than 80% of the first preset value, the level information may be generated as a second level; when the read count value is equal to or greater than 80% of the first preset value and less than 90% of the first preset value, the level information may be generated as a third level; and the level information may be generated as a fourth level when the read count value is equal to or greater than 90% of the first preset value.

FTL1221 may match the generated level information with a logical address corresponding to an associated memory block and output the generated level information to host 1300.

The buffer memory 1230 may be used as an operation memory, a cache memory, or a buffer of the processor 1220. The buffer memory 1230 may store codes and commands to be executed by the processor 1220. The buffer memory 1230 may store data processed by the processor 1220. In addition, the buffer memory 1230 may store mapping data for mapping operations to be performed in the processor 1220. The mapping data may be stored in the memory device (1100 of fig. 1) and may be read and stored in the buffer memory 1230 during a power-on operation of the memory system 1000.

Buffer memory 1230 may include a mapped data storage block 1231, a write buffer 1232, and a read buffer 1233. The mapping data storage block 1231 may store mapping data. During a write operation, the write buffer 1232 may temporarily store data received from the host 1300 and then transfer the temporarily stored data to the memory device 1100. During a read operation, the read buffer 1233 may temporarily store data received from the memory device 1100 and then transfer the temporarily stored data to the host 1300.

Buffer memory 1230 may include static ram (sram) or dynamic ram (dram).

Error correction circuitry 1240 may perform error correction operations. Error correction circuitry 1240 may perform ECC (error correction code) encoding operations based on data to be written to memory device 1100 of fig. 1 by flash control circuitry 1250. The ECC encoded data may be transferred to the memory device 1100 through the flash control circuit 1250. Error correction circuitry 1240 may perform ECC decoding operations on data received from memory device 1100 by flash control circuitry 1250. For example, error correction circuitry 1240 may be included in flash control circuitry 1250 as a component of flash control circuitry 1250.

In response to the command queue generated from processor 1220, flash control circuitry 1250 may generate and output internal commands for controlling memory device 1100. During a write operation, the flash control circuit 1250 may control an operation of transferring and writing data buffered in the write buffer 1232 of the buffer memory 1230 to the memory device 1100. In an embodiment, during a read operation, flash control circuitry 1250 may be responsive to the command queue to control the buffering of data read from memory device 1100 in read buffer 1233 of buffer memory 1230.

During the RRC operation, the flash control circuit 1250 may control the memory device 1100 to copy data stored in a memory block selected as a victim block and store the copied data in a memory block selected as a target block. Thereafter, the sacrificial block may be erased.

During the GC operation, the flash control circuit 1250 may control the memory device 1100 to copy the valid data of the plurality of memory blocks selected as the victim block and store the copied valid data in the memory block selected as the target block. Thereafter, data stored in the plurality of memory blocks selected as the victim block may be erased.

Flash control circuitry 1250 may include a flash interface.

FIG. 3 is a block diagram illustrating the read reclaim control block 1222 of FIG. 2 in accordance with an embodiment of the disclosure.

Referring to fig. 3, the read reclamation control block 1222 may include a read count storage block 1222A, a target block selection block 1222B, a read count level determination block 1222C, and a read reclamation control unit 1222D.

The read count storage block 1222A may store respective read count values of a plurality of storage blocks included in the memory device (1100 of fig. 1), and manage the read count values in such a manner that the read count value of the corresponding storage block is increased each time the read operation is completed.

The target block selection block 1222B may compare the read count value of the memory block having completed the read operation with a first preset value, and select the corresponding memory block as a victim block when the read count value of the memory block is equal to or greater than the first preset value. During RRC operation, the target block selection block 1222B may select a target memory block to store data of a memory block selected as a victim block. The target block selection block 1222B may select any one of the memory blocks each having an erase state as a target memory block.

The read count level determination block 1222C may determine a ratio of a read count value of a memory block in which a read operation has been completed with respect to a first preset value, and generate level information. For example, the read count level determination block 1222C may: generating level information as a first level when a read count value of a memory block having completed a read operation is less than 70% of a first preset value; generating the level information as a second level when the read count value is equal to or greater than 70% and less than 80% of the first preset value; generating the level information as a third level when the read count value is equal to or greater than 80% and less than 90% of the first preset value; and generates the level information as a fourth level when the read count value is equal to or greater than 90% of the first preset value. The generated level information may be matched with a logical address corresponding to an associated memory block by the FTL (1221 of fig. 2) and output to the host 1300.

If the target block selection block 1222B selects a victim block and a target block, the read reclamation control unit 1222D may control the flash control circuit (1250 of fig. 2) to perform an RRC operation on the victim block.

Fig. 4 is a diagram describing the semiconductor memory 100 of fig. 1.

Referring to fig. 4, the semiconductor memory 100 may include a memory cell array 10 configured to store data. The semiconductor memory 100 may include a peripheral circuit 200, the peripheral circuit 200 being configured to perform a program operation for storing data in the memory cell array 10, a read operation for outputting the stored data, and an erase operation for erasing the stored data. The semiconductor memory 100 may include a control logic 300, the control logic 300 being configured to control the peripheral circuit 200 under the control of the controller (1200 of fig. 1).

Memory cell array 10 may include a plurality of memory blocks MB1 through MBk (11), where k is a positive integer. Local lines LL and bit lines BL1 to BLm (m is a positive integer) may be coupled to each of the memory blocks MB1 to MBk (11). For example, the local line LL may include a first selection line, a second selection line, and a plurality of word lines arranged between the first selection line and the second selection line. The local line LL may include dummy lines disposed between the first selection line and the word line and between the second selection line and the word line. Here, the first selection line may be a source selection line, and the second selection line may be a drain selection line. For example, the local line LL may include a word line, a drain select line, a source select line, and a source line SL. For example, the local line LL may further include a dummy line. For example, the local line LL may further include a pipeline. The local line LL may be coupled to each of the memory blocks MB1 to MBk (11). The bit lines BL1 to BLm may be commonly coupled to the memory blocks MB1 to MBk (11). The memory blocks MB1 through MBk (11) may be implemented in a two-dimensional structure or a three-dimensional structure. For example, in the memory block 11 having a two-dimensional structure, memory cells may be arranged in a direction parallel to the substrate. For example, in the memory block 11 having a three-dimensional structure, memory cells may be stacked in a direction perpendicular to a substrate.

At least one of the memory blocks MB1 through MBk (11) (e.g., MB1) may be defined as a system memory block, and the mapping data may be stored in the system memory block.

The peripheral circuit 200 may perform a program operation, a read operation, or an erase operation on the selected memory block 11 under the control of the control logic 300. For example, the peripheral circuitry 200 may include voltage generation circuitry 210, a row decoder 220, a page buffer bank 230, a column decoder 240, input/output circuitry 250, pass/fail check circuitry 260, and source line drivers 270.

The voltage generation circuit 210 may generate various operation voltages Vop to be used for a program operation, a read operation, and an erase operation in response to the operation signal OP _ CMD. Further, the voltage generation circuit 210 may selectively discharge the local line LL in response to the operation signal OP _ CMD. For example, the voltage generation circuit 210 may generate a program voltage, a verify voltage, a pass voltage, and a select transistor operation voltage under the control of the control logic 300.

The row decoder 220 may transfer the operation voltage Vop to the local line LL coupled to the selected memory block 11 in response to the control signal AD _ signals. For example, the row decoder 220 may selectively apply the operating voltages (e.g., the program voltage, the verify voltage, and the pass voltage) generated from the voltage generation circuit 210 to the word line among the local lines LL in response to the row decoder control signal AD _ signals.

During the program voltage applying operation, the row decoder 220 may apply the program voltage generated by the voltage generating circuit 210 to a selected word line among the local lines LL and apply the pass voltage generated by the voltage generating circuit 210 to other unselected word lines in response to the control signal AD _ signals. During a read operation, the row decoder 220 may apply a read voltage generated by the voltage generation circuit 210 to a selected word line of the local lines LL and apply a pass voltage generated by the voltage generation circuit 210 to other unselected word lines in response to the control signal AD _ signals.

The page buffer group 230 may include a plurality of page buffers PB1 to PBm (231) coupled to bit lines BL1 to BLm. The page buffers PB1 through PBm (231) may operate in response to page buffer control signals PBSIGNALS. For example, the page buffers PB1 to PBm (231) may temporarily store data to be programmed during a program operation, or sense voltages or currents of the bit lines BL1 to BLm during a read operation or a verify operation.

In response to the column address CADD, the column decoder 240 may transfer data between the input/output circuit 250 and the page buffer group 230. For example, the column decoder 240 may exchange data with the page buffer 231 through the data lines DL or with the input/output circuit 250 through the column lines CL.

The input/output circuit 250 may transfer an internal command CMD or an address ADD received from the controller (1200 of fig. 1) to the control logic 300 or exchange data with the column decoder 240. The address ADD may be an address mapped with a physical address.

During a read operation or a verify operation, the PASS/FAIL check circuit 260 may generate a reference current in response to the enable BIT VRY _ BIT < # >, and may compare the sensing voltage VPB received from the page buffer group 230 with a reference voltage generated by the reference current and output a PASS signal PASS or a FAIL signal FAIL.

The source line driver 270 may be coupled to the memory cells included in the memory cell array 10 through the source lines SL, and may control a voltage to be applied to the source lines SL. The source line driver 270 may receive a source line control signal CTRL _ SL from the control logic 300 and control a source line voltage to be applied to the source line SL based on the source line control signal CTRL _ SL.

In response to the internal command CMD and the address ADD, the control logic 300 may control the peripheral circuit 200 by outputting the operation signal OP _ CMD, the control signal AD _ signals, the source line control signal CTRL _ SL, the page buffer control signal PBSIGNALS, the enable BIT VRY _ BIT < # >, and the column address CADD. In addition, in response to PASS signal PASS or FAIL signal FAIL, control logic 300 may determine whether the target memory cell has passed verification during a verify operation.

Fig. 5 is a diagram illustrating the memory block 11 of fig. 4.

Referring to fig. 5, in the memory block 11, a plurality of word lines arranged in parallel with each other may be coupled between a first selection line and a second selection line. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. In more detail, the memory block 11 may include a plurality of strings ST coupled between the bit lines BL1 to BLm and the source lines SL. The bit lines BL1 to BLm may be respectively coupled to the strings ST, and the source lines SL may be commonly coupled to the strings ST. The strings ST may have the same configuration; therefore, the string ST coupled to the first bit line BL1 will be described in detail by way of example.

The string ST may include a source select transistor SST, a plurality of memory cells F1 to F16, and a drain select transistor DST coupled in series to each other between a source line SL and a first bit line BL 1. At least one source select transistor SST and at least one drain select transistor DST may be included in each string ST, and a greater number of memory cells than the number of memory cells F1 through F16 shown in the drawing may be included in each string ST.

A source of the source select transistor SST may be coupled to a source line SL, and a drain of the drain select transistor DST may be coupled to a first bit line BL 1. The memory cells F1 through F16 may be coupled in series between the source select transistor SST and the drain select transistor DST. Gates of the source select transistors SST included in different strings ST may be coupled to a source select line SSL, gates of the drain select transistors DST may be coupled to a drain select line DSL, and gates of the memory cells F1 to F16 may be coupled to a plurality of word lines WL1 to WL 16. Among the memory cells included in the different strings ST, a group of memory cells coupled to each word line may be referred to as a physical page PPG. Accordingly, the number of physical pages PPG included in the memory block 11 may correspond to the number of word lines WL1 to WL 16.

Each memory cell may store 1 bit of data. The memory cell is commonly referred to as a single-level cell (SLC). In this case, each physical page PPG may store data of a single logical page LPG. The data of each logical page LPG may comprise data bits corresponding to the number of cells comprised in a single physical page PPG. Each memory cell may store 2 or more bits of data. The memory cell is commonly referred to as a multi-level cell (MLC). In this case, each physical page PPG may store data of two or more logical pages LPG.

Fig. 6 is a diagram illustrating an example of a memory block having a three-dimensional structure according to an embodiment of the present disclosure.

Referring to fig. 6, the memory cell array 10 may include a plurality of memory blocks MB1 through MBk (11). Each memory block 11 may include a plurality of strings ST11 to ST1m and ST21 to ST2 m. In an embodiment, each of the strings ST11 to ST1m and ST21 to ST2m may be formed in a "U" shape. In the first memory block MB1, m strings may be arranged in the row direction (i.e., X direction). Fig. 6 shows that two strings are arranged in the column direction (i.e., Y direction), but this is for descriptive purposes only. For example, three or more strings may be arranged in the column direction (Y direction).

Each of the plurality of strings ST11 to ST1m and ST21 to ST2m may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

The source selection transistor SST, the drain selection transistor DST, and the memory cells MC1 through MCn may have structures similar to each other. For example, each of the source selection transistor SST, the drain selection transistor DST, and the memory cells MC1 through MCn may include a channel layer, a tunnel insulation layer, a charge trapping layer, and a blocking insulation layer. For example, a post for providing a channel layer may be provided in each string. For example, a pillar for providing at least one of a channel layer, a tunnel insulating layer, a charge trapping layer, and a blocking insulating layer may be provided in each string.

The source select transistor SST of each string may be coupled between a source line SL and the memory cells MC1 through MCn.

In an embodiment, the source select transistors of the strings arranged in the same row may be coupled to a source select line extending in the row direction. The source select transistors of the strings arranged in different rows may be coupled to different source select lines. In fig. 6, the source select transistors of the strings ST 11-ST 1m in the first row may be coupled to a first source select line SSL 1. The source select transistors of strings ST 21-ST 2m in the second row may be coupled to a second source select line SSL 2.

In an embodiment, the source select transistors of strings ST 11-ST 1m and ST 21-ST 2m may be commonly coupled to a single source select line.

The first to nth memory cells MC1 to MCn in each string may be coupled between the source selection transistor SST and the drain selection transistor DST.

The first to nth memory cells MC1 to MCn may be divided into first to pth memory cells MC1 to MCp and p +1 to nth memory cells MCp +1 to MCn. The first to pth memory cells MC1 to MCp may be continuously arranged in the vertical direction (i.e., the Z direction), and coupled in series to each other between the source select transistor SST and the tunnel transistor PT. The p +1 th to nth memory cells MCp +1 to MCn may be continuously arranged in the vertical direction (Z direction) and coupled in series to each other between the pipe transistor PT and the drain select transistor DST. The first to pth memory cells MC1 to MCp and the p +1 to nth memory cells MCp +1 to MCn may be coupled to each other through a pipe transistor PT. The gates of the first to nth memory cells MC1 to MCn of each string may be coupled to the first to nth word lines WL1 to WLn, respectively.

In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. In the case where the dummy memory cell is disposed, the voltage or current of the corresponding string may be stably controlled. The gates of the pipe transistors PT of the respective strings may be coupled to the line PL.

The drain select transistor DST of each string may be coupled between a corresponding bit line and the memory cells MCp +1 to MCn. The strings arranged in the row direction may be coupled to respective drain select lines extending in the row direction. The drain select transistors of the strings ST 11-ST 1m in the first row may be coupled to a first drain select line DSL 1. The drain select transistors of the strings ST 21-ST 2m in the second row may be coupled to a second drain select line DSL 2.

The strings arranged in the column direction may be coupled to respective bit lines extending in the column direction. In fig. 6, the strings ST11 and ST21 in the first column may be coupled to a first bit line BL 1. The strings ST1m and ST2m in the mth column may be coupled to the mth bit line BLm.

In the strings arranged in the row direction, memory cells coupled to the same word line may form one page. For example, the memory cells in the strings ST 11-ST 1m of the first row, which are coupled to the first word line WL1, may form a single page. The memory cells in the strings ST 21-ST 2m of the second row, which are coupled to the first word line WL1, may form another single page. When any one of the drain select lines DSL1 and DSL2 is selected, strings arranged in the corresponding row may be selected. When any one of the word lines WL1 to WLn is selected, a corresponding single page may be selected from the selected string.

Fig. 7 is a diagram illustrating an example of a memory block having a three-dimensional structure according to an embodiment of the present disclosure.

Referring to fig. 7, memory cell array 10 may include a plurality of memory blocks MB1 through MBk (11). Each memory block 11 may include a plurality of strings ST11 'to ST1m' and ST21 'to ST2 m'. Each of the strings ST11 'to ST1m' and ST21 'to ST2m' may extend in the vertical direction (i.e., Z direction). In each memory block 11, m strings may be arranged in the row direction (i.e., X direction). Fig. 7 shows that two strings are arranged in the column direction (i.e., Y direction), but this is for descriptive purposes only. For example, three or more strings may be arranged in the column direction (Y direction).

Each of the strings ST11 'to ST1m' and ST21 'to ST2m' may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

The source select transistor SST of each string may be coupled between a source line SL and the memory cells MC1 through MCn. The source select transistors of strings arranged in the same row may be coupled to the same source select line. The source select transistors of the strings ST11 'to ST1m' arranged in the first row may be coupled to a first source select line SSL 1. The source select transistors of the strings ST21 'to ST2m' arranged in the second row may be coupled to a second source select line SSL 2. In an embodiment, the source select transistors of strings ST11 'to ST1m' and ST21 'to ST2m' may be commonly coupled to a single source select line.

The first to nth memory cells MC1 to MCn in each string may be coupled in series between the source selection transistor SST and the drain selection transistor DST. The gates of the first to nth memory cells MC1 to MCn may be coupled to the first to nth word lines WL1 to WLn, respectively.

In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. In the case where the dummy memory cell is disposed, the voltage or current of the corresponding string may be stably controlled. Thus, the reliability of the data stored in each memory block 11 can be improved.

The drain select transistor DST of each string may be coupled between a corresponding bit line and the memory cells MC1 through MCn. The drain select transistors DST of the strings arranged in the row direction may be coupled to respective drain select lines extending in the row direction. The drain select transistors DST of the strings ST11 'to ST1m' in the first row may be coupled to a first drain select line DSL 1. The drain select transistors DST of the strings ST21 'to ST2m' in the second row may be coupled to the second drain select line DSL 2.

FIG. 8 is a flow chart of a method of operating a memory system according to an embodiment of the present disclosure.

A method of operating a memory system according to an embodiment of the present disclosure will be described with reference to fig. 1 to 8.

In step S810, a Host command Host _ CMD and a logical address are received from the Host 1300 corresponding to the read operation.

In step S820, the processor 1220 of the controller 1200 generates a command queue in response to the Host command Host _ CMD, and maps a logical address to a physical address.

In response to the command queue, the flash control circuit 1250 generates an internal command CMD for controlling the memory device 1100 and transfers the internal command CMD and the mapped address ADD to the selected semiconductor memory 100 of the memory device 1100.

In step S830, in response to the internal command CMD and the mapped address ADD, the selected semiconductor memory 100 performs a read operation on a selected memory block (for example, MB1) among the plurality of memory blocks 11. The data read from the selected semiconductor memory 100 is temporarily stored in the read buffer 1233 of the controller 1200.

Subsequently, in step S840, the read count memory block 1222A of the read reclamation control block 1222 increments the read count value of the memory block MB1 of the semiconductor memory 100, which has performed the read operation, by 1, and checks the read count value of the memory block MB 1.

In step S850, the target block selection block 1222B compares the read count value of the memory block MB1 on which the read operation has been performed with the first preset value.

If the result of the comparison operation (S850) indicates that the read count value of the memory block MB1 on which the read operation has been performed is equal to or greater than the first preset value (yes), the read reclamation control block 1222 controls the flash memory control circuit 1250 to perform the read reclamation operation on the memory block MB 1.

For example, the target block selection block 1222B selects the memory block MB1 as a victim block to perform an RRC operation, and selects a memory block having an erase state among a plurality of memory blocks included in the selected semiconductor memory 100 of the memory device 1100 as a target memory block. In step S860, the read reclamation control unit 1222D controls the flash control circuit 1250 to perform the RRC operation, and the flash control circuit 1250 controls the memory device 1100 to copy data stored in the victim block and store the data in the target memory block, thereby performing the RRC operation.

The read data temporarily stored in the read buffer 1233 may be transferred to the host 1300 before or after the RRC operation is performed. Thereafter, a command response signal CMD _ response of the Host command Host _ CMD may be transmitted to the Host 1300. In response to the command response signal CMD _ response, the garbage collection control block 1320 of the host 1300 increases a read count value corresponding to a logical address at which the read operation has been completed.

If the result of the comparison operation (S850) indicates that the read count value of the memory block MB1 for which the read operation has been performed is less than the first preset value (no), the read count level determination block 1222C of the read reclamation control block 1222 determines the ratio of the read count value of the memory block MB1 with respect to the first preset value, and generates level information level _ info, in step S870. For example, the read count level determination block 1222C may: when the read count value of the memory block MB1 for which the read operation has been completed is less than 70% of the first preset value, generating the level information as a first level; generating the level information as a second level when the read count value is equal to or greater than 70% and less than 80% of the first preset value; generating the level information as a third level when the read count value is equal to or greater than 80% and less than 90% of the first preset value; and generates the level information as a fourth level when the read count value is equal to or greater than 90% of the first preset value.

In step S880, the FTL (1221 of fig. 2) matches the generated level information level _ info with a logical address corresponding to the memory block MB1, and outputs the matched level information level _ info to the Host 1300 together with a command response signal CMD _ response related to the Host command Host _ CMD.

In step S890, in response to the command response signal CMD _ response, the garbage collection control block 1320 of the host 1300 increases the read count value corresponding to each of the logical address LBAs for which the read operation has been completed, and in addition, in response to the level information level _ info, the garbage collection control block 1320 of the host 1300 weights the read count value of each of the logical address LBAs corresponding to the corresponding memory block MB 1.

For example, when the level information level _ info is the first level, the logical address LBA corresponding to the relevant memory block MB1 is not weighted. When the level information level _ info is the second level, the logical address LBA corresponding to the relevant memory block MB1 is weighted. Further, when the level information level _ info is the third level, the logical address LBA corresponding to the relevant memory block MB1 is selected as a logical address at which the GC operation is to be performed, and information on the address is transferred to the host processor 1310. In addition, when the level information level _ info is the fourth level, the logical address LBA corresponding to the relevant memory block MB1 is selected as an urgent logical address requiring immediate GC operation, and information about the address and the urgency is transferred to the host processor 1310.

In step S900, the garbage collection control block 1320 compares the read count value of each of all the logical address LBAs with a second preset value.

If the result of the comparison operation (S900) indicates that the read count value of the logical address is equal to or greater than the second preset value (yes), the corresponding logical address is determined as the logical address at which the GC operation is to be performed, and information about the address is transmitted to the host processor 1310.

If the result of the comparison operation (S900) indicates that the read count value of the logical address is less than the second preset value (no), the corresponding logical address is determined as a logical address where no GC operation is performed.

In step S910, when the number of logical addresses selected as objects of the GC operation by the garbage collection control block 1320 is equal to or greater than a preset value, the Host processor 1310 may generate a Host command Host _ CMD corresponding to the GC operation of the selected logical addresses. Further, if information on a logical address selected by the garbage collection control block 1320 as an urgent logical address to perform an immediate GC operation is received, the Host processor 1310 may immediately generate a Host command Host _ CMD corresponding to the GC operation of the urgent logical address and output the Host command Host _ CMD to the controller 1200 together with the urgent logical address.

In response to a Host command Host _ CMD received from the Host 1300 corresponding to the GC operation, the processor 1220 of the controller 1200 generates a command queue corresponding to the GC operation. The processor 1220 may check a physical address corresponding to the logical address received together with the Host command Host _ CMD, and control the flash control circuit 1250 to select a memory block indicated by the checked physical address as a victim block and perform a GC operation on the selected memory block. In step S920, under the control of the flash memory control circuit 1250, the memory device 1100 performs a GC operation by copying valid data stored in a memory block selected as a victim block and storing the valid data in a memory block selected as a target block.

Thereafter, data stored in the plurality of memory blocks selected as the victim block may be erased.

In various embodiments of the present disclosure, a read reclamation operation is performed based on a read count value of a memory block on which the read operation has been performed under the control of the controller 1200. For a garbage collection operation performed under the control of the host 1300, the read count value of each of the logical addresses is weighted based on the read count value of the memory block, and the logical address at which the GC operation is to be performed is selected. Accordingly, the garbage collection operation is performed before the read reclamation operation of the corresponding memory block is performed, so that the read reclamation operation may not be performed on the memory device performing the garbage collection operation.

Fig. 9 is a diagram illustrating a memory system 30000 according to an embodiment of the present disclosure.

Referring to fig. 9, the memory system 30000 may be implemented in a cellular phone, a smart phone, a tablet PC, a Personal Digital Assistant (PDA), or a wireless communication device. The memory system 30000 can include a memory device 1100 and a controller 1200 capable of controlling the operation of the memory device 1100. The controller 1200 may control data access operations, such as program operations, erase operations, or read operations, of the memory device 1100 under the control of the processor 3100.

Data programmed into memory device 1100 may be output through display 3200 under the control of controller 1200.

The radio transceiver 3300 may transmit and receive a radio signal through an antenna ANT. For example, the radio transceiver 3300 may change a radio signal received through the antenna ANT into a signal that can be processed in the processor 3100. Accordingly, the processor 3100 may process a signal output from the radio transceiver 3300 and transmit the processed signal to the controller 1200 or the display 3200. The controller 1200 may program signals processed by the processor 3100 to the memory device 1100. Further, the radio transceiver 3300 may change a signal output from the processor 3100 into a radio signal and output the changed radio signal to an external device through an antenna ANT. The input device 3400 may be used to input a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 may be implemented in a pointing device such as a touch pad, a computer mouse, a keypad, or a keyboard. The processor 3100 may control the operation of the display 3200 such that data output from the memory controller 1200, data output from the radio transceiver 3300, or data output from the input device 3400 is output through the display 3200.

In an embodiment, the controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 3100 or a chip provided separately from the processor 3100. Alternatively, the controller 1200 may be implemented by the example of the controller shown in fig. 2.

Fig. 10 is a diagram illustrating a memory system 40000 according to an embodiment of the present disclosure.

Referring to fig. 10, the memory system 40000 may be implemented in a Personal Computer (PC), a tablet PC, a netbook, an e-reader, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), an MP3 player, or an MP4 player.

The memory system 40000 may include a memory device 1100 and a controller 1200 capable of controlling data processing operations of the memory device 1100.

The processor 4100 may output data stored in the memory device 1100 through the display 4300 according to data input from the input device 4200. For example, the input device 4200 may be implemented in a pointing device such as a touch pad, computer mouse, keypad, or keyboard.

The processor 4100 may control the overall operation of the memory system 40000 and control the operation of the controller 1200. In an embodiment, the controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 4100 or a chip provided separately from the processor 4100. Alternatively, the controller 1200 may be implemented by the example of the controller shown in fig. 2.

Fig. 11 is a diagram illustrating a memory system 50000 according to an embodiment of the present disclosure.

Referring to fig. 11, the memory system 50000 may be implemented in an image processing apparatus such as a digital camera, a portable phone provided with a digital camera, a smart phone provided with a digital camera, or a tablet PC provided with a digital camera.

The memory system 50000 may include a memory device 1100 and a controller 1200, the controller 1200 being capable of controlling data processing operations of the memory device 1100, such as a program operation, an erase operation, or a read operation.

The image sensor 5200 of the memory system 50000 may convert the optical image to a digital signal. The converted digital signal may be transmitted to the processor 5100 or the controller 1200. The converted digital signal may be output through the display 5300 or stored in the memory device 1100 through the controller 1200 under the control of the processor 5100. Data stored in the memory device 1100 may be output through the display 5300 under the control of the processor 5100 or the controller 1200.

In embodiments, the controller 1200, which is capable of controlling the operation of the memory device 1100, may be implemented as part of the processor 5100 or as a chip provided separately from the processor 5100. Alternatively, the controller 1200 may be implemented by the example of the controller shown in fig. 2.

Fig. 12 is a diagram illustrating a memory system 70000 according to an embodiment of the present disclosure.

Referring to fig. 12, the memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory apparatus 1100, a controller 1200, and a card interface 7100.

The controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. In an embodiment, the card interface 7100 may be a Secure Digital (SD) card interface or a multimedia card (MMC) interface, but is not limited thereto. The controller 1200 may be implemented by an example of the controller 1200 shown in fig. 2.

The card interface 7100 may interface the host 60000 and the controller 1200 according to the protocol of the host 60000 to enable data exchange between the host 60000 and the controller 1200. In an embodiment, the card interface 7100 may support a Universal Serial Bus (USB) protocol and an inter-chip (IC) -USB protocol. Here, the card interface may refer to hardware capable of supporting a protocol used by the host 60000, software installed in hardware, or a signal transfer scheme.

When the memory system 70000 is connected to a host interface 6200 of a host 60000 such as a PC, a tablet PC, a digital camera, a digital audio player, a cellular phone, console video game hardware, or a digital set-top box, the host interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the controller 1200 under the control of the microprocessor 6100.

As described above, in various embodiments of the present disclosure, a read reclamation operation is performed based on a read count value of a memory block on which the read operation has been performed. Selecting a logical address at which a garbage collection operation is to be performed based on the read count value of each of the logical addresses and the read count value of the memory block. Therefore, the read recovery operation and the garbage collection operation can be prevented from overlapping each other.

Although embodiments of the present disclosure have been disclosed, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure.

The scope of the disclosure is, therefore, indicated by the appended claims and their equivalents, rather than by the foregoing description.

In the embodiments discussed above, all steps may be selectively performed or skipped. In addition, the steps in each embodiment may not always be performed in the conventional order. Furthermore, the embodiments disclosed in the present specification and drawings are intended to help those skilled in the art clearly understand the present disclosure, and are not intended to limit the scope of the present disclosure. In other words, those skilled in the art to which the present disclosure pertains will readily understand that various modifications are possible based on the technical scope of the present disclosure.

Embodiments of the present disclosure have been described with reference to the accompanying drawings, and specific terms or words used in the specification should be construed in accordance with the spirit of the present disclosure, without limiting the subject matter of the present disclosure. It should be understood that many variations and modifications of the basic inventive concepts described herein will still fall within the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.