阅读说明：本技术 一种基于等效电路模型的集成电路ibis模型提取方法及系统 (Integrated circuit IBIS model extraction method and system based on equivalent circuit model ) 是由 唐章宏 邹军 汲亚飞 黄承清 王芬 于 2020-08-06 设计创作，主要内容包括：本发明提供了一种基于等效电路模型的集成电路IBIS模型提取方法及系统,方法包括：获取集成电路无源部分的多层集成电路版图信息,设置提取相关参数和仿真参数；对多层集成电路无源部分识别其金属层-介质形成的平行平板场域并进行网格剖分,计算电磁场；定义无源部分的多端口网络,根据无源部分多端口和多层集成电路的电磁场,计算无源部分多端口网络的散射参数,将散射参数转换为无源部分的SPICE模型；如果是有源模型,将有源部分的SPICE模型与无源SPICE模型通过耦合节点合并成新的SPICE模型；将SPICE模型转换为IBIS模型。能够根据用户不同的需求,来设置IC封装网络的IBIS模型提取相关参数和仿真参数,具有IBIS模型的提取完整度高、提取效率高、仿真精确性高等优点。(The invention provides an integrated circuit IBIS model extraction method and system based on an equivalent circuit model, wherein the method comprises the following steps: acquiring multilayer integrated circuit layout information of a passive part of an integrated circuit, and setting and extracting relevant parameters and simulation parameters; identifying a parallel flat plate field formed by metal layers and media of a passive part of the multilayer integrated circuit, meshing and calculating an electromagnetic field; defining a multiport network of a passive part, calculating scattering parameters of the multiport network of the passive part according to electromagnetic fields of multiport and multilayer integrated circuits of the passive part, and converting the scattering parameters into an SPICE model of the passive part; if the active part is the active part, combining the SPICE model of the active part and the passive SPICE model into a new SPICE model through a coupling node; and converting the SPICE model into an IBIS model. The IBIS model of the IC packaging network can be set to extract relevant parameters and simulation parameters according to different requirements of users, and the method has the advantages of high extraction integrity, high extraction efficiency, high simulation accuracy and the like of the IBIS model.)

1. An integrated circuit IBIS model extraction method based on an equivalent circuit model is characterized by comprising the following steps:

s1: acquiring multilayer integrated circuit layout information of a passive part of an integrated circuit, and setting relevant parameters and simulation parameters extracted by an IBIS model;

s2: aligning and simplifying polygons of the multilayer integrated circuit layout according to the multilayer integrated circuit layout information; according to the alignment and simplification of polygons of the multilayer integrated circuit layout, identifying parallel flat plate fields formed by metal layers and media of the multilayer integrated circuit layout, and meshing the parallel flat plate fields; calculating the electromagnetic field of the multilayer integrated circuit according to the mesh subdivision of the multilayer integrated circuit layout;

s3: judging whether the IBIS model to be extracted is an active model, if so, executing a step S4, otherwise, executing a step S5;

s4: obtaining an SPICE model of an active device of the integrated circuit, and taking the SPICE model as an SPICE model of an active part of the integrated circuit; based on the node of the integrated circuit active part and the passive part multilayer integrated circuit layout coupling and the defined IBIS model port, defining the multiport network of the passive part, calculating the scattering parameters of the multiport network of the passive part according to the electromagnetic fields of the multiport and multilayer integrated circuit of the passive part, and converting the scattering parameters into the SPICE model of the passive part; coupling the SPICE model of the active part and the SPICE model of the passive part at the coupled nodes to form a new SPICE model, converting the new SPICE model into an IBIS model, and then executing the step S6;

s5: defining a multiport network of a passive part based on ports of an IBIS model, calculating scattering parameters of the multiport network of the passive part according to electromagnetic fields of multiport of the passive part and a multilayer integrated circuit, and converting the scattering parameters into an SPICE model of the passive part; converting the SPICE model of the passive part into an IBIS model;

s6: and outputting and graphically displaying the calculation result.

2. The method for extracting the IBIS model of the integrated circuit based on the equivalent circuit model according to claim 1, wherein the step of coupling the SPICE model of the active part and the SPICE model of the passive part at the coupled nodes to form a new SPICE model comprises the following steps:

the SPICE model of the active part and the SPICE model of the passive part have respective model parameters including the serial number of the circuit node connected with the model port, and the SPICE model of the active part and the SPICE model of the passive part are coupled through the common circuit node between the models; after the coupling is completed, other nodes except the common circuit node in the SPICE model of the active part or the SPICE model of the passive part are numbered again to form circuit nodes with non-repeated numbers, and therefore the circuit nodes are combined into a new SPICE model.

3. The equivalent circuit model-based integrated circuit IBIS model extraction method of claim 1, wherein the multilayer integrated circuit layout information comprises layer information, layout shape information, and interconnection information between layers and layouts of the integrated circuit layout.

4. The IBIS model extraction method of claim 1, wherein the IBIS model extraction related parameters include selecting a package type to be extracted, setting a port network to be extracted and setting an extraction frequency range, the package type includes but is not limited to ball grid array package and flip chip package; simulation parameters include, but are not limited to, stack, solder ball, dielectric layer parameters, and setup output control.

5. The method for extracting the IBIS model of the integrated circuit based on the equivalent circuit model according to claim 1, wherein the aligning and simplifying process is performed on the polygons of the multi-layer integrated circuit layout according to the integrated circuit layout information, and specifically comprises the following steps:

acquiring a plurality of polygons of a multilayer integrated circuit layout, wherein the polygons comprise a plurality of vertexes;

vertically projecting a plurality of polygons of each layer to the same layer, and forming a Delaunay triangular mesh with polygon vertexes as mesh nodes according to a Delaunay triangulation algorithm, wherein each side of the polygons comprises preset polygon number information;

aligning the Delaunay triangular mesh to each side of the plurality of polygons according to a side exchange method, simultaneously calculating intersection points of the sides of the polygons, and adding the intersection points as vertexes of the polygons and nodes of the Delaunay triangular mesh to form a first triangular mesh;

forming an inner auxiliary polygon P0 and an outer auxiliary polygon P9 sandwiching each polygon P inside and outside the polygon P, respectively, based on the first triangular mesh, and controlling the distances of the inner auxiliary polygon, the outer auxiliary polygon and the polygon P by a set distance threshold;

and aligning and simplifying the sides of each layer of polygons between the inner auxiliary polygon and the outer auxiliary polygon, and restoring the multi-layer polygons projected to the same layer into each layer according to polygon number information contained in the sides of each polygon.

6. The method for extracting the IBIS model of the integrated circuit based on the equivalent circuit model according to claim 1, wherein the method comprises the following steps of identifying the parallel flat plate field formed by the metal layer and the medium of the multilayer integrated circuit layout according to the alignment and simplification of the polygons of the multilayer integrated circuit layout, and performing the non-structural adaptive mesh subdivision on the parallel flat plate field:

acquiring a plurality of polygons of a multilayer integrated circuit layout, wherein the polygons comprise a plurality of vertexes;

vertically projecting a plurality of polygons of each layer to the same layer, and forming a Delaunay triangular mesh with polygon vertexes as mesh nodes according to a Delaunay triangulation algorithm, wherein each side of each polygon comprises preset polygon information of the polygon and layer information of the layer where the polygon is located;

merging the polygon information and layer information of the projected and overlapped polygon edges;

aligning the Delaunay triangular mesh to each side of the polygons according to a side exchange method, simultaneously calculating intersection points of the polygon sides and adding the intersection points as vertexes of the polygons and nodes of the Delaunay triangular mesh to form a first triangular mesh, wherein the side exchange method sorts the sides of the polygons meeting conditions to form a set, takes out the sides of the polygons according to the sort, and finishes the exchange if the set is an empty set after the exchange is carried out on the sides of the polygons;

based on the first triangular mesh, layer information of each polygon edge is superposed to all triangles in each polygon based on Boolean operation;

identifying and collecting the triangular edges and the polygonal edges contained in each parallel flat plate field by a parallel flat plate field identification method according to the layer information of the triangular edges and the polygonal edges;

and according to the calculation precision requirement and the common edges of different parallel flat plate fields, carrying out self-adaptive mesh subdivision processing on the triangles in each parallel flat plate field.

7. An integrated circuit IBIS model extraction system based on an equivalent circuit model, the system comprising:

the acquisition module is used for acquiring the layout information of the multilayer integrated circuit of the passive part of the integrated circuit and acquiring the SPICE model of the active device;

the parameter setting module is used for setting relevant parameters and simulation parameters extracted by the IBIS model;

the first information processing module is used for aligning and simplifying the polygons of the multilayer integrated circuit layout according to the integrated circuit layout information;

the second information processing module is used for identifying a parallel flat plate field formed by metal layers and media of the multilayer integrated circuit layout according to the alignment and simplification of polygons of the multilayer integrated circuit layout and carrying out mesh subdivision on the parallel flat plate field;

the third information processing module is used for calculating the electromagnetic field of the multilayer integrated circuit according to the mesh subdivision of the multilayer integrated circuit layout;

the judgment module is used for judging whether the IBIS model to be extracted is an active model or not;

the fourth information processing module is used for obtaining the SPICE model of the active device of the integrated circuit and taking the SPICE model as the SPICE model of the active part of the integrated circuit; based on the node of the integrated circuit active part and the passive part multilayer integrated circuit layout coupling and the defined IBIS model port, defining the multiport network of the passive part, calculating the scattering parameters of the multiport network of the passive part according to the electromagnetic fields of the multiport and multilayer integrated circuit of the passive part, and converting the scattering parameters into the SPICE model of the passive part; coupling the SPICE model of the active part and the SPICE model of the passive part at coupled nodes to form a new SPICE model, and converting the new SPICE model into an IBIS model;

the fifth information processing module is used for defining a multiport network of the passive part based on the IBIS model ports, calculating scattering parameters of the multiport network of the passive part according to electromagnetic fields of multiport of the passive part and the multilayer integrated circuit, and converting the scattering parameters into an SPICE model of the passive part; converting the SPICE model of the passive part into an IBIS model;

and the output display module is used for outputting the calculation result and displaying the calculation result in a graphical mode.

8. The integrated circuit IBIS model extraction system based on equivalent circuit model as claimed in claim 7, wherein said coupling SPICE model of active part and SPICE model of passive part at coupled node to form new SPICE model, comprises the following steps:

the SPICE model of the active part and the SPICE model of the passive part have respective model parameters including the serial number of the circuit node connected with the model port, and the SPICE model of the active part and the SPICE model of the passive part are coupled through the common circuit node between the models; after the coupling is completed, other nodes except the common circuit node in the SPICE model of the active part or the SPICE model of the passive part are numbered again to form circuit nodes with non-repeated numbers, and therefore the circuit nodes are combined into a new SPICE model.

9. The integrated circuit IBIS model extraction system based on equivalent circuit model as claimed in claim 7, wherein said multi-layer integrated circuit layout information comprises layer information, layout shape information, and interconnection information between layers and layouts of the integrated circuit layout.

10. The IBIS model extraction system of claim 7, wherein the IBIS model extraction related parameters include selecting a package type to be extracted, setting a port network to be extracted, and setting an extraction frequency range, the package type including but not limited to ball grid array package and flip chip package; simulation parameters include, but are not limited to, stack, solder ball, dielectric layer parameters, and setup output control.

Technical Field

The invention relates to the technical field of integrated circuit IBIS model extraction, in particular to an integrated circuit IBIS model extraction method and system based on an equivalent circuit model.

Background

The equivalent circuit is characterized in that a port formed by a relatively complex structure of a part of the circuit at a coupled node is replaced by a simple structure, and the replaced circuit and the original complex structure keep the same action and effect on an external circuit when viewed from the port. For example, the volt-ampere relationships of two-terminal networks are identical, and the corresponding circuits of the two networks are equivalent. The equivalent two networks may have completely different structures inside, but they have completely the same response to the external circuit.

An IBIS (Input/Output Buffer Information Specification) model is a method for quickly and accurately modeling an Input/Output (I/O) Buffer based on a voltage/current (V/I) curve, is an international standard reflecting chip driving and receiving electrical characteristics, provides a standard file format for recording parameters such as driving source Output impedance, rising/falling time, Input load and the like, and is very suitable for calculating and simulating high-frequency effects such as oscillation and crosstalk. IBIS can be used to characterize the input, output and I/O Buffer behavior of an IC device, to simulate the interaction of the Buffer with the on-board circuitry.

Spice (simulation program with integrated circuit emulation) is the most common circuit-level simulation program, various software manufacturers provide different versions of spice software such as Vspice, Hspice and Pspice, and the simulation cores of the spice software are the same and different, and the spice simulation algorithm developed by Berkeley university, Calif. is adopted. The SPICE model is based on the working principle of the components and based on the model parameters and the mode equations of the components and based on the basic components (such as transistors, resistors, capacitors and the like) of the circuit, and can mathematically predict the electrical behavior of the components under different conditions.

And aiming at IC packaging, extracting models of all networks or part of networks in the packaging design according to user requirements, and generating a standard IBIS format packaging model. Wherein, the whole network refers to the whole packaged network, namely the network formed by packaging all pins; the partial network refers to a network corresponding to different functional modules in the package, such as a power supply network, a network formed by correspondingly packaging all power supply pins, and a signal network is a network formed by packaging all signal pins. The IBIS model generally comprises two parts, one part is a Buffer active model, and the other part is a passive encapsulation part outside the Buffer. Currently, the integrated circuit IBIS model extraction has the following problems: 1. IBIS model extraction parameters of the IC package network are broadly fixed. 2. How to extract a Buffer active model and a passive encapsulation part outside the Buffer, how to fuse the active encapsulation model and the passive encapsulation model, and how to convert the SPICE model into the IBIS model. 3. In the prior art, the accuracy, integrity and high efficiency of field identification and grid subdivision processing of an integrated circuit layout cannot be guaranteed, and the accuracy and efficiency of processing results are low. 4. In the prior art, the alignment and simplification processing of a plurality of polygons of a multilayer integrated circuit layout is only simplified aiming at a single-layer polygon, the problem of fragmentation after the formation of a parallel flat plate field by the multilayer polygons is not processed, and the overlapping problem of polygons at two sides of a gap is not considered when the simplification processing is only carried out aiming at a single polygon.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, the present invention aims to: the method comprises the steps of aligning and simplifying polygons of a multilayer integrated circuit layout, meshing parallel flat plate field areas formed by metal layers and media, calculating electromagnetic field distribution of the multilayer integrated circuit, and extracting and coupling a Buffer active part and a Buffer passive part. The IBIS model of the IC packaging network can be set to extract relevant parameters and simulation parameters according to different requirements of users, and the method has the advantages of high extraction integrity, high extraction efficiency, high simulation accuracy and the like of the IBIS model.

An integrated circuit IBIS model extraction method based on an equivalent circuit model comprises the following steps:

s1: acquiring multilayer integrated circuit layout information of a passive part of an integrated circuit, and setting relevant parameters and simulation parameters extracted by an IBIS model;

s2: aligning and simplifying polygons of the multilayer integrated circuit layout according to the multilayer integrated circuit layout information; according to the alignment and simplification of polygons of the multilayer integrated circuit layout, identifying parallel flat plate fields formed by metal layers and media of the multilayer integrated circuit layout, and meshing the parallel flat plate fields; calculating the electromagnetic field of the multilayer integrated circuit according to the mesh subdivision of the multilayer integrated circuit layout;

s3: judging whether the IBIS model to be extracted is an active model, if so, executing a step S4, otherwise, executing a step S5;

s4: obtaining an SPICE model of an active device of the integrated circuit, and taking the SPICE model as an SPICE model of an active part of the integrated circuit; based on the node of the integrated circuit active part and the passive part multilayer integrated circuit layout coupling and the defined IBIS model port, defining the multiport network of the passive part, calculating the scattering parameters of the multiport network of the passive part according to the electromagnetic fields of the multiport and multilayer integrated circuit of the passive part, and converting the scattering parameters into the SPICE model of the passive part; coupling the SPICE model of the active part and the SPICE model of the passive part at the coupled nodes to form a new SPICE model, converting the new SPICE model into an IBIS model, and then executing the step S6;

s5: defining a multiport network of a passive part based on ports of an IBIS model, calculating scattering parameters of the multiport network of the passive part according to electromagnetic fields of multiport of the passive part and a multilayer integrated circuit, and converting the scattering parameters into an SPICE model of the passive part; converting the SPICE model of the passive part into an IBIS model;

s6: and outputting and graphically displaying the calculation result.

Further, the coupling the SPICE model of the active part and the SPICE model of the passive part at the coupled node to form a new SPICE model specifically includes the following steps:

the SPICE model of the active part and the SPICE model of the passive part have respective model parameters including the serial number of the circuit node connected with the model port, and the SPICE model of the active part and the SPICE model of the passive part are coupled through the common circuit node between the models; after the coupling is completed, other nodes except the common circuit node in the SPICE model of the active part or the SPICE model of the passive part are numbered again to form circuit nodes with non-repeated numbers, and therefore the circuit nodes are combined into a new SPICE model.

Further, the multilayer integrated circuit layout information includes layer information, layout shape information, and interconnection information between layers and layouts of the integrated circuit layout.

Further, the IBIS model extracts relevant parameters including selecting a package type to be extracted, setting a port network to be extracted and setting an extraction frequency range, wherein the package type includes but is not limited to a ball grid array package and a flip chip package; simulation parameters include, but are not limited to, stack, solder ball, dielectric layer parameters, and setup output control.

Further, the aligning and simplifying processing of the polygons of the multilayer integrated circuit layout according to the integrated circuit layout information specifically includes the following steps:

acquiring a plurality of polygons of a multilayer integrated circuit layout, wherein the polygons comprise a plurality of vertexes;

vertically projecting a plurality of polygons of each layer to the same layer, and forming a Delaunay triangular mesh with polygon vertexes as mesh nodes according to a Delaunay triangulation algorithm, wherein each side of the polygons comprises preset polygon number information;

aligning the Delaunay triangular mesh to each side of the plurality of polygons according to a side exchange method, simultaneously calculating intersection points of the sides of the polygons, and adding the intersection points as vertexes of the polygons and nodes of the Delaunay triangular mesh to form a first triangular mesh;

forming an inner auxiliary polygon P0 and an outer auxiliary polygon P9 sandwiching each polygon P inside and outside the polygon P, respectively, based on the first triangular mesh, and controlling the distances of the inner auxiliary polygon, the outer auxiliary polygon and the polygon P by a set distance threshold;

and aligning and simplifying the sides of each layer of polygons between the inner auxiliary polygon and the outer auxiliary polygon, and restoring the multi-layer polygons projected to the same layer into each layer according to polygon number information contained in the sides of each polygon.

Further, according to the alignment and simplification of the polygons of the multilayer integrated circuit layout, identifying the parallel flat plate field formed by the metal layer and the medium of the multilayer integrated circuit layout, and performing non-structural adaptive mesh subdivision on the parallel flat plate field, specifically comprising the following steps:

acquiring a plurality of polygons of a multilayer integrated circuit layout, wherein the polygons comprise a plurality of vertexes;

vertically projecting a plurality of polygons of each layer to the same layer, and forming a Delaunay triangular mesh with polygon vertexes as mesh nodes according to a Delaunay triangulation algorithm, wherein each side of each polygon comprises preset polygon information of the polygon and layer information of the layer where the polygon is located;

merging the polygon information and layer information of the projected and overlapped polygon edges;

aligning the Delaunay triangular mesh to each side of the polygons according to a side exchange method, simultaneously calculating intersection points of the polygon sides and adding the intersection points as vertexes of the polygons and nodes of the Delaunay triangular mesh to form a first triangular mesh, wherein the side exchange method sorts the sides of the polygons meeting conditions to form a set, takes out the sides of the polygons according to the sort, and finishes the exchange if the set is an empty set after the exchange is carried out on the sides of the polygons;

based on the first triangular mesh, layer information of each polygon edge is superposed to all triangles in each polygon based on Boolean operation;

identifying and collecting the triangular edges and the polygonal edges contained in each parallel flat plate field by a parallel flat plate field identification method according to the layer information of the triangular edges and the polygonal edges;

and according to the calculation precision requirement and the common edges of different parallel flat plate fields, carrying out self-adaptive mesh subdivision processing on the triangles in each parallel flat plate field.

An integrated circuit IBIS model extraction system based on an equivalent circuit model, the system comprising:

the acquisition module is used for acquiring the layout information of the multilayer integrated circuit of the passive part of the integrated circuit and acquiring the SPICE model of the active device;

the parameter setting module is used for setting relevant parameters and simulation parameters extracted by the IBIS model;

the first information processing module is used for aligning and simplifying the polygons of the multilayer integrated circuit layout according to the integrated circuit layout information;

the second information processing module is used for identifying a parallel flat plate field formed by metal layers and media of the multilayer integrated circuit layout according to the alignment and simplification of polygons of the multilayer integrated circuit layout and carrying out mesh subdivision on the parallel flat plate field;

the third information processing module is used for calculating the electromagnetic field of the multilayer integrated circuit according to the mesh subdivision of the multilayer integrated circuit layout;

the judgment module is used for judging whether the IBIS model to be extracted is an active model or not;

the fourth information processing module is used for obtaining the SPICE model of the active device of the integrated circuit and taking the SPICE model as the SPICE model of the active part of the integrated circuit; based on the node of the integrated circuit active part and the passive part multilayer integrated circuit layout coupling and the defined IBIS model port, defining the multiport network of the passive part, calculating the scattering parameters of the multiport network of the passive part according to the electromagnetic fields of the multiport and multilayer integrated circuit of the passive part, and converting the scattering parameters into the SPICE model of the passive part; coupling the SPICE model of the active part and the SPICE model of the passive part at coupled nodes to form a new SPICE model, and converting the new SPICE model into an IBIS model;

the fifth information processing module is used for defining a multiport network of the passive part based on the IBIS model ports, calculating scattering parameters of the multiport network of the passive part according to electromagnetic fields of multiport of the passive part and the multilayer integrated circuit, and converting the scattering parameters into an SPICE model of the passive part; converting the SPICE model of the passive part into an IBIS model;

and the output display module is used for outputting the calculation result and displaying the calculation result in a graphical mode.

Further, the coupling the SPICE model of the active part and the SPICE model of the passive part at the coupled node to form a new SPICE model specifically includes the following steps:

the SPICE model of the active part and the SPICE model of the passive part have respective model parameters including the serial number of the circuit node connected with the model port, and the SPICE model of the active part and the SPICE model of the passive part are coupled through the common circuit node between the models; after the coupling is completed, other nodes except the common circuit node in the SPICE model of the active part or the SPICE model of the passive part are numbered again to form circuit nodes with non-repeated numbers, and therefore the circuit nodes are combined into a new SPICE model.

Further, the multilayer integrated circuit layout information includes layer information, layout shape information, and interconnection information between layers and layouts of the integrated circuit layout.

Further, the IBIS model extracts relevant parameters including selecting a package type to be extracted, setting a port network to be extracted and setting an extraction frequency range, wherein the package type includes but is not limited to a ball grid array package and a flip chip package; simulation parameters include, but are not limited to, stack, solder ball, dielectric layer parameters, and setup output control.

Compared with the prior art, the invention has the following advantages:

the invention provides an integrated circuit IBIS model extraction method and system based on an equivalent circuit model, which are characterized in that polygons of a multilayer integrated circuit layout are aligned and simplified, a parallel flat plate field formed by a metal layer and a medium is subjected to grid subdivision, so that electromagnetic field distribution of a multilayer integrated circuit is calculated, then a Buffer active part and a Buffer passive part are extracted and coupled, a coupled SPICE model is converted into an IBIS model, and the calculation result is output and graphically displayed. The method and the system can set the IBIS model of the IC packaging network to extract relevant parameters and simulation parameters according to different requirements of users, and have the advantages of high extraction integrity, high extraction efficiency, high simulation accuracy and the like of the IBIS model.

Drawings

FIG. 1 is a first control flow chart of an IBIS model extraction of an integrated circuit based on an equivalent circuit model according to an embodiment;

FIG. 2 is a second control flow diagram of the IBIS model extraction of the integrated circuit based on the equivalent circuit model according to the first embodiment;

FIG. 3 is a circuit diagram of an active SPICE model in an embodiment;

FIG. 4 is a circuit diagram of a passive SPICE model for integrated circuit scattering parameter S transformation in an embodiment;

FIG. 5 is a circuit diagram illustrating the coupling of an active SPICE model and a passive SPICE model in an embodiment;

FIG. 6 is a schematic diagram of a partial same polygon, projection to the same layer, and partial enlargement of a multi-layer metal layer according to an embodiment;

FIG. 7 is a schematic diagram of a field formed by multiple metal layers and a dielectric layer and its fragments in an embodiment;

FIG. 8 is a system block diagram of the IBIS model extraction of the integrated circuit based on the equivalent circuit model in the second embodiment.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and therefore are only examples, and the protection scope of the present invention is not limited thereby.