阅读说明：本技术 一种高频硅锗异质结双极晶体管及其制造方法 (High-frequency silicon-germanium heterojunction bipolar transistor and manufacturing method thereof ) 是由 王冠宇 刘培培 文剑豪 周春宇 魏进希 宋琦 王巍 肖渝 于 2020-07-06 设计创作，主要内容包括：本发明涉及一种高频硅锗异质结双极晶体管及其制造方法,属于电子技术领域。在单晶Si衬底上淀积埋氧化层；在基极窗口所对应的集电区的位置进行硼离子注入,并执行快速退火操作以消除晶格损伤；在集电区的一端刻蚀出凹槽形成STI隔离区,淀积填充重掺杂的Si材料；在基区的Ge组分采用阶梯型分布；在单晶Si薄层上淀积N+多晶硅作为发射极；在多晶Si发射极层、单晶Si薄层和基区SiGe薄层的两侧覆盖一层Si<Sub>3</Sub>N<Sub>4</Sub>应力膜,在发射区和基区同时引入单轴应力；光刻集电极、发射极和基极以外的金属,形成引线。本发明中在发射区和基区同时引入了单轴压应力,提高了载流子的迁移率和器件的频率特性,满足太赫兹频段对核心器件性能的要求。(The invention relates to a high-frequency silicon-germanium heterojunction bipolar transistor and a manufacturing method thereof, belonging to the technical field of electronics. Depositing a buried oxide layer on a single crystal Si substrate; injecting boron ions at the position of the collector region corresponding to the base electrode window, and performing rapid annealing operation to eliminate lattice damage; etching a groove at one end of the collector region to form an STI isolation region, and depositing and filling a heavily doped Si material; the Ge component in the base region is distributed in a step shape; depositing N + polycrystalline silicon on the single crystal Si thin layer to be used as an emitter; covering a layer of Si on two sides of the polycrystalline Si emitter layer, the single crystal Si thin layer and the base SiGe thin layer 3 N 4 The stress film introduces uniaxial stress to the emitter region and the base region simultaneously; and photoetching metal except the collector, the emitter and the base to form a lead. The invention introduces single axis into the emitter region and the base region simultaneouslyThe compressive stress improves the mobility of current carriers and the frequency characteristics of the device, and meets the requirements of the terahertz frequency band on the performance of the core device.)

1. A high frequency silicon germanium heterojunction bipolar transistor, characterized by: comprises the steps of (a) preparing a mixture of a plurality of raw materials,

a substrate having a crystal plane of (100) single crystal Si;

a buried oxide layer is deposited on the single crystal Si substrate, and the single crystal Si substrate and the Si material of the collector region form an SOI structure;

boron ions are injected into the position of the collector region corresponding to the base electrode window;

one end of the collector region is etched with a groove I to form an STI isolation region, and a groove II is etched and filled with a heavily doped Si material;

ge component of the base region distributed in a ladder shape;

a single crystal Si thin layer is deposited above the base region and is used as a cap layer;

n + polycrystalline silicon is deposited on the single crystal Si thin layer to be used as an emitter;

PECVD deposition of high-stress capping layer Si using dual-frequency radio frequency power supply₃N₄A material etched with an emitter window and a base window;

the outer base region part except the SiGe base region is positioned in the substrate to improve the amplification factor and the frequency of the device.

2. A high frequency silicon germanium heterojunction bipolar transistor as claimed in claim 1, wherein: an SOI SiGe HBT heterojunction bipolar transistor structure with uniaxial compressive stress at the base region is deposited with a high-stress covering layer Si by using a double-frequency radio frequency power supply PECVD₃N₄The material transfers intrinsic stress to the field of an emitter region and a base region and the surface of a collector region, and applied stress changes the energy band structure of a device and enhances the mobility of current carriers;

meanwhile, the lattice constants of Si and Ge are different, so that the base region of the high-frequency silicon-germanium heterojunction bipolar transistor is affected by Si₃N₄Uniaxial stress caused by the material and biaxial stress caused by the substrate act to form a uniaxial strain emitter region and a composite strain base region.

3. A method for manufacturing a high-frequency silicon-germanium heterojunction bipolar transistor is characterized in that: the method comprises the following steps:

selecting a single crystal Si substrate with a crystal face of (100);

depositing a buried oxide layer on the single crystal Si substrate to enable the buried oxide layer, the single crystal Si substrate and the Si material of the collecting region to form an SOI structure;

injecting boron ions at the position of the collector region corresponding to the base electrode window, and performing rapid annealing operation to eliminate lattice damage;

etching a groove at one end of the collector region to form an STI isolation region, etching a groove again, and depositing and filling a heavily doped Si material;

the Ge component in the base region is distributed in a step shape;

depositing a single crystal Si thin layer above the base region to be used as a cap layer;

depositing N + polycrystalline silicon on the single crystal Si thin layer to be used as an emitter;

PECVD deposition of high-stress capping layer Si using dual-frequency radio frequency power supply₃N₄Material is etched from the emitter and base windows.

4. The method for manufacturing a high-frequency silicon-germanium heterojunction bipolar transistor according to claim 3, wherein: the PECVD (plasma enhanced chemical vapor deposition) method using the dual-frequency radio frequency power supply is used for depositing the high-stress covering layer Si₃N₄After the material is prepared, the intrinsic stress of the material is transferred into a silicon channel, and the applied stress changes the energy band structure of the device and enhances the mobility of current carriers; meanwhile, the lattice constants of Si and Ge are different, so that the base region of the high-frequency silicon-germanium heterojunction bipolar transistor is affected by Si₃N₄Uniaxial stress caused by the material and biaxial stress caused by the substrate act to form a uniaxial strain emitter region and a composite strain base region.

Technical Field

The invention belongs to the technical field of electronics, and relates to a high-frequency silicon-germanium heterojunction bipolar transistor and a manufacturing method thereof.

Background

Cut-off frequency f of silicon-based active devices as integrated circuits continue to move toward smaller process nodes_TAnd a maximum oscillation frequency f_maxAnd gradually entering a terahertz frequency band. Compared with the traditional III-V semiconductor device, the silicon-based solid terahertz device has the technical advantages of low cost, easiness in mass production and compatibility with a super-large-scale integrated circuit process, and gradually draws attention of all countries in the world. In the frequency band of 0.1-1 THz, due to the fact that huge potential and technical advantages are displayed in the application of the SiGeBiCMOS reference circuit and the system, the SiGeHBT becomes a core device of the silicon-based high-frequency integrated circuit, research institutions and scholars at home and abroad strive to optimize the frequency performance of the silicon-based high-frequency integrated circuit by various technical means, and the potential of the silicon-based high-frequency integrated circuit in the high-frequency application field is fully exploited.

A SiGe Heterojunction Bipolar Transistor (HBT) is a silicon-based Bipolar Junction Transistor (BJT) with a base region to which a small amount of Ge component is added. The base region is made of SiGe material, so that the device performance is remarkably improved, and the SiGeHBT becomes a standard bipolar transistor in high-speed application. A Heterojunction Bipolar Transistor (HBT) developed on the basis of a mature silicon process and based on a germanium-silicon (SiGe) process utilizes the advantages of 'energy band engineering', solves the contradiction between the improvement of amplification factor and the improvement of frequency characteristic, and has a certain limit on improving the performance of a device only by means of the technology.

The research finds that: the strain Si technology can improve the mobility of carriers, shorten the transit time of the carriers and effectively improve the performance of the device. The SOI technology can not only reduce the parasitic capacitance effect generated by the PN junction and the power consumption of the device and reduce the production cost, but also can accelerate the working speed of the device and improve the radiation resistance of the device and the utilization rate of the wafer. Therefore, the advanced silicon-based SOI technology is used, the characteristic size of the device is continuously reduced, and key performance parameters such as the frequency, the early voltage, the breakdown voltage and the like of the device can be greatly improved by combining with the strain Si technology.

Disclosure of Invention

In view of the above, the present invention provides a high frequency silicon germanium heterojunction bipolar transistor and a method for fabricating the same.

In order to achieve the purpose, the invention provides the following technical scheme:

a preparation method of a high-frequency silicon-germanium heterojunction bipolar transistor comprises the following steps: depositing buried oxide layer on single crystal Si substrate to form SOI structure with the single crystal Si substrate and the Si material in the collector region, i.e. Si on the insulating substrate, wherein the structure has three layers, i.e. introducing an insulating layer (mostly SiO) between the top Si material and the substrate Si material₂Material); injecting boron ions at the position of the collector region corresponding to the base electrode window, and performing rapid annealing operation to eliminate lattice damage; etching a groove at one end of the collector region to form an STI isolation region, etching a groove again, and depositing and filling a heavily doped Si material; the Ge component in the base region is distributed in a step shape; depositing a single crystal Si thin layer above the base region to be used as a cap layer; depositing N + polycrystalline silicon on the single crystal Si thin layer to be used as an emitter; PECVD deposition of high-stress capping layer Si using dual-frequency radio frequency power supply₃N₄Etching the emitter window and the base window with a material; after stress introduction, a mirroring operation is performed.

PECVD deposition of high-stress capping layer Si using dual-frequency radio frequency power supply₃N₄The intrinsic stress of the material is easily transferred into the silicon channel by using the method, the applied stress changes the energy band structure of the device, the mobility of current carriers is enhanced, and the performance of the device is improved. Meanwhile, due to different lattice constants of Si and Ge, the high-frequency silicon-germanium heterojunction bipolar transistor designed by the method is enabled to be furtherIs under the action of biaxial stress.

The outer base region part outside the SiGe base region is positioned in the substrate instead of the region above the substrate as in the conventional SiGe HBT, so that the junction area of a collector junction is effectively increased while the lower base region series resistance is kept, the amplification factor and the frequency of the device are improved, and the process integration with a complementary metal oxide semiconductor CMOS is easier.

According to the physical theory of semiconductor device, the cut-off frequency f of SOI SiGe HBT_TCan be written as:

τ_ec，SOISiGeincluding base transit time, delay time due to emitter junction band discontinuity, emitter transit time, collector junction space charge region transit time, and collector junction capacitance charging time. Wherein τ of SOI SiGe HBT_ec，SOISiGeCan be written as:

the uniaxial compressive stress introduced by the base region splits the valence band energy band, the heavy hole band leaves the valence band top, and the light hole band is left at the valence band top, so that the conductivity effective mass of holes in the direction is reduced, the mobility of carriers is enhanced, the total transit time of the carriers is reduced, and the cut-off frequency of the device is improved.

f_TThe relationship to fmax is:

r_bis the base resistance. The introduction of stress has no effect on the concentration of the device, but enhances the mobility of carriers, so the base resistance decreases with the enhancement of the mobility of carriers. From the above expression, the maximum oscillation frequency is proportional to the cut-off frequency and inversely proportional to the base resistance. Due to cut-off frequencyf_TIncreased, reduced base resistance, so that the maximum oscillation frequency f_maxAnd (4) increasing.

The invention has the beneficial effects that: the method organically combines the mature silicon-based integrated circuit process with the rapidly developed SiGe technology, the SOI technology and the strain technology, and forms a new SOI SiGe HBT structure under a new terahertz frequency band by introducing uniaxial stress in a base region, wherein the uniaxial stress applied by the base region splits a valence band energy band, a heavy hole band leaves the valence band top, and a light hole band remains at the valence band top, so that the conductivity effective mass of holes in the direction is reduced, the mobility of carriers is enhanced, the total transit time of the carriers is reduced, and the cut-off frequency of a device is improved.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.

Drawings

For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:

fig. 1 is a schematic device structure diagram of a high-frequency silicon-germanium heterojunction bipolar transistor provided by the invention;

FIG. 2 is a schematic diagram of a high frequency silicon germanium heterojunction bipolar transistor fabrication process;

FIG. 3 is a schematic diagram of a second high frequency silicon germanium heterojunction bipolar transistor fabrication process;

FIG. 4 is a schematic diagram of a method for fabricating a triple high frequency silicon germanium heterojunction bipolar transistor;

FIG. 5 is a schematic diagram of a four-high frequency silicon germanium heterojunction bipolar transistor fabrication process;

FIG. 6 is a schematic diagram of a five-case high frequency silicon germanium heterojunction bipolar transistor fabrication process;

fig. 7 is a schematic diagram of a six-high frequency silicon germanium heterojunction bipolar transistor manufacturing method.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.

Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.

Fig. 1 is a schematic device structure diagram of a high-frequency silicon-germanium heterojunction bipolar transistor provided by the invention. Referring to fig. 2 to fig. 7, schematic diagrams of a method for manufacturing a high frequency silicon germanium heterojunction bipolar transistor provided by the present invention are shown, the method comprising:

100 preparing a Si substrate with a crystal orientation of (100) and a thickness of 100 nm;

growing SiO with the thickness of 190nm on a 101Si substrate material₂A buried oxide layer BOX of material composition;

growing a collector region of Si material on the buried oxide layer BOX, wherein the collector region is divided into two parts, the sub-collector region 102 is arranged close to the buried oxide layer BOX, the thickness of the sub-collector region is 120nm, the doping impurity is P, and the impurity concentration is 1.1 × 10¹⁹cm^-3The collector region 103 above the sub-collector region has a thickness of 190nm, a dopant impurity of P, and an impurity concentration of 1.5 × 10¹⁷cm^-3The SOI structure at this time is shown in FIG. 2;

growing Si over the collector region₃N₄Material, corresponding to the base window, to Si₃N₄Etching the material, implanting boron (B) ions into the etched region to form a P + intrinsic base region 104, wherein the dose of the implanted boron ions is 4 × 10¹³cm^-3After ion implantation, rapid thermal annealing operation is required to recover the structure and eliminate lattice damage;

deposition of SiO₂Material forming shallow trench isolation 105, etching the corresponding position of the collector window, depositing heavily doped Si material 106 with P as impurity and 1.1 × 10 as impurity concentration¹⁹cm^-3The device structure at this time is as shown in fig. 3;

a base region 107 with the thickness of 38nm is formed above the collector region 103 and a part of the P + inner base region 104, the Ge component of the base region adopts a step-shaped distribution, wherein the part close to the collector region 103 is a SiGe material with the thickness of 16nm and the Ge component of 30%, the part close to the emitter region 108 is a SiGe material with the thickness of 16nm and the Ge component of 17%, the part between the two parts is a SiGe material with the thickness of 6nm and the Ge component of 30-17%, the whole base region of the SiGe material is doped with impurities of B, and the concentration is 4 × 10¹⁸cm^-3；

Depositing a strained Si material to form a thin layer of single crystal Si 108, depositing N + polysilicon 109, etching away the polysilicon outside the emitter region, depositing SiO with a thickness of 20nm₂Forming a side wall 110 outside the N + polysilicon, depositing the N + polysilicon, and finally reserving an emitter windowThe structure of the device is shown in fig. 4 at this time;

deposition of high-stress capping layer Si by dual-frequency radio frequency power source PECVD₃N₄Material 111, capping layer Si₃N₄The material provides uniaxial compressive stress, and the device structure is shown in fig. 5;

deposition of isolated SiO₂Material deposited in the base region P + polysilicon 112 with an impurity concentration of 4 × 10¹⁸cm^-3Etching it, depositing isolating SiO₂The material, the device structure at this point is shown in fig. 6;

depositing collector region N + polysilicon 113 with impurity concentration of 1 × 10¹⁸cm^-3The whole device structure is sputtered with aluminum 114 to form a metal electrode material, and the area except the electrode is photoetched, and the device structure is as shown in fig. 7.

Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.