阅读说明：本技术 半导体芯片 (Semiconductor chip ) 是由 洪守玉 吴世利 周甘宇 高远 施金汕 曾剑鸿 于 2019-03-25 设计创作，主要内容包括：本公开提供一种半导体芯片,包含功能区、第一端、第二端、第三端及连接部,功能区具有相对的第一面及第二面,第一端设置于第一面上,第三端设置于第一面上,其中半导体芯片依据第三端及第一端之间所接收的驱动信号而进行导通或关断的切换,连接部设置于功能区第一面且连接第一端及第三端,其中当温度上升至高于第一温度时连接部为导电态,使半导体芯片因第一端及第三端之间短路而关断,当温度下降至不高于第三温度时,连接部为绝缘态,其中第一温度大于或等于第三温度。(The present disclosure provides a semiconductor chip, including a functional region, a first end, a second end, a third end and a connecting portion, wherein the functional region has a first surface and a second surface opposite to each other, the first end is disposed on the first surface, the third end is disposed on the first surface, wherein the semiconductor chip switches on or off according to a driving signal received between the third end and the first end, the connecting portion is disposed on the first surface of the functional region and connects the first end and the third end, wherein the connecting portion is in a conductive state when a temperature rises above a first temperature, so that the semiconductor chip is turned off due to a short circuit between the first end and the third end, and the connecting portion is in an insulating state when the temperature drops to a temperature not higher than the third temperature, wherein the first temperature is greater than or equal to the third temperature.)

1. A semiconductor chip, comprising:

the functional area is provided with a first surface and a second surface which are opposite;

a first end disposed on the first face;

a second end;

a third terminal disposed on the first surface, wherein the semiconductor chip is switched on or off according to a driving signal received between the third terminal and the first terminal; and

and the connecting part is arranged on the first surface of the functional area and is connected with the first end and the third end, wherein when the temperature rises to be higher than a first temperature, the connecting part is in a conductive state, so that the semiconductor chip is turned off due to short circuit between the first end and the third end, and when the temperature drops to be not higher than a third temperature, the connecting part is in an insulating state, wherein the first temperature is higher than or equal to the third temperature.

2. The semiconductor chip of claim 1, wherein said driving signal is a voltage.

3. The semiconductor chip of claim 1, wherein said first terminal and said second terminal are output terminals.

4. The semiconductor chip as claimed in claim 1, wherein the semiconductor chip further comprises a metal wiring layer, and the first temperature is lower than a melting temperature of the metal wiring layer and lower than a minimum temperature at which the semiconductor chip loses semiconductor characteristics.

5. The semiconductor chip of claim 1, wherein the semiconductor chip operates normally when the temperature of the semiconductor chip is reduced to not higher than a second temperature, which is lower than the first temperature.

6. The semiconductor chip of claim 1, wherein the semiconductor chip is a metal oxide semiconductor field effect transistor, an insulated gate bipolar transistor, a high electron mobility transistor, or a bipolar junction transistor.

7. The semiconductor chip of claim 1, wherein the connection portion is a temperature-induced phase change material or a low melting temperature glass.

8. The semiconductor chip of claim 1, wherein the semiconductor chip comprises a first passivation layer disposed on the first surface of the functional region, and the connecting portion covers the first passivation layer.

9. The semiconductor chip of claim 1 or 8, wherein said semiconductor chip comprises a second passivation layer overlying said connection portion.

10. The semiconductor chip as claimed in claim 9, wherein the semiconductor chip comprises a metal layer disposed between the connection portion and the second passivation layer and contacting the connection portion, the metal layer being connected to the first end and the third end through the connection portion, or one end of the metal layer contacting the first end and being connected to the third end through the connection portion, or one end of the metal layer contacting the third end and being connected to the first end through the connection portion.

11. The semiconductor chip of claim 1, wherein the material of the semiconductor chip is silicon carbide or gallium nitride.

12. The semiconductor chip of claim 1, wherein the semiconductor chip comprises a metal layer in contact with the connection portion, the metal layer being connected to the first terminal and the third terminal via the connection portion, or one end of the metal layer being in contact with the first terminal and being connected to the third terminal via the connection portion, or one end of the metal layer being in contact with the third terminal and being connected to the first terminal via the connection portion.

13. A process method applied to a semiconductor chip comprises the following steps:

step (a): the chip comprises a chip body, a first terminal, a second terminal and a third terminal, wherein the chip body comprises a functional area, the functional area is provided with a first surface and a second surface which are opposite, the first terminal and the third terminal are arranged on the first surface, and a driving signal is received between the first terminal and the third terminal to control the semiconductor chip to be switched on or switched off; and

step (b): and forming a connecting part on the first surface of the functional region and connecting the first end and the third end, wherein when the temperature of the connecting part rises to be higher than a first temperature, the connecting part is in a conductive state, so that the semiconductor chip is turned off due to short circuit between the first end and the third end, and when the temperature of the connecting part drops to be not higher than a third temperature, the connecting part is in an insulating state, wherein the first temperature is higher than or equal to the third temperature.

14. The process of claim 13, wherein the semiconductor chip is normally operated when the temperature is lowered to not higher than a second temperature, which is lower than the first temperature.

15. The process of claim 13, wherein in step (b) of the process, the connecting portion is formed on the first surface of the functional region by physical vapor deposition, chemical vapor deposition, spin-on-glass, or spot coating.

16. The process of claim 13, wherein the process further comprises:

step (c): and forming a metal layer to contact with the connecting part, so that the metal layer is connected with the first end and the third end through the connecting part, or one end of the metal layer is contacted with the first end and is connected with the third end through the connecting part, or one end of the metal layer is contacted with the third end and is connected with the first end through the connecting part.

Technical Field

The present disclosure relates to the field of integrated circuit technology, and more particularly, to a semiconductor chip with a temperature control connection portion.

Background

With the rapid development of new energy vehicles, calculator equipment, autopilot, smart phones and other communication equipment terminal equipment and other fields, the requirements for power supply products applied to the fields are higher and higher, wherein a semiconductor chip is a key component in the power supply product and is widely applied to a switching conversion circuit, a power amplification circuit, a rectification circuit, a driving circuit and the like, and therefore, the reliability requirements of the semiconductor chip are gradually increased.

A conventional semiconductor chip often experiences a temperature increase due to various reasons, such as short circuit, overcurrent, abnormal heat dissipation or abnormal driving. Referring to fig. 1, which is a schematic cross-sectional view of a conventional semiconductor chip, as shown in fig. 1, a semiconductor chip 1 ', such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a Gate (Gate G) and a Source (Source S) cell of the semiconductor chip 1' are periodically arranged, and are respectively connected to a respective pad (not shown) through a metal, a metal wiring connecting the plurality of Gate G and Source S cells to the pad, and a metal wiring layer of a pad body are collectively referred to as a metal wiring layer. It should be noted that the wiring connecting the cell of the gate G to the bonding pad usually includes two forms of heavily doped polysilicon and a poly-metal layer on the polysilicon, which will not be described in detail later. And the gate G and the source S are spaced apart from each other to provide independent electrodes. When some faults occur, if the temperature of the chip rises to a high temperature, so that the metal wiring layer is affected by the high temperature and is melted, the metal wiring layer may melt and flow to form the metal connection portion M, so that the melted metal crosses the gap and connects the gate G and the source S, thereby causing a short circuit between the gate G and the source S, and further causing the semiconductor chip 1' to be turned off passively. However, although the semiconductor chip 1 'is turned off due to the melting of the metal wiring layer at a high temperature, on one hand, after the normal temperature is recovered, the melted and condensed metal wiring layer still short-circuits the gate G and the source S, so that the semiconductor chip 1' cannot normally operate, and on the other hand, before the high-temperature fault occurs, the metal wiring layer itself is not directly connected to the gate G and the source S, but is connected to the gate G and the source S due to accidental spreading after melting, and is uncontrollable.

Therefore, how to develop a semiconductor chip that overcomes the above-mentioned disadvantages is a urgent need.

Disclosure of Invention

The present disclosure is directed to a semiconductor chip to improve the practicability of the semiconductor chip.

To achieve the above objective, a broad embodiment of the present disclosure provides a semiconductor chip including a functional region, a first terminal, a second terminal, a third terminal and a connecting portion. The functional area is provided with a first surface and a second surface which are opposite. The first end is arranged on the first surface. The third terminal is disposed on the first surface, wherein the semiconductor chip is switched on or off according to a driving signal received between the third terminal and the first terminal. The connecting part is arranged on the first surface of the functional area and is connected with the first end and the third end, wherein when the temperature rises to be higher than the first temperature, the connecting part is in a conductive state, so that the semiconductor chip is turned off due to short circuit between the first end and the third end, and when the temperature drops to be not higher than the third temperature, the connecting part is in an insulating state, wherein the first temperature is higher than or equal to the third temperature.

To achieve the above objects, another broad embodiment of the present disclosure provides a process applied to a semiconductor chip. First, step S1 is executed to set a chip body including a functional region, a first end, a second end and a third end, the functional region has a first surface and a second surface opposite to each other, the first end and the third end are disposed on the first surface, and a driving signal is received between the first end and the third end to control the semiconductor chip to be turned on or off. Then, step S2 is executed to form a connection portion on the first surface of the functional region and connecting the first end and the third end, wherein the connection portion is in a conductive state when the temperature of the connection portion is increased to be higher than the first temperature, so that the semiconductor chip is turned off due to the short circuit between the first end and the third end, and the connection portion is in an insulating state when the temperature of the connection portion is decreased to be not higher than the third temperature, wherein the first temperature is higher than or equal to the third temperature.

Drawings

Fig. 1 is a schematic cross-sectional view of a conventional semiconductor chip.

Fig. 2 is a schematic cross-sectional structure diagram of a semiconductor chip according to a first embodiment of the disclosure.

Fig. 3 is a schematic diagram illustrating the change of resistivity of the connection portion of the semiconductor chip shown in fig. 2 at different temperatures.

Fig. 4 is a schematic top view of the semiconductor chip shown in fig. 2 according to an embodiment.

Fig. 5 is a schematic top view of the semiconductor chip shown in fig. 2 according to another embodiment.

Fig. 6 is a schematic top view of the semiconductor chip shown in fig. 2 according to still another embodiment.

Fig. 7 is a schematic cross-sectional view of a semiconductor chip according to a second embodiment of the disclosure.

Fig. 8 is a schematic cross-sectional view of a semiconductor chip according to a third embodiment of the disclosure.

Fig. 9 is a schematic cross-sectional view of a semiconductor chip according to a fourth embodiment of the disclosure.

Fig. 10 is a schematic cross-sectional view of a semiconductor chip according to a fifth embodiment of the disclosure.

Fig. 11 is a schematic cross-sectional view of a semiconductor chip according to a sixth embodiment of the disclosure.

Fig. 12 is a schematic cross-sectional view of a semiconductor chip according to a seventh embodiment of the disclosure.

Fig. 13 is a schematic cross-sectional view of a semiconductor chip according to an eighth embodiment of the disclosure.

Fig. 14 is a flow chart illustrating a method of processing the semiconductor chip shown in fig. 2.

Fig. 15 is a flowchart illustrating a method of processing the semiconductor chip shown in fig. 11.

Description of the symbols:

1': semiconductor chip

G: gate pole

S: source electrode

M: metal connection part

1. 2, 3, 4, 5, 6: semiconductor chip

10. 20, 30, 40, 50, 60: chip body

11. 21, 31, 41, 51, 61: functional area

111. 211, 311, 411, 511, 611: first side

112. 212, 312, 412, 512, 612: second surface

12. 22, 32, 42, 52, 62: first end

13. 23, 33, 43, 53, 63: third terminal

14. 24, 34, 44, 54: connecting part

64: polycrystalline silicon

70: insulating medium

15. 35, 45, 55: first passivation layer

25. 36, 46, 56: second passivation layer

47. 57: metal layer

D: packaging structure

19: second end

S1-S3: step (ii) of

Detailed Description

Some exemplary embodiments that incorporate the features and advantages of the present disclosure will be described in detail in the specification which follows. As will be realized, the disclosure is capable of other and different forms without departing from the scope thereof, and the description and drawings are to be regarded as illustrative in nature, and not as restrictive.

Referring to fig. 2 and 3, fig. 2 is a schematic cross-sectional view of a semiconductor chip according to a first embodiment of the disclosure, and fig. 3 is a schematic diagram illustrating a resistivity change of a connection portion of the semiconductor chip shown in fig. 2 at different temperatures. As shown, the semiconductor chip 1 of the present disclosure is, for example but not limited to, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), an Insulated Gate Bipolar Transistor (IGBT), a High Electron Mobility Transistor (HEMT), or a Bipolar Junction Transistor (BJT), and includes a functional region 11, a first end 12, a second end (not shown), a third end 13, and a connection portion 14. In some embodiments, the material of the semiconductor chip 1 may be, but is not limited to, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN).

The functional region 11 includes a first surface 111 and a second surface 112 opposite to each other. The first end 12 is disposed on the first face 111. The first terminal 12 may be an output terminal, such as a source of a MOSFET. The functional region 11 is a semiconductor material region of the semiconductor chip 1, for example a Si material region of a Si-based device. The second terminal is an output terminal, such as a drain of a MOSFET. The third end 13 is disposed on the first face. The third terminal 13 is, for example, an input terminal, such as a gate of a MOSFET. The semiconductor chip 1 is switched on or off according to the driving signals received by the third terminal 13 and the first terminal 12, wherein the driving signals can be voltages or currents. In some embodiments, the functional region 11, the first end 12, the second end and the third end 13 may constitute the chip body 10. Referring to fig. 3, when the connection portion 14 is shifted from one environmental temperature to another environmental temperature due to, for example, system failure, chip failure, environmental change, etc., the temperature of the connection portion 14 gradually approaches to a new environmental temperature due to thermal hysteresis, for example, the connection portion 14 is vanadium dioxide (VO2), when the temperature of the connection portion 14 rises to the first temperature, the resistivity of the connection portion 14 decreases to be in a conductive state, so that the semiconductor chip 1 is turned off due to a short circuit between the first end 12 and the third end 13, which helps to prevent the semiconductor chip from being damaged due to further temperature rise; in addition, when the temperature of the connection portion 14 is lowered to a third temperature, the resistivity of the connection portion 14 is raised to be in an insulating state, and at this time, the semiconductor chip 1 can be restored to a normal operation, in which the first temperature is greater than or equal to the third temperature. In some embodiments, the first temperature is equal to the third temperature, so that the semiconductor chip 1 is normally operated in an insulating state when the temperature of the connection portion 14 is decreased to be not higher than the first temperature, the semiconductor chip 1 is turned off due to a short circuit between the first terminal 12 and the third terminal 13 in a conductive state when the temperature of the connection portion 14 is increased to be higher than the first temperature, and the conductive state is changed to the insulating state when the temperature of the connection portion 14 is decreased to be not higher than the first temperature from being higher than the first temperature. In some embodiments, the values of the first temperature and the third temperature may be related to the material preparation of the connection portion 14, the material thickness of the connection portion 14, the speed of temperature change of the connection portion 14, and other factors.

In some embodiments, the connection portion 14 can be but is not limited to a temperature-induced phase change material, such as vanadium dioxide (VO2), germanium-or other element-doped vanadium dioxide, and other temperature-induced phase change materials, or the connection portion 14 can be a low-melting-temperature glass, such as a vanadate material, a phosphate material, a borate material, or a silicate material, and the connection portion 14 can be but is not limited to a lead oxide-zinc oxide-boron trioxide material system (PbO-ZnO-B2O3), a lead oxide-aluminum oxide-boron trioxide material system (PbO-Al2O3-B2O3), a lead oxide-bismuth trioxide-boron trioxide material system (PbO-Bi2O3-B2O3), a lead oxide-boron trioxide-silica material system (PbO-B2O3-SiO2), a potassium oxide-lead-silica material system (K2O-Pb-SiO2), Zinc oxide-diboron trioxide-silica material systems (ZnO-B2O3-SiO2), lead oxide-silica-zinc oxide-barium oxide material systems (PbO-SiO2-ZnO-BaO), sodium oxide-barium oxide-silica material systems (Na2O-BaO-SiO2), zinc oxide-diboron trioxide-phosphorus pentoxide material systems (ZnO-B2O3-P2O5), lithium oxide-alumina-silica material systems (Li2O-Al2O3-SiO2), thallium oxide-vanadium pentoxide-tellurium oxide-arsenic oxide material systems (Tl2O-V2O5-TeO2-AsO3), bismuth trioxide-diboron trioxide material systems (Bi2O3-B2O3), lead oxide-bismuth pentoxide-zinc oxide material systems (PbO-V2O5-Bi2O3-ZnO 3) A lithium oxide-zinc oxide-silicon dioxide material system (Li2O-ZnO-SiO2), a tin oxide-zinc oxide-phosphorus pentoxide material system (SnO-ZnO-P2O5), a vanadium pentoxide-phosphorus pentoxide-antimony oxide material system (V2O5-P2O5-SbO), and the like, and the connection portion 14 may further include other materials added to the above materials to adjust the melting point, strength, thermal expansion coefficient, wettability, electrical properties, and manufacturability.

As can be seen from the above, when the connecting portion material of the above portion is adopted, the temperature of the connecting portion 14 of the semiconductor chip 1 of the present disclosure is in the conductive state when the first temperature is equal to the third temperature, and is in the insulating state when the temperature of the connecting portion 14 is reduced to be not higher than the first temperature, so that compared with the conventional semiconductor chip 1' which cannot normally work after the normal temperature is recovered, the semiconductor chip 1 of the present disclosure utilizes the state transition of the connecting portion 14 at different temperatures, so that the semiconductor chip 1 is automatically turned off at a high temperature to avoid further damage, and the semiconductor chip 1 normally works when the normal temperature is recovered, so that the practicality of the semiconductor chip 1 of the present disclosure is high.

In the present embodiment, the semiconductor chip 1 includes a pad and a metal wiring layer (not shown), the first temperature is lower than the melting temperature of the metal wiring layer (for example, the melting point of aluminum is 660 ℃), and the first temperature is lower than the lowest temperature at which the semiconductor chip loses the semiconductor characteristics, so that the arrangement of the metal wiring layer and the characteristics of the semiconductor chip are not affected when the semiconductor chip 1 switches the state of the connection portion 14 according to the boundary of the first temperature. In addition, the semiconductor chip 1 further has a second temperature, which is the highest allowable junction temperature of the semiconductor chip 1 (it should be specifically noted that the highest allowable junction temperature is a temperature given by considering the performance, the service life, and the like comprehensively, and the temperature is usually far less than the limit temperature which the semiconductor can bear and loses the switching characteristics of the semiconductor), so that the semiconductor chip 1 normally operates when the temperature is reduced to be not greater than the second temperature. The second temperature is lower than the first temperature, so that when the semiconductor chip 1 is in a normal operation state, i.e. the temperature of the semiconductor chip 1 is reduced to be not higher than the second temperature, the connection portion 14 is in an insulation state, so that a short circuit between the two control electrodes (the first end 12 and the third end 13) can be avoided when the semiconductor chip 1 is in a normal operation state, as shown in table 1 below, which exemplarily shows the corresponding highest junction temperature, the lowest temperature at which the semiconductor characteristics are lost, the material type of the connection portion 14, and the first temperature range among the material types of the different semiconductor chips 1, but not limited thereto.

TABLE 1

With reference to fig. 2, the semiconductor chip 1 may further include a first passivation layer 15, but the invention is not limited thereto. The first passivation layer 15 is disposed on the first surface 111 of the functional region 11 for protecting the functional region 11, and the connecting portion 14 covers the first passivation layer 15, wherein the material of the first passivation layer 15 can be, but not limited to, silicon dioxide (SiO2), silicon nitride (SiN), or Polyimide (PI), and further the first passivation layer 15 can be a composite layer, such as a polyimide layer disposed on silicon nitride, a silicon nitride layer composited on silicon dioxide, and the like. In this embodiment, the first passivation layer 15 is used to block moisture and contamination on the first surface 111 of the functional region 11 located between the first end 12 and the third end 13, so that the material forming the connecting portion 14 has a lower requirement for blocking moisture and contamination, and the structure of the semiconductor chip 1 is easier to implement and the manufacturing method is simpler.

In some embodiments, the first end 12 includes a plurality of first pads 121, the third end 13 includes a second pad 131 and a second bus bar 132, and the connection portion 14 completely fills the space between the first end 12 and the third end 13 on the first surface 111 of the functional region 11, as shown in fig. 4, the connection portion 14 completely fills the space between the first pad 121 and the second pad 131 and the space between the first pad 121 and the second bus bar 132, so that the connection portion 14 can be switched to a conductive state when the temperature of the semiconductor chip 1 at any position rises above the first temperature, and the state switching sensitivity of the semiconductor chip 1 is high.

In other embodiments, the first end 12 includes a plurality of first pads 121, the third end 13 includes a second pad 131 and a second bus bar 132, and the connection portion 14 is only filled on a portion of the first surface 111 of the functional region 11 and is located in a space between the first end 12 and the third end 13, for example, the connection portion 14 is filled in a position where the semiconductor chip 1 is more prone to heat generation, as shown in fig. 5, the connection portion 14 is filled in a space between a portion of the first pads 121 and the second pad 131 and a space between a portion of the first pads 121 and the second bus bar 132, so that one or more connection portions 14 can be flexibly disposed, thereby reducing the cost of the semiconductor chip 1. In some embodiments, such as the semiconductor chip shown in fig. 4 and 5, the second end is disposed on the second surface 112 of the functional region 11.

In some embodiments, the first end 12 includes a first pad 121 and a first bus bar 122, the third end 13 includes a second pad 131 and a second bus bar 132, and the connection portion 14 is only filled on a portion of the first surface 111 of the functional region 11 and in a space between the first end 12 and the third end 13, as shown in fig. 6, the connection portion 14 is filled in a space between a portion of the first pad 121 and the second bus bar 132 and a space between a portion of the first bus bar 122 and the second bus bar 132. In some embodiments, such as the semiconductor chip shown in fig. 6, the second terminal 19 is disposed on the first surface 111 of the functional region 11.

Referring to fig. 7, which is a schematic cross-sectional structure view of a semiconductor chip according to a second embodiment of the disclosure, in this embodiment, a first passivation layer 15 is disposed on a first surface 111 of a functional region 11 and at least partially covers a first end 12 and a third end 13, a connection portion 14 is formed on the first surface 111 of the functional region 11 by using pvd, cvd, spin-on-glass, or a dot coating process, so as to form a semiconductor chip 1, and the connection portion 14 covers the first passivation layer 15. Please refer to fig. 8, which is a schematic cross-sectional view of a semiconductor chip according to a third embodiment of the present disclosure, in which the semiconductor chip is first disposed on a package structure D, and then disposed with a connecting portion 14. The connection portion 14 is formed on the first surface 111 of the functional region 11 by dot coating, printing, and the like, and the connection portion 14 covers the first passivation layer 15. As can be seen from the above, the semiconductor chip 1 of the present disclosure may be provided with the connection portion 14 in a chip process or a packaging process, and the connection portion 14 may be provided after the first passivation layer 15 is provided, so that the semiconductor chip 1 of the present disclosure has a flexible process and may reduce the difficulty of the process.

Please refer to fig. 9, which is a schematic cross-sectional view illustrating a semiconductor chip according to a fourth embodiment of the disclosure. As shown in the figure, the semiconductor chip 2 of the present embodiment includes a functional region 21, a first end 22, a third end 23, a connecting portion 24 and a second passivation layer 25, wherein the functional region 21, the first end 22, the third end 23 and the connecting portion 24 of the semiconductor chip 2 are respectively similar to the functional region 11, the first end 12, the third end 13 and the connecting portion 14 of the semiconductor chip 1 shown in fig. 2, and the similar component structures, operations and functions are not repeated herein. In contrast to the embodiment shown in fig. 2, in the embodiment shown in fig. 9, the connection portion 24 of the semiconductor chip 2 is disposed on the first surface 211 of the functional region 21, and the second passivation layer 25 covers the connection portion 24 to protect the connection portion 24. The material and the like of the second passivation layer 25 may be the same as the first passivation layer 15.

Please refer to fig. 10, which is a schematic cross-sectional view illustrating a semiconductor chip according to a fifth embodiment of the disclosure. As shown in the figure, the semiconductor chip 3 of the present embodiment includes a functional region 31, a first end 32, a third end 33, a connecting portion 34 and a first passivation layer 35, wherein the functional region 31, the first end 32, the third end 33, the connecting portion 34 and the first passivation layer 35 of the semiconductor chip 3 are similar to the functional region 11, the first end 12, the third end 13, the connecting portion 14 and the first passivation layer 15 of the semiconductor chip 1 shown in fig. 2, respectively, and the similar component structures, operations and functions are not described herein again. In contrast to the embodiment shown in fig. 2, in the embodiment shown in fig. 10, the semiconductor chip 3 further includes a second passivation layer 36, and the second passivation layer 36 covers the connection portion 34 to protect the functional region 31 and the connection portion 34, so that the semiconductor chip 3 obtains better protection capability. In some embodiments, the first passivation layer 35 may be, but is not limited to, silicon dioxide (SiO2), and the second passivation layer 36 may be, but is not limited to, Polyimide (PI). In other embodiments, the second passivation layer 36 is made of a composite material, such as a composite layer of ethyl silicate (TEOS) and silicon nitride (SiN) with good conformality and stress release.

Please refer to fig. 11, which is a schematic cross-sectional view illustrating a semiconductor chip according to a sixth embodiment of the disclosure. As shown in the figure, the semiconductor chip 4 of the present embodiment includes a functional region 41, a first end 42, a third end 43, a connecting portion 44 and a first passivation layer 45, wherein the functional region 41, the first end 42, the third end 43, the connecting portion 44 and the first passivation layer 45 of the semiconductor chip 4 are similar to the functional region 11, the first end 12, the third end 13, the connecting portion 14 and the first passivation layer 15 of the semiconductor chip 1 shown in fig. 2, respectively, and the similar component structures, operations and functions are not described herein again. In contrast to the embodiment shown in fig. 2, in the embodiment shown in fig. 11, the semiconductor chip 4 further includes a second passivation layer 46 and a metal layer 47. The second passivation layer 46 covers the connection portion 44 to protect the functional region 41 and the connection portion 44, so that the semiconductor chip 4 can obtain better protection capability. The metal layer 47 is disposed between the connection portion 44 and the second passivation layer 46, and is in contact with the connection portion 44, and the metal layer 47 is not directly connected to the first end 42 and the third end 43, but is connected to the first end 42 and the third end 43 through the connection portion 44, so that the impedance between the first end 42 and the third end 43 is reduced. Therefore, when the temperature of the connection portion 44 rises above the first temperature and becomes conductive, the short circuit between the first terminal 42 and the third terminal 43 can be achieved more quickly by the metal layer 47, so that the semiconductor chip 4 can be turned off more quickly. In some embodiments, the first passivation layer 45 may be, but is not limited to, silicon dioxide (SiO2), and the second passivation layer 46 may be, but is not limited to, Polyimide (PI). In other embodiments, the second passivation layer 46 is made of a composite material, such as a composite layer of ethyl silicate (TEOS) and silicon nitride (SiN) with good conformality and stress relief. In some embodiments, metal layer 47 may be formed by Physical Vapor Deposition (PVD). The first passivation layer 45 and the second passivation layer 46 in this embodiment may be omitted individually or entirely, and the invention is not limited thereto.

Please refer to fig. 12, which is a schematic cross-sectional view illustrating a semiconductor chip according to a seventh embodiment of the disclosure. As shown in the figure, the semiconductor chip 5 of the present embodiment includes a functional region 51, a first end 52, a third end 53, a connecting portion 54 and a first passivation layer 55, wherein the functional region 51, the first end 52, the third end 53, the connecting portion 54 and the first passivation layer 55 of the semiconductor chip 5 are similar to the functional region 11, the first end 12, the third end 13, the connecting portion 14 and the first passivation layer 15 of the semiconductor chip 1 shown in fig. 2, respectively, and the similar component structures, operations and functions are not described herein again. In contrast to the embodiment shown in fig. 2, in the embodiment of fig. 12, the semiconductor chip 5 further includes a second passivation layer 56 and a metal layer 57. The second passivation layer 56 covers the connection portion 54 to protect the functional region 51 and the connection portion 54, so that the semiconductor chip 5 can obtain better protection capability. The metal layer 57 is disposed between the connection portion 54 and the second passivation layer 56, and contacts the connection portion 54. In the present embodiment, one end of the metal layer 57 is connected to the third terminal 53, and the metal layer 57 is connected to the first terminal 52 through the connection portion, so that the impedance between the first terminal 52 and the third terminal 53 is reduced. Therefore, when the temperature of the connection portion 54 is increased to be higher than the first temperature and is in a conductive state, the short circuit between the first terminal 52 and the third terminal 53 can be achieved more quickly by the metal layer 57, so that the semiconductor chip 5 can be turned off more quickly. In other embodiments, one end of the metal layer 57 is connected to the first end 52, and the metal layer 57 is connected to the third end 53 through the connection portion 54, so that the impedance between the first end 52 and the third end 53 is reduced, and the semiconductor chip 5 is turned off more rapidly. One end of the metal layer may be located anywhere on the metal layer. In some embodiments, the first passivation layer 55 may be, but is not limited to, silicon dioxide (SiO2), and the second passivation layer 56 may be, but is not limited to, Polyimide (PI). In other embodiments, the second passivation layer 56 is made of a composite material, such as a composite layer of ethyl silicate (TEOS) and silicon nitride (SiN) with good conformality and stress release. In some embodiments, metal layer 57 may be formed by Physical Vapor Deposition (PVD). The first passivation layer 55 and the second passivation layer 56 in this embodiment may be omitted individually or entirely, and the present invention is not limited thereto. The metal layer in each embodiment of the present disclosure is arranged to be in contact with the connection portion, and includes both direct contact and indirect contact through other conductive materials, and at least partial contact is sufficient; the metal layer may be disposed between the connection portion and the second passivation layer, between the connection portion and the first passivation layer, or both. If the first passivation layer and/or the second passivation layer are omitted, the metal layer may be disposed so as to be at least partially in contact with the connection portion. The metal layer may be divided into multiple sections and multiple layers, and the invention is not limited thereto.

Please refer to fig. 13, which is a schematic cross-sectional view illustrating a semiconductor chip according to an eighth embodiment of the disclosure. As shown in the figure, the semiconductor chip 6 of the present embodiment includes a functional region 61, a first terminal 62, a third terminal 63 and a polysilicon 64, wherein the second terminal is omitted. The functional region 61, the first end 62, and the third end 63 of the semiconductor chip 6 are similar to the functional region 11, the first end 12, and the third end 13 of the semiconductor chip 1 shown in fig. 2, respectively, and the structure, operation, and function of the similar components are not described herein again. In contrast to the embodiment shown in fig. 2, in the embodiment of fig. 13, the semiconductor chip 6, such as a MOSFET, has an insulating medium 70 between the metal wires connecting the cells at the third end (e.g., the gate of the MOSFET) and the first end (e.g., the source of the MOSFET) to the bonding pad. A connecting portion may be disposed within the insulating medium 70 connecting the first end 62 to a third end (e.g., a gate of a MOSFET).

In other embodiments, such as the semiconductor chip shown in fig. 13, the connection portion may not be disposed in the insulating layer 70, but disposed on the insulating layer 70 and between the first end 62 and the third end 63. Since the insulating layer 70 is disposed on the first surface 611 of the functional region 61, the connection portion disposed on the insulating layer 70 is also considered to be disposed on the first surface 611 of the functional region 61, and is not limited to direct contact or indirect contact.

Please refer to fig. 14, which is a flowchart illustrating a method for fabricating the semiconductor chip shown in fig. 2. First, step S1 is executed to configure a chip body 10 including a functional region 11, a first end 12, a second end and a third end 13, where the functional region 11 has a first surface 111 and a second surface 112 opposite to each other, the first end 12 and the third end 13 are disposed on the first surface 111, and a driving signal is received between the first end 12 and the third end 13 to control the semiconductor chip 1 to be turned on or off. Next, step S2 is executed to form a connection portion 14 on the first surface 111 of the functional region 11 and connect the first terminal 12 and the third terminal 13, wherein the connection portion 14 is in a conductive state when the temperature of the connection portion 14 is increased to be higher than a first temperature, so that the semiconductor chip 1 is turned off due to a short circuit between the first terminal 12 and the third terminal 13, and the connection portion 14 is in an insulating state when the temperature of the connection portion 14 is decreased to be not higher than a third temperature, wherein the first temperature is higher than or equal to the third temperature. However, the above-mentioned process methods can also be applied to other embodiments of the present disclosure, and therefore, are not described herein again.

Please refer to fig. 15, which is a flowchart illustrating a method of manufacturing the semiconductor chip shown in fig. 11. First, step S1 is executed to configure a chip body 40 including a functional region 41, a first end 42, a second end and a third end 43, wherein the functional region 41 has a first surface 411 and a second surface 412 opposite to each other, the first end 42 and the third end 43 are disposed on the first surface 411, and a driving signal is received between the first end 42 and the third end 43 to control the semiconductor chip 4 to be turned on or off. Next, step S2 is executed to form a connection portion 44 on the first surface 411 of the functional region 41 and connect the first end 42 and the third end 43, wherein the connection portion 44 is in a conductive state when the temperature of the connection portion 44 is increased to be higher than a first temperature, so that the semiconductor chip 4 is turned off due to a short circuit between the first end 42 and the third end 43, and the connection portion 44 is in an insulating state when the temperature of the connection portion 44 is decreased to be not higher than a third temperature, wherein the first temperature is higher than or equal to the third temperature. Next, step S3 is executed to form the metal layer 47 in contact with the connection portion 44, such that the metal layer 47 is connected to the first end 42 and the third end 43 via the connection portion 44, or one end of the metal layer 47 is connected to the third end 43 and the first end 42 via the connection portion 44. One end of the metal layer may be located anywhere on the metal layer. However, the above-mentioned process methods can also be applied to other embodiments of the present disclosure, and therefore, are not described herein again. In some embodiments, the sequence of step S2 and step S3 may be changed or completed simultaneously, and the invention is not limited thereto.

As can be seen from the above, the temperature of the connecting portion of the semiconductor chip of the present disclosure is conductive when it rises above the first temperature, and is insulating when the temperature of the connecting portion drops to not higher than the first temperature, so that compared to the conventional semiconductor chip which cannot normally operate after the normal temperature is recovered, the semiconductor chip of the present disclosure utilizes the state transition of the connecting portion at different temperatures, so that the semiconductor chip is automatically turned off at high temperature to avoid further damage, and the semiconductor chip can resume normal operation when the normal temperature is recovered, so that the semiconductor chip of the present disclosure has high practicability. In some embodiments, the insulating state and the conducting state of the connecting part are changed due to the material characteristics of the connecting part, so that the semiconductor chip is shut down at high temperature and is protected from normal operation at low temperature, and the semiconductor chip is safe and reliable.