阅读说明：本技术 场效应功率晶体管及其制作方法 (Field effect power transistor and manufacturing method thereof ) 是由 宋滨 陈越 于 2020-07-09 设计创作，主要内容包括：本申请实施例提供场效应功率晶体管及其制作方法,涉及半导体器件制作技术领域。通过控制栅氧层与多晶层的厚度,有效阻止P型体区制作过程中,注入的正价离子(比如硼正离子)进入到JFET区,将JFET区中的负价离子(比如磷负离子)中和,使得JFET区中导电离子的浓度减少,确保JFET区中导电离子的浓度稳定,引线孔刻蚀使用双功率刻蚀控制N+区掺杂离子区域的过刻蚀量,保证了N+区掺杂离子浓度不会因为过刻导致明显减少,保证N+区掺杂离子浓度的重复性和稳定性,从而保证批次间或同一批次不同的场效应晶体管保持相对稳定的RDSON参数。(The embodiment of the application provides a field effect power transistor and a manufacturing method thereof, and relates to the technical field of semiconductor device manufacturing. By controlling the thickness of the gate oxide layer and the polycrystalline layer, injected positive ions (such as boron positive ions) enter the JFET region and neutralize negative ions (such as phosphorus negative ions) in the JFET region, so that the concentration of conductive ions in the JFET region is reduced, the concentration stability of the conductive ions in the JFET region is ensured, double-power etching is used for etching the pin holes to control the over-etching amount of the doped ion region of the N + region, the concentration of the doped ions of the N + region is ensured not to be obviously reduced due to the over-etching, the repeatability and stability of the concentration of the doped ions of the N + region are ensured, and the relatively stable RDSON parameters of different field effect transistors in one batch or the same batch are ensured.)

1. A method of fabricating a field effect power transistor, the method comprising:

providing a substrate (101);

manufacturing a JFET area (104) and P well areas (103) positioned on two sides of the JFET area (104) on the upper surface of the substrate (101);

manufacturing a gate oxide layer (105) with the thickness range of 400-1200 angstrom on one side of the upper surface of the substrate (101);

manufacturing a polycrystalline layer (106) with the thickness not less than 5500 angstroms on the side, away from the substrate (101), of the gate oxide layer (105);

etching the polycrystalline layer (106) and the gate oxide layer (105) to form a P-type body region window, and manufacturing a P-type body region (107) on the upper surface of the substrate (101) by injecting ions and performing junction pushing treatment;

manufacturing an N + region (108) on the P-type body region (107), wherein the N + region (108) is adjacent to the P well region (103);

depositing an insulating layer (109) on one side of the upper surface of the substrate (101);

etching the insulating layer (109) on the two opposite sides of the upper surface of the substrate (101);

manufacturing a first metal layer (110) on one side of the upper surface of the substrate (101), wherein the first metal layer (110) is in contact with the P well region (103) and the N + region (108);

a second metal layer (111) is formed on the lower surface side of the substrate (101).

2. The method of manufacturing according to claim 1, wherein fabricating the JFET region (104) and the P-well region (103) on the upper surface of the substrate (101) comprises:

growing an oxide layer (102) with the thickness ranging from 4000 angstroms to 5000 angstroms on the upper surface of the substrate (101);

etching the oxide layer (102) to form a JFET area window and a P well area window respectively;

implanting ions into the substrate (101) through the JFET area window and the P well area window respectively;

and carrying out junction pushing treatment on the substrate (101) after ion implantation, and forming a JFET (junction field effect transistor) region (104) and a P well region (103) on the upper surface of the substrate (101).

3. The method as claimed in claim 2, wherein forming the gate oxide layer (105) with a thickness in the range of 400-1200 a on the upper surface of the substrate (101) comprises:

and growing a gate oxide layer (105) with the thickness of 400-1200 angstroms on the upper surface side of the substrate (101) in a growth temperature range of 950-1100 ℃ and in a growth environment with pure oxygen and trichloroethylene in a gaseous environment.

4. A method according to claim 3, wherein forming a polycrystalline layer (106) having a thickness of no less than 5500 angstroms on a side of the gate oxide layer (105) remote from the substrate (101) comprises:

and growing a polycrystalline layer (106) with the thickness not less than 5500 angstroms on the basis of the side of the gate oxide layer (105) far away from the substrate (101) at the growth temperature range of 500-800 ℃.

5. The method of claim 4, wherein forming an N + region (108) over said P-type body region (107) comprises:

coating a photoresist layer on the P-type body region (107);

etching the photoresist layer to obtain an N + region window;

and implanting arsenic ions with the dose not less than 3E15 into the P-type body region (107) through the N + region window under the implantation energy of 100-130Kev to obtain an N + region (108).

6. The method of claim 5, wherein etching the insulating layer (109) on opposite sides of the upper surface of the substrate (101) comprises:

-applying a photoresist layer on the insulating layer (109);

etching the photoresist layer, and etching lead region windows on the insulating layer (109) on two opposite sides of the upper surface of the substrate (101);

and etching the insulating layer (109) corresponding to the lead region window by adopting a mode of firstly carrying out high etching power and then carrying out low etching power to expose the N + region (108).

7. The method of manufacturing of claim 6, further comprising:

removing the photoresist in the window of the lead region by adopting a dry method twice;

removing an oxide layer and residual glue on the upper surface of the substrate (101) by adopting a mixed solution comprising an HF solution, an SC-1 solution and an SC-2 solution, wherein the SC-1 solution comprises NH with the mass ratio of 1:1:5-1:5:10₄OH、H₂O₂And H₂The O, SC-2 solution comprises HCL and H with the mass ratio of 1:1:5-1:5:10₂O₂And H₂O。

8. The fabrication method according to claim 7, wherein after fabricating the first metal layer (110) based on the upper surface side of the substrate (101), the fabrication method further comprises:

and carrying out alloying treatment on the first metal layer (110) and the substrate (101) under the working environment that the temperature is 380-450 ℃ and the gas environment is the mixed gas of nitrogen and hydrogen.

9. A field effect power transistor, comprising:

a substrate (101);

a JFET area (104) manufactured on the upper surface of the substrate (101) and P well areas (103) positioned on two sides of the JFET area (104);

a P-type body region (107) formed on the upper surface of the substrate (101) and located between the P-well region (103) and the JFET region (104), wherein the P-well region (103) is doped with positive ions, and the P-type body region (107) is also doped with positive ions;

an N + region (108) formed on the P-type body region (107) and adjacent to the P-well region (103);

a gate oxide layer (105) formed on one side of the upper surface of the substrate (101), wherein the gate oxide layer (105) at least covers the JFET region (104), and the thickness of the gate oxide layer (105) is 400-1200 angstroms;

a polycrystalline layer (106) manufactured on one side of the gate oxide layer (105) far away from the substrate (101), wherein the thickness of the polycrystalline layer (106) is not less than 5500 angstroms;

an insulating layer (109) formed on one side of the upper surface of the substrate (101), wherein the insulating layer (109) covers the polycrystalline layer (106);

a first metal layer (110) formed on one side of the upper surface of the substrate (101), wherein the first metal layer (110) covers the insulating layer (109), and the first metal layer (110) is in contact with the P-well region (103) and the N + region (108);

and the second metal layer (111) is manufactured on one side of the lower surface of the substrate (101).

10. The field effect power transistor as claimed in claim 9, characterized in that the thickness of the insulating layer (109) is 8000-.

Technical Field

The application relates to the technical field of semiconductor device manufacturing, in particular to a field effect power transistor and a manufacturing method thereof.

Background

The Field Effect power Transistor is widely used in electronic products in various fields of national economy, for example, a Vertical Double-diffused metal Oxide Semiconductor Field Effect Transistor (VDMOS) in the Field Effect Transistor, and an on-Resistance (RDSON) of the Field Effect power Transistor has an important meaning for product performance, and how to ensure that Field Effect transistors in different batches or in the same batch keep relatively stable RDSON parameters in a production process of the Field Effect power Transistor is a technical problem which needs to be solved urgently for technicians in the Field.

Disclosure of Invention

In order to overcome the technical problems mentioned in the above technical background, embodiments of the present application provide a field effect power transistor and a method for manufacturing the same.

In a first aspect of the present application, a method for manufacturing a field effect power transistor is provided, the method including:

providing a substrate (101);

manufacturing a JFET area (104) and P well areas (103) positioned on two sides of the JFET area (104) on the upper surface of the substrate (101);

manufacturing a gate oxide layer (105) with the thickness range of 400-1200 angstrom on one side of the upper surface of the substrate (101);

manufacturing a polycrystalline layer (106) with the thickness not less than 5500 angstroms on the side, away from the substrate (101), of the gate oxide layer (105);

etching the polycrystalline layer (106) and the gate oxide layer (105) to form a P-type body region window, and manufacturing a P-type body region (107) on the upper surface of the substrate (101) by injecting ions and performing junction pushing treatment;

manufacturing an N + region (108) on the P-type body region (107), wherein the N + region (108) is adjacent to the P well region (103);

depositing an insulating layer (109) on one side of the upper surface of the substrate (101);

etching the insulating layer (109) on the two opposite sides of the upper surface of the substrate (101);

manufacturing a first metal layer (110) on one side of the upper surface of the substrate (101), wherein the first metal layer (110) is in contact with the P well region (103) and the N + region (108);

a second metal layer (111) is formed on the lower surface side of the substrate (101).

In one possible embodiment of the present application, the making of the JFET region (104) and the P-well region (103) on the upper surface of the substrate (101) comprises:

growing an oxide layer (102) on the upper surface of the substrate (101) to a thickness in the range of 4000 angstroms to 5000 angstroms;

etching the oxide layer (102) to form a JFET area window and a P well area window respectively;

implanting ions into the substrate (101) through the JFET area window and the P well area window respectively;

and carrying out junction pushing treatment on the substrate (101) after ion implantation, and forming a JFET (junction field effect transistor) region (104) and a P well region (103) on the upper surface of the substrate (101).

In one possible embodiment of the present application, the fabricating a gate oxide layer (105) with a thickness in the range of 400-1200 angstroms on the upper surface side of the substrate (101) includes:

and growing a gate oxide layer (105) with the thickness of 400-1200 angstroms on the upper surface side of the substrate (101) in a growth temperature range of 950-1100 ℃ and in a growth environment with pure oxygen and trichloroethylene in a gaseous environment.

In one possible embodiment of the present application, fabricating a polycrystalline layer (106) having a thickness of no less than 5500 angstroms on a side of the gate oxide layer (105) away from the substrate (101) comprises:

and growing a polycrystalline layer (106) with the thickness not less than 5500 angstroms on the basis of the side of the gate oxide layer (105) far away from the substrate (101) at the growth temperature range of 500-800 ℃.

In one possible embodiment of the present application, fabricating an N + region (108) on the P-type body region (107) comprises:

coating a photoresist layer on the P-type body region (107);

etching the photoresist layer to obtain an N + region window;

and implanting arsenic ions with the dose not less than 3E15 into the P-type body region (107) through the N + region window under the implantation energy of 100-130Kev to obtain an N + region (108).

In one possible embodiment of the present application, etching the insulating layer (109) on two opposite sides of the upper surface of the substrate (101) includes:

-applying a photoresist layer on the insulating layer (109);

etching the photoresist layer, and etching lead region windows on the insulating layer (109) on two opposite sides of the upper surface of the substrate (101);

and etching the insulating layer (109) corresponding to the lead region window by adopting a mode of firstly carrying out high etching power and then carrying out low etching power to expose the N + region (108).

In one possible embodiment of the present application, the manufacturing method further includes:

removing the photoresist in the window of the lead region by adopting a dry method twice;

removing an oxide layer and residual glue on the upper surface of the substrate (101) by adopting a mixed solution comprising an HF solution, an SC-1 solution and an SC-2 solution, wherein the SC-1 solution comprises NH with the mass ratio of 1:1:5-1:5:10₄OH、H₂O₂And H₂The O, SC-2 solution comprises HCL and H with the mass ratio of 1:1:5-1:5:10₂O₂And H₂O。

In one possible embodiment of the present application, after fabricating the first metal layer (110) based on the upper surface side of the substrate (101), the fabrication method further includes:

and alloying the first metal layer (110) and the substrate (101) in a working environment with the temperature of 400 ℃ and the gaseous environment of mixed gas of nitrogen and hydrogen.

In a second aspect of the present application, there is also provided a field effect power transistor comprising:

a substrate (101);

a JFET area (104) manufactured on the upper surface of the substrate (101) and P well areas (103) positioned on two sides of the JFET area (104);

a P-type body region (107) formed on the upper surface of the substrate (101) and located between the P-well region (103) and the JFET region (104), wherein the P-well region (103) is doped with positive ions, and the P-type body region (107) is also doped with positive ions;

an N + region (108) formed on the P-type body region (107) and adjacent to the P-well region (103);

a gate oxide layer (105) formed on one side of the upper surface of the substrate (101), wherein the gate oxide layer (105) at least covers the JFET region (104), and the thickness of the gate oxide layer (105) is 400-1200 angstroms;

a polycrystalline layer (106) manufactured on one side of the gate oxide layer (105) far away from the substrate (101), wherein the thickness of the polycrystalline layer (106) is not less than 5500 angstroms;

an insulating layer (109) formed on one side of the upper surface of the substrate (101), wherein the insulating layer (109) covers the polycrystalline layer (106);

a first metal layer (110) formed on one side of the upper surface of the substrate (101), wherein the first metal layer (110) covers the insulating layer (109), and the first metal layer (110) is in contact with the P-well region (103) and the N + region (108);

and the second metal layer (111) is manufactured on one side of the lower surface of the substrate (101).

In one possible embodiment of the present application, the thickness of the insulating layer (109) is 8000-.

The embodiment of the application provides a field effect power transistor and a manufacturing method thereof, which effectively prevents injected positive ions (such as boron positive ions) from entering a JFET (junction field effect transistor) region (104) in the manufacturing process of a P-type body region (107) by controlling the thicknesses of a gate oxide layer (105) and a polycrystalline layer (106), and neutralizes negative ions (such as phosphorus negative ions) in the JFET region (104), so that the concentration of conductive ions in the JFET region (104) is reduced, the concentration of conductive ions in the JFET region (104) is ensured to be stable, and the field effect transistors in different batches or in the same batch are ensured to keep relatively stable RDSON parameters.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

Fig. 1 is a schematic cross-sectional view of a field effect power transistor according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart of a method for fabricating the field effect power transistor of fig. 1 according to an embodiment of the present disclosure;

fig. 3A-3K are process diagrams for fabricating the field effect power transistor of fig. 1 according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present application, it should be noted that the terms "upper", "lower", and the like refer to orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the application usually place when using, are only used for convenience of description and simplification of description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.

To solve the technical problems mentioned in the background, the inventors have innovatively designed the following field effect power transistor structure.

Referring to fig. 1, fig. 1 is a schematic structural cross-sectional view illustrating a field effect power transistor according to an embodiment of the present disclosure.

The field effect power transistor may include: substrate 101, P-well region 103, JFET region 104, gate oxide layer 105, poly layer 106, P-type body region 107, N + region 108, insulating layer 109, first metal layer 110, and second metal layer 111.

The JFET region 104 is located on the upper surface of the substrate 101, and the P-well region 103 is located on both sides of the JFET region 104. in the embodiment of the present application, the substrate 101 is an N-type semiconductor substrate, the JFET region 104 is doped with negative ions (e.g., phosphorus negative ions), and the P-well region 103 is doped with positive ions (e.g., boron positive ions).

A P-type body region 107 is located on the upper surface of substrate 101, and P-type body region 107 is located between P-well region 103 and JFET region 104, wherein the P-type body region is doped with positive ions (e.g., boron positive ions).

N + region 108 is located over P-type body region 107, and the N + region is adjacent to P-well region 103. The gate oxide layer 105 is formed on one side of the upper surface of the substrate 101, the gate oxide layer 105 at least covers the JFET region 104, and the thickness of the gate oxide layer 105 is 400-1200 angstroms.

The polycrystalline layer 106 is formed on the side of the gate oxide layer 105 away from the substrate 101, and the thickness of the polycrystalline layer 106 is not less than 5500 angstroms.

An insulating layer 109 is formed on the upper surface of the substrate 101, and the polycrystalline layer 106 is covered by the insulating layer 109. In the embodiment, the insulating layer 109 may be a Boro-phosphosilicate Glass (BPSG).

The first metal layer 110 is formed on one side of the upper surface of the substrate 101, the first metal layer 110 covers the insulating layer 109, and the first metal layer 110 contacts the P-well 103 and the N + region. In the embodiment of the present application, the first metal layer 110 may be a metal aluminum layer.

The second metal layer 111 is formed on the lower surface of the substrate 101. in the embodiment of the present invention, the second metal layer 111 may include three layers of metal, which are Ti, Ni and Ag in sequence, and the thickness of the second metal layer 111 ranges from 100 to 10000 angstroms.

In the embodiment of the present application, the gate layer 105 connects the metal electrode to serve as a gate of the field effect power transistor, the first metal layer 110 serves as a source of the field effect power transistor, and the second metal layer 111 serves as a drain of the field effect power transistor.

In the field-effect power transistor provided by the above embodiment, since the gate oxide layer 105 and the polycrystalline layer 106 are thicker, it is possible to effectively prevent the injected positive ions from entering the JFET region 104 during the manufacturing process of the P-type body region 107, and neutralize the negative ions in the JFET region 104, so that the concentration of the conductive ions in the JFET region 104 is reduced, and the concentration of the conductive ions in the JFET region 104 is ensured to be stable, thereby ensuring that different field-effect transistors in a batch or in the same batch maintain relatively stable RDSON parameters.

Referring to fig. 2, an embodiment of the present application further provides a manufacturing method for manufacturing the field effect power transistor, where the manufacturing method includes the following steps:

in step S201, a substrate 101 is provided.

Referring to FIG. 3A, a substrate with an N-type [110] crystal orientation is provided.

In step S202, a JFET region 104 and P-well regions 103 located on both sides of the JFET region 104 are formed on the upper surface of the substrate 101.

In the embodiment of the present application, the step S202 can be implemented by the following processes.

First, referring to fig. 3B, an oxide layer 102 is formed on the upper surface of the substrate 101.

Specifically, under a high temperature environment of 1100 ℃, hydrogen and oxygen are introduced to generate an oxide layer 102 on the upper surface of the substrate 101, and the thickness of the oxide layer 102 may range from 4000 angstroms to 5000 angstroms, and preferably, the thickness of the oxide layer 102 is 4500 angstroms.

Next, referring to fig. 3C, a JFET region window and a P-well region window are formed on the oxide layer 102 by coating photoresist, photolithography, etching, and removing photoresist, respectively.

Next, ions are implanted into the substrate 101 through the JFET region window and the P-well region window, respectively.

Specifically, phosphorus ions are implanted into the substrate 101 through the JFET region window at an implant energy of 100Kev, and the implantation amount of the phosphorus ions can be 1-4E 12; boron ions are then implanted into the substrate 101 through the P-well region window at an implant energy of 80Kev, which may be implanted at an implant rate of 5E14-1E 15.

Finally, referring to fig. 3D, the substrate 101 after ion implantation is subjected to junction pushing treatment, and a JFET region 104 and a P-well region 103 are formed on the upper surface of the substrate 101.

Specifically, a junction push-off process is performed for about 90-180 minutes in a nitrogen atmosphere at a high temperature of 1150 degrees celsius to form the JFET region 104 and the P-well region 103 on the upper surface of the substrate 101.

In the above process, a JFET region window may be formed on the oxide layer 102 by coating, photolithography, etching, and removing photoresist, and then ions may be implanted into the substrate 101 through the JFET region window; then, a P-well window is formed on the oxide layer 102 by coating photoresist, photoetching, etching and photoresist removal, and ions are implanted into the substrate 101 through the P-well window; finally, ion push junction processing is carried out to obtain a JFET region 104 and a P well region 103. It will be appreciated that the order of etching the JFET region windows and the P-well region windows and implanting ions can be adjusted.

In step S203, referring to fig. 3E, a gate oxide layer 105 with a thickness range of 400-.

Specifically, the gate oxide layer 105 with the thickness of 400-1200 angstroms is grown on the upper surface side of the substrate 101 in the growth temperature range of 950-1100 ℃ under the growth environment of pure oxygen and trichloroethylene in the gaseous environment.

In step S204, referring to fig. 3F, a polycrystalline layer 106 with a thickness not less than 5500 angstroms is formed on the side of the gate oxide layer 105 away from the substrate 101.

Specifically, polycrystalline layer 106 is grown to a thickness of no less than 5500 angstroms on the side of gate oxide layer 105 away from substrate 101 at a growth temperature in the range of 500-.

In steps S304 and S305, by controlling the thickness of the gate oxide layer and the polycrystalline layer, the injected positive ions can be effectively prevented from entering the JFET region during the manufacturing process of the P-type body region, and the negative ions in the JFET region are neutralized, so that the concentration of the conductive ions in the JFET region is reduced, and the concentration of the conductive ions in the JFET region is ensured to be stable, thereby ensuring that different field effect transistors in a batch or in the same batch maintain relatively stable RDSON parameters.

In step S205, referring to fig. 3G, a P-type body region window is formed by coating photoresist, photolithography, etching, and photoresist removal on the polycrystalline layer 106 and the gate oxide layer 105, and a P-type body region 107 is formed on the upper surface of the substrate 101 by ion implantation and junction push-off processing.

In step S205, boron positive ions are implanted into the substrate 101 through the P-type body region window at an implant energy of 80Kev-120Kev, and the implantation amount of the boron positive ions may range from 2E13 to 5E 13.

Specifically, during the junction pushing process of step S205, ions in the P-well region 103 continue to diffuse toward the lower surface of the substrate 101, so that the junction depth of the P-well region 103 becomes deeper, and in the embodiment of the present application, after step S205, the junction depth of the P-well region 103 is greater than the junction depth of the P-type body region 107.

In step S206, referring to fig. 3H, N + region 108 is formed on P-type body region 107, and N + region 108 is adjacent to P-well region 103.

In the embodiment of the present application, the step S206 can be realized by the following processes.

First, a photoresist layer is coated on the P-type body regions 107.

Then, photoetching, etching and removing the photoresist layer to obtain an N + region window;

finally, arsenic ions are implanted into the P-type body regions 107 through the N + region window at an implant energy of 80-130Kev at a dose not less than 3E15, resulting in N + regions 108.

In step S206, the dose of the implanted arsenic ions is large, so that the implanted arsenic ions can form a good ohmic contact with the silicon in the substrate 101 to form a good contact resistance, and the RDSON parameters are stable.

In step S207, referring to fig. 3I, an insulating layer 109 is deposited on one side of the upper surface of the substrate 101.

In step S208, referring to fig. 3J, the insulating layer 109 on two opposite sides of the upper surface of the substrate 101 is etched.

In the embodiment of the present application, the step S208 can be implemented by the following processes.

First, a photoresist layer is coated on the insulating layer 109.

Then, photoetching, etching and removing the photoresist layer, and etching a lead area window on the insulating layer 109 on two opposite sides of the upper surface of the substrate 101;

and finally, etching the insulating layer 109 corresponding to the window of the lead region by adopting a mode of firstly high etching power and then low etching power to expose the N + region 108.

In step S208, since the junction depth of the N + region 108 is shallow, the etching amount needs to be controlled when the window of the lead region is etched, and the etching manner of first high etching power and then low etching power can shorten the manufacturing time of the device and ensure that the N + region is not excessively etched to affect the RDSON parameters of the field effect power transistor.

In step S209, referring to fig. 3K, a first metal layer 110 is formed on one side of the upper surface of the substrate 101, and the first metal layer 110 is in contact with the P-well region 103 and the N + region 108.

In step S210, referring to fig. 1 again, a second metal layer 111 is formed on the lower surface of the substrate 101.

Further, in the embodiment of the present application, after step S208, the method for manufacturing a field effect power transistor further includes:

removing the photoresist in the window of the lead region by adopting a dry method twice;

removing an oxide layer and residual glue on the upper surface of the substrate 101 by adopting a mixed solution comprising an HF solution, an SC-1 solution and an SC-2 solution, wherein the SC-1 solution comprises NH with the mass ratio of 1:1:5-1:5:10₄OH、H₂O₂And H₂The O, SC-2 solution comprises HCL and H with the mass ratio of 1:1:5-1:5:10₂O₂And H₂O。

Further, after step S209, the method for manufacturing a field effect power transistor further includes:

and alloying the first metal layer 110 and the substrate 101 at 380-450 ℃ in a working environment in which the gas environment is a mixed gas of nitrogen and hydrogen.

Through the photoresist stripping operation in the above steps, the first metal layer 110 and the silicon corresponding to the lead area window can form a good alloy, so as to ensure the stability of the RDSON parameters of the field effect power transistor, and prevent the RDSON parameters from increasing due to the fact that the silicon corresponding to the lead area window and the first metal layer 110 cannot form a good alloy due to the existence of residual photoresist. Further, before the first metal layer 110 is manufactured, the SC-1 solution and the SC-2 solution are used to remove the oxide layer on the upper surface of the substrate 101, so that the first metal layer 110 and the silicon corresponding to the lead area window can be ensured to form a good alloy.

In summary, the embodiments of the present application provide a field effect power transistor and a method for manufacturing the same. By controlling the thickness of the gate oxide layer and the polycrystalline layer, injected positive ions (such as boron positive ions) enter the JFET region and neutralize negative ions (such as phosphorus negative ions) in the JFET region in the manufacturing process of the P-type body region, so that the concentration of conductive ions in the JFET region is reduced, the concentration of the conductive ions in the JFET region is ensured to be stable, and the RDSON parameter of the field effect power transistor is ensured to be stable. Further, when the N + region 108 is obtained, the ions with a larger implantation dose can ensure that the N + region 108 and the substrate 101 form a good ohmic contact, and simultaneously, by controlling the etching mode of the N + region, the RDSON parameters of the field effect power transistor can also be ensured to be stable. And further removing the photoresist twice by a dry method, and cleaning the SC-1 and SC-2 to remove the photoresist layer and the oxide layer, thereby further ensuring the stability of RDSON parameters of the field effect power transistor. By controlling each step in the manufacturing process, the field effect transistors in different batches or in the same batch can be ensured to keep relatively stable RDSON parameters.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.