阅读说明：本技术 双向晶闸管器件 (Bidirectional thyristor device ) 是由 J·伏贝基 U·维穆拉帕蒂 M·拉希莫 于 2019-02-13 设计创作，主要内容包括：提供了一种双向晶闸管装置(100),其中,半导体晶片按照从第一主侧(102)到第二主侧(104)的顺序包括第一导电类型的第一半导体层(106)、第二导电类型的第二半导体层(108)、第一导电类型的第三半导体层(110)、第二导电类型的第四半导体层(112)以及第一导电类型的第五半导体层(114)。第一主电极(115)形成在第一主侧上(102)并且第二主电极(116)形成在第二主侧(104)上。第一发射极短路部(128)穿透第一半导体层(106),以将第一主电极(115)与第二半导体层(108)电连接,并且第二发射极短路部(138)穿透第五半导体层(114),以将第二主电极(116)与第四半导体层(112)电连接。在平行于第一主侧(102)的平面上的正交投影中,由第一半导体层(106)和第一发射极短路部(128)占据的第一区与由第五半导体层(114)和第二发射极短路(138)占据的第二区在重叠区中重叠,其中,第一发射极短路部(128)和第二发射极短路部(138)位于重叠区内。(A triac device (100) is provided wherein a semiconductor wafer comprises, in order from a first main side (102) to a second main side (104), a first semiconductor layer (106) of a first conductivity type, a second semiconductor layer (108) of a second conductivity type, a third semiconductor layer (110) of the first conductivity type, a fourth semiconductor layer (112) of the second conductivity type and a fifth semiconductor layer (114) of the first conductivity type. A first main electrode (115) is formed on the first main side (102) and a second main electrode (116) is formed on the second main side (104). A first emitter short (128) penetrates the first semiconductor layer (106) to electrically connect the first main electrode (115) with the second semiconductor layer (108), and a second emitter short (138) penetrates the fifth semiconductor layer (114) to electrically connect the second main electrode (116) with the fourth semiconductor layer (112). In an orthogonal projection on a plane parallel to the first main side (102), a first region occupied by the first semiconductor layer (106) and the first emitter short (128) overlaps a second region occupied by the fifth semiconductor layer (114) and the second emitter short (138) in an overlap region, wherein the first emitter short (128) and the second emitter short (138) are located within the overlap region.)

1. A triac device (100), the triac device comprising:

a semiconductor wafer having a first main side (102) and a second main side (104) opposite to the first main side (102);

a first main electrode (115) arranged on the first main side (102);

a first gate electrode (135) arranged on the first main side (102) and separated from the first main electrode (115);

a second main electrode (116) arranged on the second main side (104); and

a second gate electrode (145) arranged on the second main side (104) and separated from the second main electrode (116),

wherein the semiconductor wafer comprises the following layers in order from the first main side (102) to the second main side (104):

a first semiconductor layer (106) having a first conductivity type, the first semiconductor layer (106) being in direct contact with the first main electrode (115);

a second semiconductor layer (108) having a second conductivity type different from the first conductivity type, wherein the second semiconductor layer (108) is in direct contact with the first gate electrode (135), and wherein the first semiconductor layer (106) and the second semiconductor layer (108) form a first p-n junction (J-n junction)₁)；

A third semiconductor layer (110) having the first conductivity type, the second semiconductor layer (108) and the third semiconductor layer (110) forming a second p-n junction (J)₂)；

A fourth semiconductor layer (112) having the second conductivity type, wherein the third semiconductor layer (110) and the fourth semiconductor layer (112) form a third p-n junction (J)₃) And wherein the fourth semiconductor layer (112) is in direct contact with the second gate electrode (116); and

a fifth semiconductor layer (114) having the first conductivity type and being in direct contact with the second main electrode (116), wherein the fourth semiconductor layer (112) and the fifth semiconductor layer (114) form a fourth p-n junction (J)₄)，

Characterized by a plurality of first emitter shorts (128), each first emitter short (128) penetrating the first semiconductor layer (106) to electrically connect the second semiconductor layer (108) with the first main electrode (115), and

a plurality of second emitter shorts (138), each second emitter shorts (138) penetrating the fifth semiconductor layer (114) to electrically connect the fourth semiconductor layer (112) with the second main electrode (116), wherein:

in an orthogonal projection on a plane parallel to the first main side (102), a first region occupied by the first semiconductor layer (106) and the first emitter short (128) overlaps a second region occupied by the fifth semiconductor layer (114) and the second emitter short (138) in an overlap region,

in the orthogonal projection on a plane parallel to the first main side (102), the first emitter short (128) and the second emitter short (138) are located within the overlap region, and

in the orthogonal projection on a plane parallel to the first main side (102), the overlap region in which the first region overlaps the second region covers at least 50% of a total wafer area occupied by the semiconductor wafer.

2. The bidirectional thyristor device according to claim 1, wherein, in the orthogonal projection on a plane parallel to the first main side (102), the first emitter short (128) occupies at least 2%, such as at least 5%, such as at least 8%, further such as at least 10%, of the overlap region.

3. Thyristor device according to claim 1 or 2, wherein the second emitter short (138) occupies at least 2%, such as at least 5%, such as at least 8% and further such as at least 10% of the overlap region in the orthogonal projection on a plane parallel to the first main side (102).

4. The bidirectional thyristor device according to any one of claims 1 to 3, wherein the first emitter short (138) is discrete in the orthogonal projection on a plane parallel to the first main side (102).

5. The triac device according to claim 4, wherein a distance between two adjacent first emitter shorts (128) varies in such a way that an average distance between two adjacent first emitter shorts (128) decreases with increasing distance from the first gate electrode (135).

6. The bidirectional thyristor device of any of claims 1 to 5, wherein the second emitter short (138) is discrete in the orthogonal projection on a plane parallel to the first main side (102).

7. The bidirectional thyristor device according to claim 6, wherein the distance between two adjacent second emitter shorts (138) varies in such a way that the average distance between two adjacent second emitter shorts (138) decreases with increasing distance from the second gate electrode (145).

8. The bidirectional thyristor device according to any of claims 1 to 7, wherein, in the orthogonal projection on a plane parallel to the first main side (102), the first emitter short (128) and the second emitter short (138) have a lateral dimension in the range from 30 μ ι η to 500 μ ι η, for example in the range from 50 μ ι η to 200 μ ι η.

9. The bidirectional thyristor device of any of claims 1 to 8, wherein at least the first gate electrode (135) or the second gate electrode (145) has rotational symmetry in the orthogonal projection on a plane parallel to the first main side (102).

10. The bidirectional thyristor device of any of claims 1 to 9, wherein the first gate electrode (135) and the second gate electrode (145) have the same shape in the orthogonal projection on a plane parallel to the first main side (102).

11. The bidirectional thyristor device of any of claims 1 to 10, wherein the third semiconductor layer (110) is used inHas a density of deep energy levels with a distance (J) from said third p-n junction₃) Is closer to the second p-n junction (J)₂) First local maximum (P) of₁) And/or with said second p-n junction (J)₂) Is closer to the third p-n junction (J)₃) Second local maximum (P)₂)。

12. The bidirectional thyristor device of claim 11, wherein the first local maximum (P) is₁) From the second p-n junction (J)₂) Less than 50 μm, and/or wherein the second local maximum (P)₂) From the third p-n junction (J)₃) Less than 50 μm.

13. The bidirectional thyristor device of any of claims 1 to 12, wherein excess carrier lifetime has a junction (J) in the third semiconductor layer (110) with the third p-n junction (J) from the third semiconductor layer₃) Is closer to the second p-n junction (J)₂) And/or with the second p-n junction (J)₂) Is closer to the third p-n junction (J)₃) Of the second local minimum.

14. The bidirectional thyristor device of claim 13, wherein the first local minimum is spaced from the second p-n junction (J)₂) Less than 50 μm, and/or wherein the second local minimum is spaced from the third p-n junction (J)₃) Less than 50 μm.

Technical Field

The present invention relates to a bidirectional thyristor device implemented in a single semiconductor wafer.

Background

A thyristor, sometimes also referred to as a Silicon Controlled Rectifier (SCR), is a switching semiconductor device that can be turned on in the forward direction (i.e., when forward biased) by providing a positive gate trigger current pulse to the gate terminal. The thyristor is then said to be in a forward conducting state or conducting state, wherein current may flow in a forward direction from the anode to the cathode. On the other hand, the thyristor may also be in a forward blocking state (also referred to as an off-state), which means that a high current flowing through the anode may be blocked and the thyristor is subjected to a higher positive voltage in the forward direction. In the reverse direction, which is opposite to the forward direction, the thyristor cannot turn on. The thyristor may be reverse blocking, meaning that it can maintain at least approximately the same voltage in the reverse direction as the forward blocking state without significant current flow, or may be asymmetric, meaning that it has little blocking capability in the reverse direction. Phase-controlled thyristors (PCT) (adapted for 50/60Hz frequency) are typically reverse blocking, since phase control applications typically require reverse blocking capability.

The known thyristor comprises an emitter short-circuit for controlling the diffusion of the plasma in the lateral direction and reducing the amplification factor of the internal NPN transistor when the thyristor is turned on, thereby reducing the leakage current and increasing the dV/dt capability during a fast rise of the forward blocking voltage (i.e. without triggering at zero gate current when an anode forward voltage with a high dV/dt is applied). According to WO 2011/161097a2, the emitter short-circuit pattern of the thyristor should be as uniform and homogeneous as possible, ideally with a constant density of short-circuits throughout the cathode region and all its subregions, in particular in the cathode region close to the gate structure, in order to achieve a high lateral plasma diffusion speed and a high maximum current variation di/dt.

In many applications (e.g., matrix converters), both Direct Current (DC) breaker and Static VAR Compensator (SVC) bi-directional power device functionality are required to block voltage and conduct current in both directions. For bi-directional power semiconductor device functionality, it is now common to use two Reverse Blocking (RB) thyristors in an anti-parallel configuration, or two Reverse Conducting (RC) thyristors in a back-to-back configuration. The configuration of two RC thyristors with a back-to-back configuration has the disadvantage of high losses, since the losses of the two thyristors are superimposed in series.

From US 3476993 a there is known a five-layer switching device having two thyristor structures in an anti-parallel configuration. However, the two thyristor structures use different regions of the semiconductor wafer, so that in the known five-layer switching device no regions of the semiconductor wafer can be effectively utilized.

From US 2004/0183092 a1 there is known a thyristor structure having three separate lifetime control regions inside the low doped intermediate semiconductor layer of the thyristor structure.

In the Bidirectional Controllable Thyristor (BCT) disclosed in EP 0880182B 1, two antiparallel thyristors are integrated onto a single wafer and assembled into one housing. By integrating the two thyristor halves in a single package, BCT allows for a more compact design of the device, simplifies the cooling system for high power applications, and improves system reliability. However, in BCT, less than half of the die area can be used per current direction or polarity. A major challenge in the integration of two thyristor halves in BCT is to avoid crosstalk between the two thyristor halves, which are separated from each other by a separation region in the semiconductor wafer. Another problem in the operation of BCT devices is thermal management because heat generation is unevenly distributed across the wafer area.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a bidirectional thyristor device that efficiently uses the entire device region for both current directions to provide a smaller device with good electrical and thermal performance.

The object of the invention is achieved by a triac device according to claim 1.

The bidirectional thyristor device has a structure in which the first semiconductor layer can be considered as a cathode of a first thyristor, and the fifth semiconductor layer can be considered as a cathode of a second thyristor connected to the first thyristor in an anti-parallel configuration. The first emitter short in combination with the second semiconductor layer may be considered as an anode of the second thyristor, and the second emitter short in combination with the fourth semiconductor layer may be considered as an anode of the first thyristor. Therefore, in the triac device of the present invention, the cathodes and anodes of the first thyristor and the second thyristor are staggered with each other in such a manner that the first emitter short of the first thyristor is used for the anode of the second thyristor and the second emitter short of the second thyristor is used for the anode of the first thyristor.

In the present invention, the first thyristor and the second thyristor are integrated in a single semiconductor die in an anti-parallel configuration between a first main electrode and a second main electrode. Compared to the known BCT, no separation region is required between the two thyristors, and the triac device of the present invention can use the die regions for both polarities more efficiently, respectively, due to the overlap between the first region occupied by the first semiconductor layer and the first emitter short and the second region occupied by the fifth semiconductor layer and the second emitter short in an orthogonal projection on a plane parallel to the first main side.

In the triac device, an overlap region in which the first region overlaps the second region covers at least 50% of a total wafer area occupied by the semiconductor wafer when viewed in orthogonal projection on a plane parallel to a first main side of the semiconductor wafer. Thus, at least 50% of the total wafer area is used for both polarities, respectively.

Further developments of the invention are specified in the dependent claims.

In an exemplary embodiment of the triac device, the first emitter short occupies at least 2%, such as at least 5%, such as at least 8%, further such as at least 10% of the overlap region, when viewed in orthogonal projection on a plane parallel to the first main side. In the case where the area occupied by the first emitter short is relatively large, the on-state voltage of the second thyristor at high anode currents can be reduced compared to a thyristor device having the same structure but with a smaller area occupied by the first emitter short.

In an exemplary embodiment of the triac device, the second emitter short occupies at least 2%, such as at least 5%, such as at least 8%, further such as at least 10% of the overlap region, when viewed in orthogonal projection on a plane parallel to the first main side. In the case where the area occupied by the second emitter short is relatively large, the on-state voltage of the first thyristor at a high anode current can be reduced compared to a thyristor device having the same structure but a smaller area occupied by the first emitter short.

In an exemplary embodiment of the triac device, the first emitter short is discrete when viewed in orthogonal projection on a plane parallel to the first main side. The discrete first emitter shorts allow a particularly efficient diffusion of plasma in a lateral direction when the first thyristor is switched from a forward blocking state (off-state) to a forward conducting state (on-state). Throughout the description, the transverse direction refers to a direction parallel to the first main side. The distance between two adjacent discrete first emitter shorts may vary in such a way that the average distance between two adjacent first emitter shorts decreases with increasing distance from the first gate electrode, i.e. the density of first emitter shorts increases with increasing lateral distance from said first gate electrode. This variation in the density of the first emitter shorts allows the second thyristor to have a relatively low on-state voltage at high anode currents while the first thyristor can be triggered at relatively low anode currents (i.e., the first thyristor has a high di/dt capability). Throughout the specification, the average distance between two adjacent emitter shorts at a certain distance d from the gate electrode means an arithmetic average of distances between all pairs of adjacent first emitter shorts in a zone including all positions having distances ranging from d to d + Δ d, where Δ d is constant for calculation of the average distance at all distances d, e.g., Δ d ═ 5 mm.

In an exemplary embodiment of the triac device, the second emitter short is discrete in an orthogonal projection on a plane parallel to the first main side. The discrete second emitter shorts allow a particularly efficient diffusion of the plasma in the lateral direction when said second thyristor is switched from the off-state to the on-state. The distance between two adjacent discrete second emitter shorts may vary in such a way that the average distance between two adjacent second emitter shorts decreases with increasing distance from the second gate electrode, i.e. the density of the second emitter shorts increases with increasing lateral distance from the second gate electrode. This variation in the density of the second emitter shorts allows the first thyristor to have a relatively low on-state voltage at high anode currents, while the second thyristor can be triggered at relatively low anode currents (i.e., the second thyristor has a high di/dt capability).

As described above, the distance between two adjacent discrete first (second) emitter shorts may vary in such a way that the average distance between two adjacent first (second) emitter shorts decreases with increasing distance from the second gate electrode, i.e. the density of the second emitter shorts increases with increasing lateral distance from the second gate electrode. In addition, there may be channels in the high density region of the shorts that have a lower density of first (second) emitter shorts to allow for fast conduction (i.e., faster plasma diffusion) through these channels even in regions away from the gate. This function is important especially for large area devices.

In an exemplary embodiment, the first emitter short and the second emitter short have a lateral dimension in a range from 30 μm to 500 μm, for example in a range from 50 μm to 200 μm, when viewed in orthogonal projection on a plane parallel to the first main side.

In an exemplary embodiment, at least the first gate electrode or the second gate electrode has rotational symmetry in an orthogonal projection on a plane parallel to the first main side. This shape of the gate electrode with rotational symmetry allows the die region of the thyristor to be used more efficiently in a ceramic hockey-package (ceramic package) and improves the thermal management of the device.

In an exemplary embodiment, the first gate electrode and the second gate electrode have the same shape when viewed in orthogonal projection on a plane parallel to the first main side. This identical shape of the first gate electrode and the second gate electrode allows to simplify the process of manufacturing the device, since the same mask design may be used for constructing the first gate electrode and the second gate electrode.

In an exemplary embodiment, the density of deep energy levels used as recombination centers in the third semiconductor layer has a first local maximum closer to the second p-n junction than to the third p-n junction and/or a second local maximum closer to the third p-n junction than to the second p-n junction. The first local maximum may, for example, be less than 50 μm from the second p-n junction and/or the second local maximum may, for example, be less than 50 μm from the third p-n junction. The local maximum of the density of deep energy levels used as recombination centers in the third semiconductor layer near the second p-n junction and/or the third p-n junction may improve the turn-off capability of the bidirectional thyristor device by commutation of the anode voltage.

In an example embodiment, the excess carrier lifetime has a first local minimum closer to the second p-n junction than to the third p-n junction and/or a second local minimum closer to the third p-n junction than to the second p-n junction. The first local minimum may, for example, be less than 50 μm from the second p-n junction and/or the second local minimum may, for example, be less than 50 μm from the third p-n junction. Local minima of excess carrier lifetime in the third semiconductor layer near the second p-n junction and/or the third p-n junction may improve the turn-off capability of the bidirectional thyristor device by commutation of the anode voltage.

Drawings

Detailed embodiments of the present invention will be described below with reference to the accompanying drawings, in which:

fig. 1 illustrates a cross-sectional view of a bidirectional thyristor device according to an embodiment of the invention.

Fig. 2 shows a top view of the bidirectional thyristor device of fig. 1;

fig. 3 shows a bottom view of the triac device of fig. 2.

FIG. 4 illustrates I-V curves for a bidirectional thyristor device having different patterns of first and second emitter shorts;

fig. 5 shows a cross-sectional view of the triac device of fig. 1 and a graph showing a spatial distribution of deep energy levels in the energy band gap (point defect);

fig. 6a shows results of an extended resistance test of a specific example of a bidirectional thyristor device according to an embodiment; and

fig. 6b shows the results of an extended resistance test of another specific example of a bidirectional thyristor device according to an embodiment.

The reference symbols used in the drawings and their meanings are summarized in the list of reference symbols. Generally, similar elements have the same reference numerals throughout the specification. The described embodiments are to be considered in all respects only as illustrative and not restrictive.

Detailed Description

Fig. 1 shows a longitudinal cross-section of a triac device 100 according to an embodiment of the present invention, fig. 2 shows a top view of the triac device 100, and fig. 3 shows a bottom view of the triac device 100. The triac device 100 includes a semiconductor wafer having a first main side 102 and a second main side 104 opposite and parallel to the first main side 102. The plane of the diagram in fig. 1 is a plane perpendicular to the first main side 102. The cross-section shown in fig. 1 is taken along the line a-a' of fig. 2 and 3, respectively.

The semiconductor wafer comprises n in order from the first main side 102 of the semiconductor wafer⁺A doped first semiconductor layer 106, a p-doped second semiconductor layer 108, n^-A doped third semiconductor layer 110, a p-doped fourth semiconductor layer 112 and n⁺A doped fifth semiconductor layer 114. n is⁺The doped first semiconductor layer 106 and the p-doped second semiconductor layer 108 form a first p-n junction J₁P-doped second semiconductor layer 108 and n^-The doped third semiconductor layer 110 forms a second p-n junction J₂，n^-The doped third semiconductor layer 110 and the p-doped fourth semiconductor layer 112 form a third p-n junction J₃And p-doped fourth semiconductor layer 112 and n⁺The doped fifth semiconductor layer 114 forms a fourth p-n junction J₄. A plurality of first emitter shorts 128 is arranged at the first main side 102, wherein each first emitter short 128 is a p-type semiconductor region penetrating the first semiconductor layer 106 to electrically connect the p-type second semiconductor layer 108 with the first main electrode 115. The doping level of the first emitter short 128 can be, for example, p-dopedThe doping level of the doped second semiconductor layer 108 is the same or may be higher than the doping level of the p-doped second semiconductor layer 108. Likewise, a plurality of second emitter shorts 138 is provided at the second main side 104, wherein each second emitter short 138 is a p-type semiconductor region penetrating through the n-type semiconductor region⁺A fifth semiconductor layer 114 doped to electrically connect the p-type fourth semiconductor layer 112 with the second main electrode 116. The doping level of the second emitter short 138 may, for example, be the same as the doping level of the p-doped fourth semiconductor layer 112 or may be higher than the doping level of the p-doped fourth semiconductor layer 112. In an embodiment, first emitter short 128 and second emitter short 138 are discrete. For example, first emitter short 128 and second emitter short 138 may be dot-shaped in orthogonal projection on a plane parallel to first main side 102 and may have a lateral dimension in the range of 30 μm to 500 μm, for example in the range of 50 μm to 200 μm. Wherein the lateral dimension is defined as the largest lateral dimension in an orthogonal projection on a plane parallel to the first main side 102. Alternatively, first emitter short 128 and second emitter short 138 may be polygonal.

On the first main side 102 of the semiconductor wafer, a first main electrode 115 is arranged, which first main electrode is connected to n⁺The doped first semiconductor layer 106 is in direct contact with n⁺The doped first semiconductor layer 106 forms an ohmic contact. Likewise, on the second main side 104 of the semiconductor wafer, a second main electrode 116 is arranged, which second main electrode is connected to n⁺The doped fifth semiconductor layer 114 is in direct contact with n⁺The doped fifth semiconductor layer 114 forms an ohmic contact. A first amplification gate electrode 135 (which is an example of a first gate electrode recited in the claims) is arranged on the first main side 102. The first amplification gate electrode 135 is electrically separated from the first main electrode 115 and directly contacts the p-doped second semiconductor layer 108 to form an ohmic contact with the p-doped second semiconductor layer 108 at a position lateral to the first main electrode 115. As best seen in fig. 2, the first amplification gate electrode 135 includes a first ring electrode concentric with the center of the semiconductor in plan viewThe pole portion 135a, the first finger electrode portion 135b extending from the first ring electrode portion 135a toward the outer edge termination region 191 of the semiconductor wafer in the top view, and the second finger electrode portion 135c branching off from the first finger electrode portion 135b and extending toward the outer edge termination region 191 of the semiconductor wafer.

Similarly, as can be seen in fig. 1 or 3, a second amplifying gate electrode 145 (which is one example of a second gate electrode recited in the claims) is arranged on the second main side 104. The second amplification gate electrode 145 is electrically separated from the second main electrode 116 and directly contacts the p-doped fourth semiconductor layer 112 to form an ohmic contact with the p-type doped fourth semiconductor layer 112 at a position lateral to the second main electrode 116. As best seen in fig. 3, the second amplification gate electrode 145 includes a second ring electrode portion 145a concentric with the center of the semiconductor in plan view, a third finger electrode portion 145b extending from the first ring electrode portion 145a toward the outer edge termination region 191 of the semiconductor wafer in plan view, and a fourth finger electrode portion 145c diverging from the third finger electrode portion 145b toward the edge termination region 191 of the semiconductor wafer shown in fig. 2 or 3.

In an orthogonal projection on a plane parallel to the first main side 102, the region occupied by the first semiconductor layer 106 and the first emitter short 128 will be referred to as first region. Similarly, in an orthogonal projection on a plane parallel to the first main side 102, the region occupied by the fifth semiconductor layer 114 and the second emitter short 138 will be referred to as a second region. The area where the first region overlaps the second region in orthogonal projection on a plane parallel to the first main side 102 is called an overlap area. In an orthogonal projection on a plane parallel to the first main side 102, the first emitter short 128 and the second emitter short 138 are located within the overlap region. In the bidirectional thyristor device 100 according to an embodiment, the first region is identical to the second region, i.e. there is a perfect overlap between the first region and the second region.

A first thyristor comprising four semiconductor layers of alternating conductivity type (i.e., n-p-n-p layer stack) is formed of n in the triac device 100⁺Doped first semiconductor layer 106, p-doped second semiconductor layer108、n^-A doped third semiconductor layer 110, a p-doped fourth semiconductor layer 112 and a second emitter short 138. n is⁺The doped first semiconductor layer 106 is the cathode emitter layer of the first thyristor, the p-doped second semiconductor layer 108 is the p-doped base layer of the first thyristor, n^-The doped third semiconductor layer 110 is n of the first thyristor^-The doped base layer and the p-doped fourth semiconductor layer 112 and the second emitter short 138 together form the anode layer of the first thyristor. The first main electrode 115 is a cathode electrode of the first thyristor, and the second main electrode 116 is an anode electrode of the first thyristor.

The second thyristor, which includes four semiconductor layers having alternating conductivity types (i.e., n-p-n-p layer stack structure), is formed of n in the triac device 100⁺Doped fifth semiconductor layer 114, p-doped fourth semiconductor layer 112, n^-A doped third semiconductor layer 110, a p-doped second semiconductor layer 108, and a first emitter short 128. n is⁺The doped fifth semiconductor layer 114 is the cathode emitter layer of the second thyristor, the p-doped fourth semiconductor layer 112 is the p-doped base layer of the second thyristor, n^-The doped third semiconductor layer 110 is n of the second thyristor^-The doped base layer and the p-doped second semiconductor layer 108 together with the first emitter short 128 form the anode layer of the second thyristor. The second main electrode 116 is the cathode electrode of the second thyristor and the first main electrode 115 is the anode electrode of the second thyristor.

Thus, the first thyristor and the second thyristor are integrated in the triac device 100 in an anti-parallel configuration between the first main electrode 115 and the second main electrode 116.

To facilitate the triggering of the first thyristor in the triac device 100, a first auxiliary thyristor is provided. The first auxiliary thyristor may also be referred to as a first pilot thyristor and is arranged laterally beside the first thyristor in the semiconductor wafer. In an orthogonal projection on a plane parallel to the first main side 102, the first auxiliary thyristor is positioned in a central region of the wafer. The first auxiliary thyristor comprisesThere are four semiconductor layers of alternating conductivity type (i.e. an n-p-n-p layer stack similar to the first thyristor). The first auxiliary thyristor is formed from n in order from the first main side 102 of the semiconductor wafer to the second main side 104 of the semiconductor wafer⁺A doped first auxiliary cathode emitter layer 152, a p-doped second semiconductor layer 108, n^-A doped third semiconductor layer 110 and a p-doped fourth semiconductor layer 112 and a second emitter short 138. In orthogonal projection on a plane parallel to the first main side 102, n⁺The doped first auxiliary cathode emitter layer 152 is ring-shaped around the lateral center of the semiconductor wafer. n is⁺The doped first auxiliary cathode emitter layer 152 overlaps and electrically contacts the inside of the ring-shaped electrode portion 135a formed on the first main side 102 of the semiconductor wafer. In an embodiment, the first amplification gate electrode 135 is an amplification gate for the first thyristor. In the center of the semiconductor wafer, a first main gate electrode 175 is formed on the first main side 102 to be in direct contact with the p-doped second semiconductor layer 108.

To facilitate the triggering of the second thyristor in the triac device 100, a second auxiliary thyristor is provided. The second auxiliary thyristor may also be referred to as a second pilot thyristor and is arranged laterally beside the second thyristor in the semiconductor wafer. In an orthogonal projection on a plane parallel to the first main side 102, the second auxiliary thyristor is positioned in a central region of the semiconductor wafer. The first auxiliary thyristor comprises four semiconductor layers of alternating conductivity type, i.e. an n-p-n-p layer stack similar to the second thyristor. The second auxiliary thyristor is formed from n in order from the second main side 104 of the semiconductor wafer to the first main side 102 of the semiconductor wafer⁺A doped second auxiliary cathode emitter layer 162, a p-doped fourth semiconductor layer 112, n^-The doped third semiconductor layer 110 and the p-doped second semiconductor layer 112 as well as the first emitter short 128. In orthogonal projection on a plane parallel to the first main side 102, n⁺The doped second auxiliary cathode emitter layer 162 is ring-shaped around the lateral center of the semiconductor wafer. n is⁺A doped second auxiliary cathode emitter layer 162 and a doped second auxiliary cathode emitter layerThe inside of the ring-shaped electrode portion 145a formed on the second main side 104 of the conductor wafer overlaps and electrically contacts. In an embodiment, the second amplification gate electrode 145 is an amplification gate for a second thyristor. In the center of the semiconductor wafer, a second main gate electrode 185 is formed on the second main side 104 to be in direct contact with the p-doped fourth semiconductor layer 112.

The first main gate electrode 175 may be connected to a gate unit (not shown) via a first thin cable (not shown), and the first main electrode 115 may be contacted by pressing a first molybdenum pad (not shown) thereon. Also, the second main gate electrode 185 may be connected to a gate unit (not shown in the drawings) via a second thin cable (not shown in the drawings), and the second main electrode 116 may be contacted by pressing a second molybdenum pad (not shown in the drawings) thereon.

In operation, the formation of the plasma will be in the p-doped second semiconductor layer 108 in the direction away from the first amplification gate electrode 135 in the n-doped second semiconductor layer 108 during the triggering of the first thyristor^-In the doped third semiconductor layer 110 and in the p-doped fourth semiconductor layer 112, wherein the ignition process is accelerated by the distributed gate structure provided by the first amplifying gate electrode 135. Likewise, the formation of the plasma will be in the p-doped fourth semiconductor layer 112 in a direction away from the second amplification gate electrode 145 during the triggering of the second thyristor, in the n-direction^-In the doped third semiconductor layer 110 and in the p-doped second semiconductor layer 108, wherein the ignition process is accelerated by the distributed gate structure provided by the second amplifying gate electrode 145.

The first emitter short 128 may occupy at least 2%, such as at least 5%, such as at least 8%, further such as at least 10% of an overlap region where the first region and the second region overlap, when viewed in orthogonal projection on a plane parallel to the first main side 102. Likewise, the second emitter short 138 may occupy at least 2%, such as at least 5%, such as at least 8%, further such as at least 10% of an overlap region where the first region and the second region overlap, when viewed in orthogonal projection on a plane parallel to the first main side.

Furthermore, in the triac device 100 of the embodiment, the first emitter shorts 128 are distributed in an orthogonal projection on the first main side 102 in such a way that the distance between two adjacent discrete first emitter shorts 128 decreases with increasing distance from the first amplification gate electrode 135. This variation in the density of the first emitter shorts 128 allows the second thyristor to have a relatively low on-state voltage at high anode currents while the first thyristor can be triggered at relatively low anode currents (i.e., the first thyristor has a high di/dt capability). Wherein the average distance between two adjacent first emitter shorts 128 at a certain distance d from the first amplification gate electrode 135 represents the arithmetic average of all pairs of adjacent first emitter shorts 128 in a region including all positions having distances in the range of d to d + Δ d, where Δ d is constant for the calculation of the average distance at all distances d, e.g., Δ d ═ 5 mm. The density of first emitter shorts 128 may continuously increase with increasing distance from first amplification gate electrode 135, or increase stepwise, i.e., there is a first region near the first gate region where the density of first emitter shorts 128 is relatively low (i.e., the average distance between adjacent first emitter shorts 128 is relatively high) and a second region farther from first amplification gate electrode 135 than the first region (i.e., the second region is separated from first amplification gate electrode 135 by the first region) than the first region; in the second region, the density of the first emitter shorts 128 is higher compared to the density of the first emitter shorts 128 in the first region (i.e., the average distance between adjacent first emitter shorts 128 is lower compared to the average distance in the first region).

Likewise, in the triac device 100 of the embodiment, the second emitter shorts 138 are distributed in an orthogonal projection on the first main side 102 in such a way that the distance between two adjacent discrete second emitter shorts 138 decreases with increasing (lateral) distance from the second amplification gate electrode 145. This variation in the density of the second emitter shorts 138 allows the first thyristor to have a relatively low on-state voltage at high anode currents while the second thyristor can be triggered at relatively low anode currents (i.e., the second thyristor has a high di/dt capability). Wherein the average distance between two adjacent second emitter short-circuits 138 at a certain distance d from the second amplification gate electrode 145 represents the arithmetic average of the distances between all pairs of adjacent second emitter short-circuits 128 in a zone including all positions having distances in the range of d to d + Δ d, where Δ d is constant for the calculation of the average distance at all distances d, for example, Δ d ═ 5 mm. The density of the second emitter short-circuits 138 may continuously increase with increasing distance from the second amplification gate electrode 145, or gradually increase, i.e., there is a first region close to the second amplification gate region 145 where the density of the second emitter short-circuits 138 is relatively low (i.e., the average distance between adjacent second emitter short-circuits 138 is relatively high) and a second region farther from the second amplification gate electrode 145 than the first region (i.e., the second region is separated from the second amplification gate electrode 145 by the first region); in the second region, the density of second emitter shorts 138 is higher compared to the density of second emitter shorts 138 in the first region (i.e. the average distance between adjacent second emitter shorts 138 is lower compared to the average distance in the first region).

The effect of the variation in the density of first emitter shorts 128 and second emitter shorts 138 is best seen in fig. 4. The I-V curves of three different bidirectional thyristor devices are shown. The three different triac devices are identical to each other except for the density and pattern of first emitter shorts 128 and second emitter shorts 138. In all three different triac devices, the pattern of first emitter shorts 128 is the same as the pattern of second emitter shorts 138. A first curve a is measured for a triac device having a constant low density of first emitter shorts 128 and second emitter shorts 138, a second curve B is measured for a triac device having a constant but relatively higher density of first emitter shorts 128 and second emitter shorts 138, and a third curve C is measured for a triac device according to an embodiment in which the density of first emitter shorts 128 and second emitter shorts 138 becomes increasing with increasing distance from first amplifying gate electrode 135 and second amplifying gate electrode 145, respectively. It can be seen that in curve a the triac device is triggered at a relatively low anode current but has a relatively high on-state voltage at a high anode current, whereas according to curve B the triac device is triggered only at a relatively high anode current but has a relatively low on-state voltage at a high anode current. Finally, curve C, measured at a triac with a variation of the density of first and second emitter shorts as described above, is triggered at a relatively low anode current and has a relatively low on-state voltage at a high anode current. The region of the thyristor discussed above allows one to specify a typical current rating of about 2.5 kA. Fig. 4 shows that the application of a dense emitter short-circuit pattern provides a relatively low on-state voltage even under overload conditions (short-circuit operation) well above 2.5 kA.

As shown in fig. 5, in the bidirectional thyristor device 100 according to the embodiment, n is used^-The (spatial) density of deep energy levels (radiation defects) of recombination centers in the doped third semiconductor layer 110 has a J-junction with the third p-n junction along a line extending perpendicular to the first main side 102₃Is closer to the second p-n junction J than to the second p-n junction J₂And has a junction J with the second p-n₂Is closer to the third p-n junction J than to the third p-n junction J₃Of the second local maximum. In FIG. 5, the dotted line P₁The position of the first local maximum of the density of deep levels is shown, and the dashed line P in FIG. 5₂The position of the second local maximum of the density of deep energy levels is shown. On the right side of fig. 5, the density of deep energy levels (i.e. the density of radiation defects referred to as defect concentration in fig. 5) as a function of depth x from the second main side 104 is shown. The first local maximum may, for example, be spaced from the second p-n junction J₂Less than 50 μm and the second local maximum may be, for example, from the third p-n junction J₃Is less than50 μm. The local maximum of the density of deep energy levels used as recombination centers in the third semiconductor layer near the second p-n junction and/or the third p-n junction may improve the turn-off capability of the triac device. With P₁(P₂) P-n junction J from adjacent₂(J₃) At the expense of a higher on-state voltage drop (loss), the improvement in turn-off capability increases. For a given thyristor structure and application (commutation off) conditions, P is present₁(P₂) From adjacent knot J₂(J₃) The optimal distance of (a).

The first local maximum of the density of deep energy levels in the third semiconductor layer 110 may be generated, for example, by irradiation of protons with an appropriate energy, which depends on the material and thickness of the layer through which the protons will pass to reach the junction J with respect to the second p-n junction₂And a third p-n junction J₃Forming a deep level center in the desired location. Deep energy levels may also be generated by irradiation with other particles (e.g., electron irradiation or helium irradiation).

According to the use as n^-The first and second local maxima of the density of deep levels of recombination centers in the doped third semiconductor layer 110, and the excess carrier lifetime has the first and second local minima at the same positions as the first and second local maxima of the density of deep levels. The location of the local minimum of excess carrier lifetime can be measured, for example, by an extended resistance test, which can show the result of doping compensation by acceptor type deep levels formed by radiative defects, with n^-Local deviation of the background doping concentration in the doped third semiconductor layer 110. Measurement results of an extended resistance test for a specific example of a bidirectional thyristor device according to an embodiment are shown in fig. 6a, where the density of deep energy levels is at J distance from the p-n junction₂/J₃Has a local maximum at a distance of about 10 μm and measurement results of an extended resistance test for another specific example of a bidirectional thyristor device according to an embodiment are shown in fig. 6b, wherein the density of deep energy levels is at J distance from the p-n junction₂/J₃With a local maximum at a distance of about 80 μm. Local partThe reduced excess carrier lifetime facilitates turn-off capability for bidirectional thyristor devices of both polarities.

It will be apparent to those skilled in the art that modifications to the embodiments described above are possible without departing from the scope of the invention as defined in the appended claims.

In the bidirectional thyristor device 100 according to an embodiment, the first region is identical to the second region, i.e. there is a perfect overlap between the first region and the second region. However, the triac devices of the present invention may not have a perfect overlap between the first region and the second region. It is sufficient if there is an overlap region between the first region and the second region in an orthogonal projection on a plane parallel to the first main side. In an exemplary embodiment of the bidirectional thyristor device, an overlap region in which the first region overlaps the second region comprises at least 50% of the total wafer area occupied by the semiconductor wafer, when viewed in orthogonal projection on a plane parallel to the first main side of the semiconductor wafer.

In the above embodiments of the triac device, some or all of the first to fourth finger electrode portions 135b, 135c, 145b, 145c may be omitted. Likewise, the first and second amplification gate electrodes 135 and 145 may include additional finger electrode portions.

Also, although the embodiments are described with a first pilot thyristor facilitating the triggering of the first thyristor and with a second control thyristor facilitating the triggering of the second thyristor, the triac device of the present invention need not necessarily include any pilot thyristor for triggering the first thyristor and the second thyristor. This means that the entire first amplification gate electrode 135 and n may be omitted⁺A doped first auxiliary cathode emitter layer 152. In this case, the first main gate electrode will correspond to the first gate electrode recited in the claims. Likewise, the entire second amplification gate electrodes 145 and n may be omitted⁺A doped second auxiliary cathode emitter layer 162. In this case, the second main gate electrode will correspond to the second gate electrode recited in the claims.

In the drawings of the above embodiments, the semiconductor wafer is shown as a circular wafer in fig. 2 and 3. However, the invention is also applicable to semiconductor wafers of other geometries. For example, the semiconductor wafer may also have a rectangular shape or a polygonal shape.

First emitter short 128 is depicted as a p-type semiconductor region. However, they may also be made of another conductive material that forms an ohmic contact with the p-doped second semiconductor layer 108. Likewise, second emitter short 138 is depicted as a p-type semiconductor region. However, they may also be made of another conductive material that forms an ohmic contact with the p-doped fourth semiconductor layer 112.

At n⁺Doped first cathode emitter layer 152 or at n⁺The above embodiments are described without any emitter shorts in the doped second cathode emitter layer 162. However, a penetration n may be provided⁺A first auxiliary emitter short of the doped first cathode emitter layer 152 for connecting the p-type first semiconductor layer 108 with the first ring electrode portion 135 a. Likewise, a penetration n may be formed⁺And a second auxiliary emitter short-circuit portion of the doped second cathode emitter layer 162 for connecting the p-type fourth semiconductor layer 112 with the second ring-shaped electrode portion 145 a.

In the above embodiments of the bidirectional thyristor device, the first semiconductor layer 106 and the fifth semiconductor layer 116 extend to the edge termination region 191. However, a p-anode ring of the second thyristor (i.e. the cathode shorting ring of the first thyristor) in contact with the first main electrode 115 may be formed at the first main side 102 to laterally surround the outer edge of the first semiconductor layer 106. Likewise, a p-anode ring of the first thyristor (i.e., a cathode shorting ring of the second thyristor) in contact with the second main electrode 116 may be formed at the second main side 104 to laterally surround the outer edge of the fifth semiconductor layer 114. Although the presence of the p-anode ring at the cathode side improves the blocking stability, at the same time a larger anode area is provided at the opposite side.

In addition to or instead of the previously described variation in average distance between adjacent first emitter shorts 128, the average lateral dimension of the first emitter shorts 128 may increase with increasing distance from the first amplification gate electrode 135. Likewise, in addition to or instead of the previously described variation in average distance between adjacent second emitter shorts 138, the average lateral dimension of the second emitter shorts 138 may increase with increasing distance from the second amplifying gate electrode 145.

In the above embodiment, the second p-n junction J₂And a third p-n junction J₃Respectively, are plane and parallel to the first main side. However, the second p-n junction J₂And a third p-n junction J₃May for example vary in such a way that the second p-n junction J₂And a third p-n junction J₃The distance between them is smaller in the edge termination region than in the active region of the device.

In the above embodiments, the termination of the junction is formed by a negative slope. However, the termination of the junction may be formed by a positive bevel, a Junction Termination Extension (JTE), a laterally varied doping (VLD) structure, a guard ring, a combination of positive and negative bevels, or another semiconductor structure suitable for the purpose.

It should be noted that the term "comprising" does not exclude other elements or steps and the indefinite article "a" or "an" does not exclude a plurality. Also elements described in association with different embodiments may be combined.

List of reference numerals

100 bidirectional thyristor device

102 first main side

104 second main side

106 n⁺Doped first semiconductor layer

108 p doped second semiconductor layer

110 n^-Doped third semiconductor layer

112 p-doped fourth semiconductor layer

114 n⁺Doped fifth semiconductor layer

115 first main electrode

116 second main electrode

128 first emitter short

135 first amplifying gate electrode

135a first ring electrode portion

135b first finger electrode portion

135c second finger electrode portion

138 second emitter short-circuit

145 second amplifying gate electrode

145a second ring electrode portion

145b third finger electrode portion

145c fourth finger electrode portion

152 n⁺Doped first auxiliary cathode emitter layer

162 n⁺Doped second auxiliary cathode emitter layer

175 first main gate electrode

185 second main gate electrode

J₁First p-n junction

J₂Second p-n junction

J₃Third p-n junction

J₄Fourth p-n junction

P₁First local maximum of density of deep energy level

P₂Second local maximum of density of deep energy level