阅读说明：本技术 宽带隙半导体装置 (Wide band gap semiconductor device ) 是由 中村俊一 于 2018-03-29 设计创作，主要内容包括：本发明涉及的宽带隙半导体装置,包括：第一MOSFET区域(M0),具有第一栅电极10、以及设置在由第二导电型构成的第一阱区20的第一源极区域30；第二MOSFET区域(M1),设置在栅极焊盘100的下方,具有第二栅电极110、以及设置在由第二导电型构成的第二阱区120的第二源极区域130；以及内置二极管区域,与第二栅电极110电气连接,其中,第二MOSFET区域(M1)的第二源极区域120与栅极焊盘100电气连接。(The wide bandgap semiconductor device according to the present invention includes: a first MOSFET region (M0) having a first gate electrode 10 and a first source region 30 provided in a first well region 20 of a second conductivity type; a second MOSFET region (M1) provided below the gate pad 100, and having a second gate electrode 110 and a second source region 130 provided in a second well region 120 of a second conductivity type; and a built-in diode region electrically connected to the second gate electrode 110, wherein the second source region 120 of the second MOSFET region (M1) is electrically connected to the gate pad 100.)

1. A wide bandgap semiconductor device, comprising:

a drift layer made of a wide band gap semiconductor material of a first conductivity type;

a source pad;

a first MOSFET region provided below the source pad, and having a first gate electrode and a first source region provided in a first well region of a second conductivity type;

a gate pad;

a second MOSFET region provided below the gate pad, and having a second gate electrode and a second source region provided in a second well region of a second conductivity type; and

a built-in diode region electrically connected to the second gate electrode,

wherein the second source region of the second MOSFET region is electrically connected to the gate pad.

2. The wide bandgap semiconductor device of claim 1, wherein: further comprising:

and a third MOSFET region having a third gate electrode electrically connected to the gate pad and a third source region disposed in the second well region.

3. The wide bandgap semiconductor device of claim 2, wherein:

the third MOSFET region is a planar MOSFET, and the third source region and the third drain region are disposed in the second well region.

4. The wide bandgap semiconductor device of claim 1, wherein:

further comprising a pad for a diode connected to said second gate electrode,

the built-in diode region is electrically connected to the second gate electrode through the pad for a diode.

5. The wide bandgap semiconductor device of claim 4, wherein:

wherein the diode pad and the gate pad are electrically connected by a resistor.

6. The wide bandgap semiconductor device of claim 4, wherein:

wherein the built-in diode region has: a third upper well region disposed below the pad for the diode and composed of a second conductivity type, and a third lower well region disposed below the third upper well region and composed of a higher dopant concentration than the third upper well region.

7. The wide bandgap semiconductor device of claim 6, wherein:

wherein the pad for the diode is in schottky contact with the third upper well region.

8. The wide bandgap semiconductor device of claim 1, wherein:

wherein a first protection diode region electrically connected to the source pad and the gate pad is disposed in the first well region at least a portion of which is disposed under the gate pad.

9. The wide bandgap semiconductor device of claim 1, wherein:

further comprising a pad for a diode connected to said second gate electrode,

a second protection diode region electrically connected to the diode pad and the gate pad is provided in a second well region at least a portion of which is disposed below the diode pad.

10. The wide bandgap semiconductor device of claim 1, wherein:

further comprising a pad for a diode connected to said second gate electrode,

a second protection diode region electrically connected to the diode pad and the source pad is provided in the first well region at least partially disposed below the diode pad.

11. The wide bandgap semiconductor device of claim 1, wherein:

further comprising a pad for a diode connected to said second gate electrode,

in the second well region at least a part of which is disposed below the pad for a diode, a resistance region having a low concentration first conductivity type region electrically connected to the pad for a diode and the gate pad is disposed.

12. The wide bandgap semiconductor device of claim 1, wherein:

wherein a first connection region electrically connected to the second gate electrode is provided under the gate pad.

13. The wide bandgap semiconductor device of claim 12, wherein:

wherein a built-in diode region electrically connected to the first connection region is provided below the first connection region.

14. The wide bandgap semiconductor device of claim 12, wherein:

wherein, in the second well region located below the gate pad, a resistance region having a low concentration first conductivity type region electrically connected to the first connection region and the gate pad is provided.

15. The wide bandgap semiconductor device of claim 12, wherein:

wherein a second wiring layer electrically connected to the first connection region and the second gate electrode is provided between the source pad and the gate pad in an in-plane direction,

the built-in diode region is electrically connected to the second gate electrode through the second wiring layer and the first connection region,

a second protection diode region electrically connected to the second wiring layer and the source pad is provided in the first well region at least a part of which is disposed below the second wiring layer.

Technical Field

The present invention relates to a wide bandgap semiconductor device, which comprises: a drift layer of a first conductivity type; a well region of a second conductivity type provided on the drift layer; and a source region disposed in the well region.

Background

Conventionally, MOSFETs (metal-oxide semiconductor field effect transistors) have been widely known as wide band gap semiconductors such as SiC (international publication No. 2012/001837). In such a MOSFET in a wide band gap semiconductor of SiC or the like, a Cell (Cell) portion thereof is protected from an excessive electric field applied from the drain side to the gate insulating film. However, such protection typically results in a decrease in Crss. Although it is sometimes desired to reduce Crss in a silicon element, in the case of a wide band gap semiconductor device such as SiC, ron (on resistance) is small even with a high breakdown voltage. Therefore, a high withstand voltage and a low Crss occur once Crss is lowered, resulting in a very high dV/dt generated at the time of Switching (Switching). Although high dV/dt is advantageous in reducing switching loss, surge and noise are generated when dV/dt is too high, and it is necessary to control the dV/dt to an appropriate value according to circuit conditions.

Based on the above, it can be considered to use an Active mirror circuit (Active mirror circuit) or an Active clamp circuit (Active clamp circuit) for adjusting dV/dt, and thus an external MOSFET and a diode are required. In the case of a wide band gap semiconductor such as SiC, although there is an advantage that it can be used at high temperature, when such an external MOSFET is made of a silicon material, it cannot be used at high temperature.

Further, since the SiC or the like wide band gap semiconductor is expensive, if it is necessary to additionally provide a MOSFET made of the SiC or the like wide band gap semiconductor, the manufacturing cost inevitably increases.

In view of the above circumstances, an object of the present invention is to provide a wide bandgap semiconductor device capable of adjusting dV/dt while suppressing an increase in manufacturing cost.

Disclosure of Invention

[ PROCEDURE 1 ]

The wide bandgap semiconductor device according to the present invention includes:

a drift layer made of a wide band gap semiconductor material of a first conductivity type;

a source pad;

a first MOSFET region (M0) provided below the source pad and having a first gate electrode and a first source region provided in a first well region of a second conductivity type;

a gate pad;

a second MOSFET region (M1) provided below the gate pad and having a second gate electrode and a second source region provided in a second well region of a second conductivity type; and

a built-in diode region electrically connected to the second gate electrode,

wherein the second source region of the second MOSFET region (M1) is electrically connected with the gate pad.

[ PROCEDURE 2 ]

In the wide bandgap semiconductor device according to the above [ concept 1 ], further comprising:

a third MOSFET region (M5) having a third gate electrode electrically connected to the gate pad and a third source region disposed in the second well region.

[ PROCEDURE 3 ]

In the wide bandgap semiconductor device according to [ concept 1 ] above,

the third MOSFET region (M5) is a planar MOSFET, and the third source region and the third drain region are provided in the second well region.

[ concept 4 ]

In the wide bandgap semiconductor device according to any one of the above [ concept 1 ] to [ concept 3 ],

further comprising a pad for a diode connected to said second gate electrode,

the built-in diode region is electrically connected to the second gate electrode through the pad for a diode.

[ PROCEDURE 5 ]

In the wide bandgap semiconductor device according to the above [ concept 4 ],

the diode pad and the gate pad are electrically connected to each other through a resistor.

[ concept 6 ]

In the wide bandgap semiconductor device according to any one of the above [ concept 4 ] to [ concept 5 ],

the built-in diode region has: a third upper well region disposed below the pad for the diode and composed of a second conductivity type, and a third lower well region disposed below the third upper well region and composed of a higher dopant concentration than the third upper well region.

[ PROCEDURE 7 ]

In the wide bandgap semiconductor device according to the above [ concept 6 ],

the diode pad is in schottky contact with the third upper well region.

[ concept 8 ]

In the wide bandgap semiconductor device according to any one of the above [ concept 1 ] to [ concept 7 ],

in the first well region at least a portion of which is disposed under the gate pad, a first protection diode region (D6) electrically connected to the source pad and the gate pad is disposed.

[ concept 9 ]

In the wide bandgap semiconductor device according to any one of the above [ concept 1 ] to [ concept 8 ],

further comprising a pad for a diode connected to said second gate electrode,

a second protection diode region (D7) electrically connected to the diode pad and the gate pad is provided in a second well region at least a part of which is provided below the diode pad.

[ PROCEDURE 10 ]

In the wide bandgap semiconductor device according to any one of the above [ concept 1 ] to [ concept 9 ],

further comprising a pad for a diode connected to said second gate electrode,

a second protection diode region (D7) electrically connected to the diode pad and the source pad is provided in the first well region at least partially disposed below the diode pad.

[ concept 11 ]

In the wide bandgap semiconductor device according to any one of the above [ concept 1 ] to [ concept 10 ],

further comprising a pad for a diode connected to said second gate electrode,

in the second well region at least a part of which is disposed below the pad for a diode, a resistance region having a low concentration first conductivity type region electrically connected to the pad for a diode and the gate pad is disposed.

[ PROCEDURE 12 ]

In the wide bandgap semiconductor device according to any one of the above [ concept 1 ] to [ concept 11 ],

a first connection region electrically connected to the second gate electrode is disposed under the gate pad.

[ concept 13 ]

In the wide bandgap semiconductor device according to the above [ concept 12 ],

an embedded diode region electrically connected to the first connection region is provided below the first connection region.

[ PROCEDURE 14 ]

In the wide bandgap semiconductor device according to the above [ concept 12 ] or [ concept 13 ],

in the second well region located below the gate pad, a resistance region having a low concentration first conductivity type region electrically connected to the first connection region and the gate pad is provided.

[ concept 15 ]

In the wide bandgap semiconductor device according to any one of the above [ concept 12 ] to [ concept 14 ],

a second wiring layer electrically connected to the first connection region and the second gate electrode is provided between the source pad and the gate pad in an in-plane direction,

the built-in diode region is electrically connected to the second gate electrode through the second wiring layer and the first connection region,

a second protection diode region (D7) electrically connected to the second wiring layer and the source pad is provided in the first well region at least partially disposed below the second wiring layer.

Effects of the invention

In the present invention, when the second MOSFET region (M1) is provided below the gate pad and the diode region (D2b + D4) electrically connected to the second gate electrode of the second MOSFET region (M1) is provided, a wide bandgap semiconductor device capable of adjusting dV/dt while suppressing an increase in manufacturing cost can be provided.

Drawings

Fig. 1 is a cross-sectional view of a silicon carbide semiconductor device that can be used in a first embodiment of the present invention, showing a cross section at an imaginary line a1 in fig. 11 and 12.

Fig. 2 is a diagram for explaining the function of the layer at the cross section shown in fig. 1.

Fig. 3 is a cross-sectional view of a silicon carbide semiconductor device that can be used in the first embodiment of the present invention, showing a cross section at an imaginary line b1 in fig. 11 and 12.

Fig. 4 is a diagram for explaining the function of the layer at the cross section shown in fig. 3.

Fig. 5 is a cross-sectional view of a silicon carbide semiconductor device that can be used in the first embodiment of the present invention, showing a cross section at an imaginary line c1 in fig. 11 and 14.

Fig. 6 is a diagram for explaining the function of the layer at the cross section shown in fig. 5.

Fig. 7 is a cross-sectional view of a silicon carbide semiconductor device that can be used in the first embodiment of the present invention, showing a cross section at an imaginary line d1 in fig. 11 and 14.

Fig. 8 is a diagram for explaining the function of the layer at the cross section shown in fig. 7.

Fig. 9 is a cross-sectional view of a silicon carbide semiconductor device that can be used in the first embodiment of the present invention, showing a cross section at an imaginary line e1 in fig. 11, 12, and 14.

Fig. 10 is a diagram for explaining the function of the layer at the cross section shown in fig. 9.

Fig. 11 is a schematic plan view of a silicon carbide semiconductor device that can be used in the first embodiment of the present invention.

Fig. 12 is a schematic plan view of another embodiment of a silicon carbide semiconductor device that can be used in the first embodiment of the present invention.

Fig. 13 is a schematic plan view of another embodiment of a silicon carbide semiconductor device that can be used in the first embodiment of the present invention.

Fig. 14 is a schematic plan view of another embodiment of a silicon carbide semiconductor device that can be used in the first embodiment of the present invention, and shows a portion different from fig. 12 and 13.

Fig. 15 is a circuit diagram of a silicon carbide semiconductor device that can be used in the first embodiment of the present invention.

Fig. 16 is a sectional view of a silicon carbide semiconductor device that can be used in a second embodiment of the present invention, showing the section at the phantom line a2 in fig. 20.

Fig. 17 is a diagram for explaining the function of the layer at the cross section shown in fig. 16.

Fig. 18 is a sectional view of a silicon carbide semiconductor device that can be used in a second embodiment of the present invention, showing the section at the phantom line c2 in fig. 21.

Fig. 19 is a diagram for explaining the function of the layer at the cross section shown in fig. 18.

Fig. 20 is a plan view of another embodiment of a silicon carbide semiconductor device that can be used in the second embodiment of the present invention.

Fig. 21 is a plan view of another embodiment of a silicon carbide semiconductor device that can be used in the second embodiment of the present invention, which is different from fig. 20.

Fig. 22 is a circuit diagram of a silicon carbide semiconductor device that can be used in the second embodiment of the present invention.

Fig. 23 is a sectional view of a silicon carbide semiconductor device that can be used in a third embodiment of the present invention, showing the section at the phantom line f3 in fig. 26.

Fig. 24 is a diagram for explaining the function of the layer at the cross section shown in fig. 23.

Fig. 25 is a schematic plan view of a silicon carbide semiconductor device that can be used in the third embodiment of the present invention.

Fig. 26 is a schematic plan view of another embodiment of a silicon carbide semiconductor device that can be used in the third embodiment of the present invention.

Fig. 27 is a circuit diagram of a silicon carbide semiconductor device that can be used in the third embodiment of the present invention.

Fig. 28 is a sectional view of a silicon carbide semiconductor device usable in a third embodiment of the present invention, showing a section at an imaginary line f3 in fig. 26 different from the configuration shown in fig. 25,

fig. 29 is a diagram for explaining the function of the layer at the cross section shown in fig. 28.

Fig. 30 is a cross-sectional view of a silicon carbide semiconductor device that can be used in a fourth embodiment of the present invention, showing the cross-section at phantom line c4 in fig. 39.

Fig. 31 is a diagram for explaining the function of the layer at the cross section shown in fig. 30.

Fig. 32 is a sectional view of a silicon carbide semiconductor device that can be used in a fourth embodiment of the present invention, showing the section at phantom line d4 in fig. 39.

Fig. 33 is a diagram for explaining a layer function at the cross section shown in fig. 32.

Fig. 34 is a sectional view of a silicon carbide semiconductor device that can be used in a fourth embodiment of the present invention, showing the section at phantom line g4 in fig. 39.

Fig. 35 is a diagram for explaining the function of the layer at the cross section shown in fig. 34.

Fig. 36 is a sectional view of a silicon carbide semiconductor device that can be used in a fourth embodiment of the present invention, showing the section at the phantom line e4 in fig. 39.

Fig. 37 is a diagram for explaining a layer function at the cross section shown in fig. 36.

Fig. 38 is a schematic plan view of a silicon carbide semiconductor device that can be used in the fourth embodiment of the present invention.

Fig. 39 is a schematic plan view of another embodiment of a silicon carbide semiconductor device that can be used in the fourth embodiment of the present invention.

Fig. 40 is a circuit diagram of a silicon carbide semiconductor device that can be used in the fourth embodiment of the present invention.

Fig. 41 is a sectional view of a silicon carbide semiconductor device that can be used in a fifth embodiment of the present invention, showing the section at the phantom line c5 in fig. 52.

Fig. 42 is a diagram for explaining a layer function at the cross section shown in fig. 41.

Fig. 43 is a sectional view of a silicon carbide semiconductor device that can be used in a fifth embodiment of the present invention, showing the section at phantom line d5 in fig. 52.

Fig. 44 is a diagram for explaining the function of the layer at the cross section shown in fig. 43.

Fig. 45 is a cross-sectional view of a silicon carbide semiconductor device that can be used in a fifth embodiment of the present invention, showing the cross-section at phantom line g5 in fig. 52.

Fig. 46 is a diagram for explaining the function of the layer at the cross section shown in fig. 45.

Fig. 47 is a cross-sectional view of a silicon carbide semiconductor device that can be used in a fifth embodiment of the present invention, showing a cross section at an imaginary line h5a in fig. 41 and 52.

Fig. 48 is a diagram for explaining the function of the layer at the cross section shown in fig. 47.

Fig. 49 is a cross-sectional view of a silicon carbide semiconductor device that can be used in a fifth embodiment of the present invention, showing the cross-section at the imaginary line h5b in fig. 41 and 52.

Fig. 50 is a diagram for explaining a layer function at the cross section shown in fig. 49.

Fig. 51 is a schematic plan view of a silicon carbide semiconductor device that can be used in a fifth embodiment of the present invention.

Fig. 52 is a plan view of another embodiment of a silicon carbide semiconductor device that can be used in a fifth embodiment of the present invention.

Detailed Description

First embodiment

In this embodiment, a vertical MOSFET will be used as an example for description. In this embodiment, the first conductivity type is described as an n-type and the second conductivity type is described as a p-type, but the present invention is not limited to this embodiment, and the first conductivity type may be a p-type and the second conductivity type may be an n-type. In the present embodiment, silicon carbide is used as the wide band gap semiconductor, but the present invention is not limited to this form, and gallium nitride or the like may be used as the wide band gap semiconductor. In the present embodiment, the vertical direction, which is the thickness direction in fig. 1, is shown as a first direction. A direction orthogonal to the thickness direction (first direction) of fig. 1 is referred to as an "in-plane direction". That is, a plane including the left-right direction (second direction) of fig. 1 and the normal direction of the paper surface is an "in-plane direction".

As shown in fig. 1, the silicon carbide semiconductor device of the present embodiment includes an n-type silicon carbide semiconductor substrate 11, a drift layer 12 formed on a first main surface (upper end surface) of the silicon carbide semiconductor substrate 11 and using an n-type silicon carbide material, a plurality of well regions 20 formed of a p-type material provided on the drift layer 12, and an n-type source region 30 provided in the well regions 20, the well regions 20 may be formed by implanting a p-type dopant into the drift layer 12, for example, the source region 30 may be formed by implanting an n-type dopant into the well regions 20, a drain electrode 19 is provided on a second main surface (lower end surface) of the silicon carbide semiconductor substrate 11, a voltage-resistant structure portion is provided outside a peripheral edge of a region used as a cell, for example, titanium, aluminum, nickel, or the like may be used as the drain electrode 90, and the dopant concentration in the drift layer 12 of the present embodiment is, for example, 1 × 10¹⁴～4×10¹⁶cm^－3The dopant concentration in the silicon carbide semiconductor substrate 11 is, for example, 1 × 10¹⁸～3×10¹⁹cm^－3。

As shown in fig. 1 and 2, the silicon carbide semiconductor device includes: the source pad 1 and the first MOSFET region (M0) are provided below the source pad 1, and include a first gate electrode 10 made of polysilicon or the like and a first source region 30 provided in the first well region 20 made of the second conductivity type. The upper end surface and the side surface of the first gate electrode 10 are surrounded by the interlayer insulating film 65, and the lower end surface of the first gate electrode 10 is provided with a first insulating film 60 made of a gate oxide film or the like (see a virtual line a1 in fig. 11 and 12).

In the first source region 30, a portion connected to the source pad 1 is an ultra-high concentration n-type region (n)⁺⁺)32, and a high concentration n-type region (n)⁺)31 are disposed adjacent to ultra-high concentration n-type region 32. Ultra-high concentration p-type semiconductor region (p)⁺⁺)21 are disposed adjacent to ultra-high concentration n-type region 32. The ultra-high concentration n-type region 32 and the ultra-high concentration p-type semiconductor region 21 are connected to the source pad 1 through a metal layer 40. A first insulating film 60 is provided between the first well region 20 and the interlayer insulating film 65.

A silicon carbide semiconductor device includes: the gate pad 100 and the second MOSFET region (M1) are provided below the gate pad 100, and include a second gate electrode 110 made of polysilicon or the like and a second source region 130 provided in the second well region 120 made of the second conductivity type. The upper end surface and the side surface of the second gate electrode 110 are surrounded by the interlayer insulating film 65, and the lower end surface of the second gate electrode 110 is provided with a first insulating film 60 made of a gate oxide film or the like.

A second source region 130 having: a portion of which is a high concentration n-type region (n) located below the second gate electrode 110⁺)131 and an ultra-high concentration n-type region (n) adjacent to the high concentration n-type region 131⁺⁺)132. In the second well region 120, a region adjacent to the ultra-high concentration n-type region 132 is a low concentration p-type region (p)^-)122, and the region between the high concentration n-type region 131 and the drift layer 12 is a high concentration p-type region (p)⁺)121. Ultra high concentration n-type region (n)⁺⁺) And a low concentration p-type region (p)^-) And is connected to the gate pad 100 through the metal layer 40. The metal layer 40 under the gate pad 100 and the low concentration p-type region (p) of the second well region 120^-) A schottky contact.

The first isolation region 80 formed of an n-type region (n) is provided between the first source region 30 and the second source region 130 in the in-plane direction, thereby dividing the well region and forming the first well region 20 and the second well region 120.

As shown in fig. 3 and 4, the gate pad 100 is connected to the first gate electrode 10 at a location different from the location where the first MOSFET region (M0) exists (see a virtual line b1 in fig. 11 and 12), thereby forming a gate connection region. The gate connection region is formed by contacting the first gate electrode 10 with the gate pad 100 via a gate contact hole provided on the interlayer insulating film 65.

As shown in fig. 5 and 6, a first built-in diode region (D2b + D4) is provided between the gate pad 100 and the source pad 1 in the in-plane direction (see a virtual line c1 in fig. 11 and 14). The first internal diode region (D2b + D4) is connected to the gate pad 100 via a diode pad 200 made of aluminum or the like and an external resistor 400 (see fig. 11).

The first built-in diode region (D2b + D4) has a third well region 210. The third well region 210 has: a third upper well region 211 disposed below the diode pad 200 and composed of a p-type, and a third lower well region 215 disposed below the third upper well region 211 and composed of a higher dopant concentration than the third upper well region 211. The third upper well region 211 is connected to the diode pad 200 through the metal layer 40. The third lower well regions 215 are arranged in stripes below the third upper well regions 211.

As shown in fig. 5 and 6, the third lower well region 215 is configured to surround the periphery of the third upper well region 211. These are divided by providing the second separation region 85 composed of the n-type region (n) between the third lower well region 215 and the second well region 120 in the in-plane direction. As shown in fig. 7 and 8, the second gate electrode 110 is connected to a diode pad 200.

The third upper well region 211 is formed of a low concentration p-type region (p)^-) The metal layer 40 formed and connected to the diode pad 200 makes schottky contact with the third upper well region 211. The third lower well region 215 is composed of a p-type region (p).

As shown in fig. 9 and 10, a third MOSFET region (M5) is provided in the peripheral portion of the gate pad 100 in the in-plane direction (see a virtual line e1 in fig. 11, 12, and 14). A third MOSFET region (M5) having: a third gate electrode 510 electrically connected to the gate pad 100, and a third source region disposed in the second well region 120. The third MOSFET region (M5) is a planar MOSFET, and a third source region and a third drain region are provided within the second well region 120.

Specifically, the method comprises the following steps: a part of which is a pair of high concentration n-type regions (n) located below the third gate electrode 510⁺)531 and a pair of ultra-high concentration n-type regions (n) adjacent to the high concentration n-type region 531⁺⁺)532. A high concentration p-type region (p) is provided between the pair of high concentration n-type regions 531 in the second well region 120⁺)521. The third source region is formed by the high concentration n-type region 531 and the ultrahigh concentration n-type region 532 on one side (the right side in fig. 9 and 10), and the third drain region is formed by the high concentration n-type region 531 and the ultrahigh concentration n-type region 532 on the other side (the left side in fig. 9 and 10). In the embodiment shown in fig. 9 and 10, the third gate electrode 510 and the third source region are connected by the gate pad 100.

In the second well region 120, an ultra-high concentration p-type region (p)⁺⁺)522 are disposed adjacent to the ultra-high concentration n-type region 532 on the second MOSFET region (M1) side. Ultra high concentration n-type region (n)⁺⁺) And ultra-high concentration p-type region (p)⁺⁺) The metal layer 40 is connected to the first wiring layer 580 made of aluminum or the like. The first wiring layer 580 is not in contact with the ultra-high concentration n-type region (n)⁺⁺) And ultra-high concentration p-type region (p)⁺⁺) Any area other than the connection. By providing the first wiring layer 580, an ultra-high concentration n-type region (n) can be formed⁺⁺) And ultra-high concentration p-type region (p)⁺⁺) And (4) short-circuiting.

The gate electrodes such as the first gate electrode 10, the second gate electrode 110, and the third gate electrode 510 may be formed using polysilicon or the like, or may be formed using a CVD method, a photolithography technique, or the like. The interlayer insulating film 65 may be formed of silicon dioxide, or may be formed by a CVD method or the like.

The metal layer 40 provided is made of nickel, titanium, or an alloy containing nickel or titanium.

As shown in fig. 11, a withstand voltage structure 90 such as a guard ring is provided outside the periphery of the source pad 1 so as to surround the entire source pad 1.

The cells of the first MOSFET region (M0) may be substantially rectangular in the in-plane direction (squarell) as shown in fig. 12, or may be stripe-shaped (stripe cell) as shown in fig. 13. The second MOSFET region (M1) may be substantially rectangular in the in-plane direction as shown in fig. 12 and 13, or may be stripe-shaped without being limited thereto. When the second MOSFET region (M1) is substantially rectangular in the in-plane direction, the second well region 120 is connected below the second MOSFET region (M1) as shown in fig. 3 and 4 in order to prevent the potential of the second well region 120 from floating.

In the present embodiment, the ultra-high concentration n-type region (n)⁺⁺) Is, for example, 2 × 10¹⁹～1×10²¹cm^－3High concentration n-type region (n)⁺) Is, for example, 1 × 10¹⁸～2×10¹⁹cm^－3The dopant concentration of the n-type region (n) is, for example, 4 × 10¹⁶～1×10¹⁸cm^－3Low concentration n-type region (n) described later^-) Is, for example, 1 × 10¹⁴～4×10¹⁶cm^－3. Ultra-high concentration p-type semiconductor region (p)⁺⁺) Is, for example, 2 × 10¹⁹～1×10²¹cm^－3High concentration p-type region (p)⁺) Is, for example, 3 × 10¹⁷～1×10¹⁹cm^－3The dopant concentration of the p-type region (p) is, for example, 1 × 10¹⁷～5×10¹⁸cm^－3Is a high concentration p-type region (p)⁺) Lower value of dopant concentration, low concentration p-type region (p)^-) Is, for example, 1 × 10¹⁶～1×10¹⁷cm^－3。

In the present embodiment, when the second MOSFET region (M1) is provided below the gate pad 100 and the first diode-incorporating region (D2b + D4) electrically connected to the second gate electrode 110 of the second MOSFET region (M1) is provided, it is not necessary to additionally provide a MOSFET made of a wide bandgap semiconductor such as SiC, and therefore, it is possible to adjust dV/dt while suppressing an increase in manufacturing cost.

According to this embodiment, the circuit configuration shown in fig. 15 can be achieved, and a mirror circuit using the first MOSFET region (M0) and the second MOSFET region (M1) can also be provided.

In fig. 15, the portions surrounded by the broken lines become the respective well regions. Although the second MOSFET region (Normal on) may be in the normally on state (Normal on) when the second well region 120 of the second MOSFET region (M1) is negatively biased (bias), the third MOSFET region (M5) can be brought into the on state and returned to the zero bias by providing the third MOSFET region (M5) having the second well region 120 shown in fig. 15 before the second MOSFET region is brought into the normally on state by the substrate bias effect.

Second embodiment

Next, a second embodiment of the present invention will be explained.

In the present embodiment, as shown in fig. 16 and 17, a first protection diode region (D6) provided in the first well region 20 is provided between the first MOSFET region (M0) below the source pad 1 and the second MOSFET region (M1) below the gate pad 100 in the in-plane direction (see a phantom line a2 in fig. 20). Further, a second protection diode region (D7) provided in the second well region 120 is provided between the first built-in diode region (D2b + D4) below the diode pad 200 in the in-plane direction and the second MOSFET region (M1) below the gate pad 100 (see a virtual line C2 in fig. 21). Otherwise, the same as the first embodiment applies to all the configurations applied to the first embodiment. The components described in the first embodiment are described with the same reference numerals. The cross sections of the imaginary line b2 in fig. 20, the imaginary line d2 in fig. 21, and the imaginary line e2 can be the same as the cross sections of the imaginary line b1, the imaginary line d1, and the imaginary line e1 in the first embodiment.

As shown in fig. 16 and 17, the first protection diode region (D6) is aligned in the in-plane direction with the ultra-high concentration n-type semiconductor region (n) of the first source region 30⁺⁺)32 are adjacently disposed. A first protection diode region (D6) having: ultra-high concentration p-type semiconductor region (p)⁺⁺)613 and an ultra-high concentration p-type semiconductor region (p) in the in-plane direction⁺⁺) High-concentration n-type semiconductor regions (n) arranged adjacently⁺)611. Ultra-high concentration n-type semiconductor region (n)⁺⁺)612 are disposed adjacent to the high concentration n-type semiconductor region 611 in the in-plane direction. Ultra-high concentration n-type semiconductor region (n)⁺⁺) And is connected to the first gate pad 100 through the metal layer 40.

A metal member such as a pad may not be provided above the junction surface between the ultrahigh-concentration p-type semiconductor region 613 and the high-concentration n-type semiconductor region 611 in the first protection diode region (D6). By adopting such a method, improvement in heat resistance can be expected.

As shown in fig. 18 and 19, the second protection diode region (D7) passes through the low-concentration p-type semiconductor region (p) in the in-plane direction^-)122, and an ultra-high concentration n-type semiconductor region (n) of the second source region 130⁺⁺)132 are adjacently disposed. A second protection diode region (D7) having: ultra-high concentration p-type semiconductor region (p)⁺⁺)621, and a high-concentration n-type semiconductor region (n) provided adjacent to the ultra-high-concentration p-type semiconductor region 621⁺)623. Ultra-high concentration n-type semiconductor region (n)⁺⁺)624 are disposed adjacent to the high concentration n-type semiconductor region 623. The ultra-high concentration n-type semiconductor region 624 is connected to the diode pad 200 through the metal layer 40.

A metal member such as a pad may not be provided above the junction surface between the ultrahigh-concentration p-type semiconductor region 621 and the high-concentration n-type semiconductor region 623 in the second protection diode region (D7). By adopting such a method, improvement in heat resistance can be expected.

Further, the ultra-high concentration p-type semiconductor region 621 of the second protection diode region (D7) shown in fig. 18 is configured not to contact the gate pad 100.

In the second protection diode region (D7), an avalanche current flows through the low concentration p-type semiconductor region 122 adjacent to the ultrahigh concentration p-type semiconductor region 621 of the second protection diode region (D7).

Although the breakdown voltage is reduced by widening the interval of the third lower well region 215 of the first built-in diode region (D2b + D4) as shown in fig. 18 and 19, it is advantageous to prevent the occurrence of these problems because a large amount of avalanche energy flows through the first built-in diode region (D2b + D4) and the resistance portion 400(R3), and an overcurrent or an overvoltage may occur in the gate driver circuit of the semiconductor device. For the same reason, the gate of the first MOSFET region (M0) may be overvoltage, but this overvoltage is also advantageously prevented. In this regard, in the present embodiment, since the first protection diode region (D6) is provided, it is possible to prevent an overvoltage or the like in the gate electrode of the first MOSFET region (M0).

Further, it is preferable that the gate of the second MOSFET region (M1) is also protected by the value of the resistor portion 400 shown as R3 in fig. 22 and the ratio of the gate input capacity Ciss of the second MOSFET region (M1) to the junction capacity Cj of the third lower well region 215 of the first diode-incorporated region (D2b + D4). In this regard, by providing the second protection diode region (D7) according to this embodiment, the gate of the second MOSFET region (M1) can be protected. Although fig. 22 shows the second protection diode region (D7) disposed in the second well region 120, the second protection diode region (D7) may be disposed in the first well region 20 with the anode as the source potential.

Third embodiment

Next, a third embodiment of the present invention will be explained.

In each of the above embodiments, the resistor 400 is provided. In the present embodiment, instead of the resistor 400 or in addition to the resistor 400, a first internal resistor region (R3a) is provided between the first internal diode region (D2b + D4) and the first MOSFET region (M0) in the in-plane direction (see a virtual line f3 in fig. 25 and 26). In the present embodiment, all the configurations adopted in the above-described embodiments can be adopted. The components described in the above embodiments will be described with the same reference numerals. In fig. 25, the cross sections of the imaginary line a3, the imaginary line b3, the imaginary line c3, the imaginary line d3, and the imaginary line e3 may be the same as the cross sections of the imaginary line a1, the imaginary line b1, the imaginary line c1, the imaginary line d1, and the imaginary line e1 in the first embodiment, or the cross sections of the imaginary line a2, the imaginary line b2, the imaginary line c2, the imaginary line d2, and the imaginary line e2 in the second embodiment.

As shown in fig. 23, the first internal resistance region (R3a) has a low concentration n-type region (n) disposed in the second well region 120^-)655. Ultra high concentration n-type region (n)⁺⁺)656 is disposed adjacent to low-concentration n-type region 655 in the in-plane direction and is connected to diode pad 200 through metal layer 40. N-type region (n)653 is provided in a direction opposite to the in-plane direction of ultra-high concentration n-type region 656 with respect to low concentration n-type region 655. High concentration n-type region (n)⁺)652 is disposed adjacent to n-type region 653 in the in-plane direction, and is an ultra-high concentration n-type region (n)⁺⁺)651 is disposed adjacent to the high concentration n-type region 652 in the in-plane direction and is connected to the gate pad 100 through the metal layer 40.

A fourth gate electrode 660 is provided over the n-type region 653 through the first insulating film 60. A gate pad 100 is disposed above the fourth gate electrode 660, and the fourth gate electrode 660 is connected to the gate pad 100. The thickness of n-type region 653 is thinner than the thicknesses of ultra-high concentration n-type region 656, low concentration n-type region 655, high concentration n-type region 652, and ultra-high concentration n-type region 651.

The resistance of the first internal resistance region (R3a) is actually realized by the low concentration n-type region 655 which is the ldd (light Doped drain) of the planar MOSFET (M3). That is, the magnitude of the resistance is adjusted by the length of low-concentration n-type region 655, and the length of low-concentration n-type region 655 in fig. 23 is longer than the lengths of ultra-high-concentration n-type region 656, low-concentration n-type region 655, high-concentration n-type region 652, and ultra-high-concentration n-type region 651.

In the embodiment shown in fig. 23 and 24, a planar MOSFET (M3) in a normally on state is formed, and the fourth gate electrode 660 and the ultra high concentration n-type region 651 as a source region are short-circuited by the gate pad 100.

When the resistor 400 is externally arranged as shown in fig. 11, the resistance increases with the temperature increase, and dV/dt is reduced. At this time, the switching loss further increases to further cause a temperature rise. Further, by providing the first internal resistance region (R3a) and the planar MOSFET (M3) as in this embodiment mode, the temperature characteristics can be improved. In particular, when silicon carbide is used as a material, since the interface characteristics are poor, the resistance value of the MOS channel has strong negative temperature characteristics due to the influence of the interface characteristics, and therefore, it is advantageous to improve the temperature characteristics as compared with the case of externally disposing the resistor portion 400. Although fig. 27 is a circuit diagram in the present embodiment, the parasitic capacitance C3 in the first internal resistance region (R3a) is also shown.

As shown in fig. 28 and 29, low-concentration n-type region 657 may be provided instead of ultra-high-concentration n-type region 656. The low-concentration n-type region 657 and the low-concentration n-type region 655 may be the same region having the same concentration or may be regions having different concentrations. When the low-concentration n-type region 657 is provided, the low-concentration n-type region 657 makes schottky contact with the diode pad 200 via the metal layer 40, and at this time, it is not necessary to provide the D2b of the first built-in diode region (D2b + D4) on the D4. Therefore, as shown in fig. 28 and 29, the third upper well region 211 has the same planar shape as the third lower well region 215, and the diode pad 200 makes schottky contact with the drift layer 12. At this time, the concentration of the third upper well regions 211 may be the same as that of the third lower well regions 215, or may be a higher high concentration. In the embodiment shown in fig. 28 and 29, D2b of the first diode built-in region (D2b + D4) is formed between the pad 200 for a diode and the low-concentration n-type region 657.

Fourth embodiment

Next, a fourth embodiment of the present invention will be explained.

In the present embodiment, instead of the resistor section 400 or outside the resistor section 400, or instead of the first internal resistor region (R3a) or outside the first internal resistor region (R3a), a second internal resistor region (R3b) is provided between the first internal diode region (D4) below the diode pad 200 and the second MOSFET region (M1) below the gate pad 100 in the in-plane direction (see imaginary line c4 and imaginary line D4 in fig. 38 and 39). In the present embodiment, all the configurations adopted in the above embodiments can be adopted. The components described in the above embodiments will be described with the same reference numerals. The cross section of the imaginary line a4 and the imaginary line b4 in fig. 38 can adopt the same form as that of the first embodiment or the second embodiment.

As shown in fig. 30 and 31, the second internal resistance region (R3b) has a low-concentration n-type region (n) provided in the second well region 120^-)705. Ultra high concentration n-type region (n)⁺⁺)706 is disposed adjacent to the low concentration n-type region 705 in the in-plane direction and is connected to the pad for diode 200 through the metal layer 40. In addition, a low-concentration p-type region (p-type region) is provided in a direction opposite to the in-plane direction of low-concentration n-type region 705 and ultrahigh-concentration n-type region 706^-)710. And, a high concentration n-type region (n)⁺)702 are disposed adjacent to the low concentration p-type region 710 in the in-plane direction, and an ultra-high concentration n-type region (n)⁺⁺)701 is disposed adjacent to the high concentration n-type region 702 in the in-plane direction and is connected to the gate pad 100 through the metal layer 40.

Low-concentration n-type region 705 is provided continuously in a predetermined direction of the in-plane direction. As an example, as shown in fig. 39, low-concentration n-type region 705 extends in the vertical direction on the sheet of fig. 39. In this case, ultra-high concentration n-type region 706 and low concentration p-type region 710 adjacent to second internal resistance region (R3b) in the in-plane direction are also provided continuously in the predetermined direction.

As shown in fig. 30 to 33, the second gate electrode 110 is provided above the low concentration p-type region 710 through the first insulating film 60. A diode pad 200 is disposed above the second gate electrode 110, and the second gate electrode 110 is connected to the diode pad 200. The thickness of low concentration p-type region 710 is thinner than the thickness of ultra high concentration n-type region 706, low concentration n-type region 705, high concentration n-type region 702, and ultra high concentration n-type region 701.

The planar MOSFET (M3a) of the present embodiment is not in the normally-on state of the third embodiment, but in the normally-off state. The Vth of the planar MOSFET (M3a) of the present embodiment can be a lower value than the Vth of the second MOSFET region (M1). In this manner, D2b of the first built-in diode region may not be provided. At this time, as shown in fig. 30 to 33, the third upper well region 211 is formed in the same planar shape as the third lower well region 215, for example, in a stripe shape extending in the in-plane direction. In addition, the concentration of the third upper well region 211 may be the same as or higher than that of the third lower well region 215. By adopting the mode of D2b without the first built-in diode region, D4 can be made to be high withstand voltage sbd (jbs). By adopting such a configuration, a soft (soft) waveform can be obtained before the avalanche. When the whole is made on, since the planar MOSFET (M3a) is off, Vth of the second MOSFET region (M1) can be made low.

As shown in fig. 34 and 35, an ultra-high concentration n-type region (n-type region) connected to diode pad 200 via metal layer 40 is provided between first built-in diode region (D4) below diode pad 200 and first MOSFET region (M0) below source pad 1⁺⁺)724, and a high-concentration n-type region (n-type region) adjacent to the ultrahigh-concentration n-type region 724 in the in-plane direction⁺)723 in the high concentration n-type region 723 and the ultra-high concentration n-type region (n 0) of the first MOSFET region (M0)⁺⁺)32 between them, an ultra-high concentration p-type region (p) is provided⁺⁺)721 (see phantom line g4 in fig. 38 and 39). The second protection diode region (D7) is formed by the high concentration n-type region 723 and the ultra high concentration p-type region 721. The ultra-high concentration p-type region 721 and the ultra-high concentration n-type region 32 of the first MOSFET region (M0) are connected to the source pad 1 through the metal layer 40.

According to the structure, the anode of the second protection diode region (D7) is connected to the source of the first MOSFET region (M0) as shown in fig. 40. In this way, dV/dt at the time of turn-off can be assigned in accordance with the Cj of the first protection diode region (D6) (and/or Ciss of the second MOSFET region (M1) and MOSFET (M3 a)) and the Cj of the second protection diode region (D7), and only the first protection diode region (D6) can be made to flow through the second internal resistance region (R3b) and the planar MOSFET (M3 a). Therefore, even if the area of the first internal diode region (D4) is increased, the required effective Crss can be achieved. Further, the energy at the time of the occurrence of the excessive avalanche in the first built-in diode region (D4) can be absorbed by the first built-in diode region (D4) and the second protection diode region (D7), and the overcurrent and overvoltage on the gate driver circuit side can be prevented.

The cross section on the imaginary line e4 in fig. 38 may be the same as in the first embodiment, or may be the same as in fig. 36 and 37. In fig. 36 and 37, the high concentration p-type region (p) in the first embodiment is not used⁺)121 and a high concentration p-type region (p)⁺)521 (see fig. 9 and 10). This is the low Vth of the second MOSFET region (M1) described above, and therefore, the Vth of the third MOSFET region (M5) is also low.

Fifth embodiment

Next, a fifth embodiment of the present invention will be explained.

In the present embodiment, as shown in fig. 41 to 44, a third internal resistance region (R3c) and a second built-in diode region (D4a) are provided below the gate pad 100 (see a virtual line c5 and a virtual line D5 in fig. 51 and 52). As an example, as shown in fig. 51, a second built-in diode region (D4a) is provided below the gate pad 100, a pair of second MOSFET regions (M1) is provided on both sides (left and right in fig. 51) of the second built-in diode region (D4a) in the in-plane direction, and a pair of third internal resistance regions (R3c) is provided between the second built-in diode region (D4a) and the second MOSFET region (M1) in the in-plane direction. An n-type region (n)85a for separating the second well region 120 is provided between the second built-in diode region (D4a) and the third internal resistance region (R3c) in the in-plane direction. This embodiment can also adopt all the configurations adopted in the above embodiments. The components described in the above embodiments will be described with the same reference numerals.

As shown in fig. 41 and 42, the second built-in diode region (D4a) of the present embodiment includes a third well region 830. The third well region 830 has a third lower well region 825 and a third upper well region 821 disposed over the third lower well region 825. The third upper well 821 is stripe shaped as in the fourth embodiment. Further, a first connection region 831 formed of polysilicon or the like is provided above the third upper well region 821. At this time, the third upper well region 821 and the drift layer 12 make schottky contact with the first portion 831 of the first connection region.

As described above, the third internal resistance region (R3c) is provided between the second built-in diode region (D4a) and the in-plane direction of the second MOSFET region (M1). As shown in fig. 41 and 42, the third internal resistance region (R3c) has a low-concentration n-type region (n) provided in the second well region 120^-)805. The n-type region (n)806 is provided adjacent to the low concentration n-type region 805 on the second built-in diode region (D4a) side in the in-plane direction. In addition, a low-concentration p-type region (p-type region) is provided in a direction opposite to the in-plane direction of the n-type region 806 with respect to the low-concentration n-type region 805^-)810. High concentration n-type region (n)⁺)802 are disposed adjacent to the low concentration p-type region 810 in the in-plane direction, and the ultra-high concentration n-type region (n)⁺⁺)801 are disposed adjacent to the high concentration n-type region 802 in the in-plane direction. The upper end surface of the n-type region 806 is provided with a second portion 832 of the first connection region made of polysilicon or the like.

As shown in fig. 45 and 46, an ultra-high concentration n-type region (n 0) is provided between the second built-in diode region (D4a) and the first MOSFET region (M0)⁺⁺)844 and a high concentration n-type region (n) adjacent to the ultrahigh concentration n-type region 844 in the in-plane direction⁺)843 and a high concentration n-type region (n)⁺)843 adjacent ultra-high concentration p-type region (p)⁺⁺)841 (see phantom line g5 in fig. 51 and 52). Then, a second protection diode region (D7) is formed by the high concentration n-type region 843 and the ultrahigh concentration p-type region 841. Ultra-high concentration p-type region (p)⁺⁺)841 and the ultra-high concentration n-type region (n) of the first MOSFET region (M0)⁺⁺)32 adjacent to the first MOSFET region and an ultra-high concentration p-type region 841M0) is connected to source pad 1 through metal layer 40.

The ultra-high concentration n-type region 844 of the second protection diode region (D7) is connected to the second wiring layer 850 via the metal layer 40. A second wiring layer 850 is disposed above the first portion 831 and the second portion 832 of the first connection region disposed above the third upper well region 821, and the second wiring layer 850 is connected to the first portion 831 and the second portion 832 of the first connection region. The first portion 831 and the second portion 832 of the first connection region have peripheral portions formed to overlap the first insulating film 60 made of a gate oxide film or the like to form a step. Below the second wiring layer 850, an n-type region (n)85a is provided for separating the third well region 830 where the second built-in diode region (D4a) is provided from the first well region 20.

Note that, as shown in fig. 47 and 48 for the cross section along the imaginary line h5a in fig. 41, and as shown in fig. 49 and 50 for the cross section along the imaginary line h5b in fig. 41, the first portion 831 and the second portion 832 of the first connection region and the second gate electrode 110 are electrically connected to each other by the second wiring layer 850, and thus the diode region D4a is electrically connected to the second gate electrode 110 by the second wiring layer 850 and the first connection region 831.

The description of the embodiments and the drawings are merely examples for explaining the invention described in the scope of application, and the invention described in the scope of application is not limited to the description of the embodiments and the drawings. The description of the first claim is merely an example, and the description of the claims can be appropriately modified based on the description of the specification, the drawings, and the like.

Description of the symbols

1 source electrode welding pad

10 first gate electrode

11 silicon carbide semiconductor substrate (Wide band gap semiconductor substrate)

12 drift layer

20 first well region

30 first source region

100 gate pad

110 second gate electrode

120 second well region

130 second source region

Pad for 200 diode

211 third upper well region

215 third lower well region

400 resistance part

510 third gate electrode

D2 diode region

D4 diode region

D6 first protection diode region

D7 second protection diode region

M0 first MOSFET region

M1 second MOSFET region

M5 third MOSFET region