阅读说明：本技术 薄膜晶体管及其制造方法、栅极驱动电路、平板显示器 (Thin film transistor, manufacturing method thereof, gate drive circuit and flat panel display ) 是由 陈丹 金志河 黄斌 于 2018-01-30 设计创作，主要内容包括：一种薄膜晶体管及其制造方法、栅极驱动电路、平板显示器,该薄膜晶体管包括基底(11)；设置于该基底(11)上的源极层(12)和漏极层(14)二者之一；设置于该源极层(12)和漏极层(14)二者之一上的绝缘分隔层(13)；设置于该绝缘分隔层(13)上的源极层(12)和漏极层(14)二者之另一；覆盖于该源极层(12)和漏极层(14)二者之一、该绝缘分隔层(13)以及该源极层(12)和漏极层(14)二者之另一上,并将该源极层(12)和漏极层(14)二者之一与该源极层(12)和漏极层(14)二者之另一导电连接的有源层(15)；设置于该有源层(15)上的栅极绝缘层(16)；以及设置在该栅极绝缘层(16)上的栅极层(17)。有益效果为：源极层和漏极层呈垂直布置,能够有效地降低沟道长度,从而降低薄膜晶体管的尺寸。(A thin film transistor and its manufacturing method, gate drive circuit, flat panel display, the thin film transistor includes the base (11); one of a source layer (12) and a drain layer (14) disposed on the substrate (11); an insulating separation layer (13) provided on one of the source layer (12) and the drain layer (14); the other of the source layer (12) and the drain layer (14) provided on the insulating separation layer (13); an active layer (15) covering one of the source layer (12) and the drain layer (14), the insulating spacer layer (13), and the other of the source layer (12) and the drain layer (14), and electrically connecting one of the source layer (12) and the drain layer (14) to the other of the source layer (12) and the drain layer (14); a gate insulating layer (16) disposed on the active layer (15); and a gate electrode layer (17) provided on the gate insulating layer (16). The beneficial effects are that: the source electrode layer and the drain electrode layer are vertically arranged, so that the channel length can be effectively reduced, and the size of the thin film transistor is reduced.)

A thin film transistor, comprising:

a substrate;

one of a source layer and a drain layer disposed on the substrate;

an insulating spacer layer disposed on one of the source layer and the drain layer;

the other of the source layer and the drain layer is disposed on the isolation separation layer;

an active layer covering one of the source layer and the drain layer, the isolation separation layer, and the other of the source layer and the drain layer, and electrically connecting the one of the source layer and the drain layer to the other of the source layer and the drain layer;

a gate insulating layer disposed on the active layer; and

and a gate electrode layer disposed on the gate insulating layer.

The thin film transistor of claim 1 further comprising a dividing groove extending from an outer surface of the gate layer toward the substrate to the other of the source layer and the drain layer to form two thin film transistor cells sharing the source and drain electrodes.

The thin film transistor of claim 1, further comprising a dividing groove extending from an outer surface of the gate layer toward the substrate to the insulating spacer layer, forming two thin film transistor cells sharing a source or a drain.

The thin film transistor of claim 1, further comprising a dividing groove extending from an outer surface of the gate layer toward the substrate to the substrate, forming two independent thin film transistor units.

The thin film transistor according to any one of claims 1 to 4, wherein the thickness of the insulating separator layer is 1 to 1.5 μm.

A gate driver circuit comprising the thin film transistor according to any one of claims 1 to 5.

A gate driver circuit as claimed in claim 6, wherein the gate driver circuit is a two-stage gate driver circuit.

A flat panel display comprising the gate driver circuit of claim 6 or 7.

The flat panel display of claim 8, wherein the flat panel display is a flexible display.

A method for manufacturing a thin film transistor includes the steps of:

providing a substrate;

forming one of a source layer and a drain layer on a substrate;

forming an insulating separation layer on one of the source layer and the drain layer;

forming the other of the source layer and the drain layer on the isolation separation layer;

an active layer covering one of the source layer and the drain layer, the insulating separation layer, and the other of the source layer and the drain layer, the active layer electrically connecting one of the source layer and the drain layer and the other of the source layer and the drain layer;

forming a gate insulating layer on the active layer;

a gate electrode layer is formed on the gate insulating layer.

The method for manufacturing a thin film transistor according to claim 10, further comprising the step of: forming a dividing groove extending from the outer surface of the gate layer toward the substrate to the other of the source layer and the drain layer.

The method for manufacturing a thin film transistor according to claim 10, further comprising the step of: forming a dividing groove extending from the outer surface of the gate electrode layer toward the substrate direction to the insulating separation layer.

The method for manufacturing a thin film transistor according to claim 10, further comprising the step of: forming a dividing groove extending from the outer surface of the gate layer to the substrate in the direction of the substrate.

Technical Field

The present invention relates to a display, and more particularly, to a thin film transistor, a method of manufacturing the same, a gate driving circuit, and a flat panel display.

Background

Fig. 11 is a schematic structural diagram of a thin film transistor 40 in the related art, and as shown in the figure, the thin film transistor 40 can be used in a Gate Driver on Array (GOA) of a liquid crystal display, and includes a substrate 41, a Gate electrode layer 42 disposed on the substrate 41, a Gate insulating layer 43 disposed on the Gate electrode layer 42, an active layer 44 disposed on the Gate insulating layer 43, an interlayer insulating layer 45 disposed on the active layer 44, and source and drain electrodes 46 and 47 disposed on the interlayer insulating layer 45 at intervals, wherein the source and drain electrodes 46 and 47 are respectively communicated with the active layer 44.

FIG. 12 is a circuit diagram showing a gate driver circuit using the thin film transistor, which is composed of four thin film transistors M1-M4 and a capacitor. In some cases, the number of tfts needs to be increased for the lifetime of the gate driving circuit, and the increased number of tfts increases the width of the gate driving circuit, and accordingly, the edge size of the display device is increased.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

FIG. 1 is a schematic diagram of a longitudinal cross-sectional structure of a thin film transistor according to a first embodiment of the present invention;

FIG. 2 is a schematic diagram of a longitudinal cross-sectional structure of a thin film transistor according to a second embodiment of the present invention;

FIG. 3 is a schematic diagram of a vertical cross-sectional structure of a TFT in a third embodiment of the present invention;

fig. 4 is a circuit diagram of the thin film transistor shown in fig. 3;

FIG. 5 is a schematic diagram of a vertical cross-section of the thin film transistor shown in FIG. 3 when bent;

FIG. 6 is a schematic diagram of a longitudinal cross-sectional structure of a TFT in a fourth embodiment of the present invention;

fig. 7 is a circuit diagram of the thin film transistor shown in fig. 6;

FIG. 8 is a schematic diagram showing a longitudinal cross-sectional structure of a TFT in a fifth embodiment of the present invention;

fig. 9 is a circuit diagram of the thin film transistor shown in fig. 8;

fig. 10 is a circuit diagram of a gate driving circuit with the thin film transistor shown in fig. 8;

fig. 11 is a schematic longitudinal sectional structure of a thin film transistor in the related art;

fig. 12 is a circuit diagram of a gate driving circuit with the thin film transistor shown in fig. 11 in the related art.