Two-dimensional material superlattice device and manufacturing method thereof
阅读说明：本技术 一种二维材料超晶格器件及制作方法 (Two-dimensional material superlattice device and manufacturing method thereof ) 是由 卢年端 姜文峰 李泠 耿玓 王嘉玮 李蒙蒙 刘明 于 2020-05-19 设计创作，主要内容包括：本发明涉及半导体器件技术领域,尤其涉及一种二维材料超晶格器件及制作方法,该方法包括：形成绝缘层衬底；在所述绝缘层衬底上开设阵列槽；形成二维材料异质结,所述二维材料异质结包括由下至上的第一二维材料层、第二二维材料层以及第三二维材料层；将所述二维材料异质结转移至所述绝缘层衬底的所述阵列槽上,阵列槽产生的电势能够影响二维材料异质结的能带特性,而且,将器件的阵列槽与二维材料异质结的制作分开进行,避免在衬底上直接制作二维材料异质结产生的杂质,进而保障电子迁移率,提高器件性能。(The invention relates to the technical field of semiconductor devices, in particular to a two-dimensional material superlattice device and a manufacturing method thereof, wherein the method comprises the following steps: forming an insulating layer substrate; forming an array groove on the insulating layer substrate; forming a two-dimensional material heterojunction, wherein the two-dimensional material heterojunction comprises a first two-dimensional material layer, a second two-dimensional material layer and a third two-dimensional material layer from bottom to top; and the two-dimensional material heterojunction is transferred to the array groove of the insulating layer substrate, the potential generated by the array groove can influence the energy band characteristic of the two-dimensional material heterojunction, and the array groove of the device and the manufacture of the two-dimensional material heterojunction are separately carried out, so that the impurities generated by directly manufacturing the two-dimensional material heterojunction on the substrate are avoided, the electron mobility is ensured, and the device performance is improved.)
1. A method for fabricating a two-dimensional superlattice device, comprising:
forming an insulating layer substrate;
forming an array groove on the insulating layer substrate;
forming a two-dimensional material heterojunction, wherein the two-dimensional material heterojunction comprises a first two-dimensional material layer, a second two-dimensional material layer and a third two-dimensional material layer from bottom to top;
transferring the two-dimensional material heterojunction onto the array trench of the insulating layer substrate.
2. The method of claim 1, wherein the forming an insulating layer substrate comprises:
providing a Si substrate;
forming SiO on the Si substrate2An insulating layer.
3. The method of claim 1, wherein the area of the region in which the array of trenches is located is greater than or equal to the area of the bottom surface of the two-dimensional material heterojunction.
4. The method of claim 1, further comprising, after transferring the two-dimensional material heterojunction onto the array of trenches of the insulating layer substrate:
etching the edge area of the two-dimensional material heterojunction to expose the edge of the second two-dimensional material layer of the two-dimensional material heterojunction;
forming a source electrode and a drain electrode on the edges of two opposite sides of the second two-dimensional material layer respectively;
and forming a gate electrode on the top surface of the two-dimensional material heterojunction.
5. A two-dimensional material superlattice device, comprising:
the array substrate comprises an insulating layer substrate, wherein an array groove is formed in the insulating layer substrate;
the two-dimensional material heterojunction is located on the array groove and comprises a first two-dimensional material layer, a second two-dimensional material layer and a third two-dimensional material layer from bottom to top.
6. A two-dimensional material superlattice device as recited in claim 5 further comprising:
the source electrode and the drain electrode are respectively positioned on two sides of the two-dimensional material heterojunction;
and the gate electrode is positioned on the top surface of the two-dimensional material heterojunction.
7. A two-dimensional material superlattice device as recited in claim 5 wherein said insulating layer substrate comprises:
a Si substrate;
SiO on the Si substrate2An insulating layer.
8. A two-dimensional material superlattice device as claimed in claim 5 wherein said array of trenches are located in a region having an area greater than or equal to an area of a bottom surface of said two-dimensional material heterojunction.
9. A two-dimensional material superlattice device as recited in claim 5 wherein said SiO2The thickness of the insulating layer is 100 nm-500 nm, and the array groove is positioned in SiO2On the insulating layer, of each of the array of trenchesThe depth is 30 nm-80 nm.
10. The two-dimensional material superlattice device according to claim 5, wherein said first two-dimensional material layer and said third two-dimensional material layer are of the same material and are both boron nitride layers;
the second two-dimensional material layer is any one of the following materials:
graphene, molybdenum disulfide and black phosphorus.
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a two-dimensional material superlattice device and a manufacturing method thereof.
Background
In the manufacturing process of the conventional superlattice device, impurities are easily generated when a heterojunction is formed, and the existence of the impurities can influence the mobility and further influence the performance of the device.
Therefore, how to improve the mobility of the superlattice device is a technical problem to be solved urgently at present.
Disclosure of Invention
In view of the above, the present invention has been developed to provide a two-dimensional material superlattice device and method of fabrication that overcome, or at least partially solve, the above-mentioned problems.
In one aspect, the invention provides a method for manufacturing a two-dimensional material superlattice device, comprising the following steps:
forming an insulating layer substrate;
forming an array groove on the insulating layer substrate;
forming a two-dimensional material heterojunction, wherein the two-dimensional material heterojunction comprises a first two-dimensional material layer, a second two-dimensional material layer and a third two-dimensional material layer from bottom to top;
transferring the two-dimensional material heterojunction onto the array trench of the insulating layer substrate.
Further, the forming an insulating layer substrate includes:
providing a Si substrate;
forming SiO on the Si substrate2An insulating layer.
Further, the area of the area where the array groove is located is larger than or equal to the area of the bottom surface of the two-dimensional material heterojunction.
Further, after transferring the two-dimensional material heterojunction onto the array of trenches of the insulating layer substrate, further comprising:
etching the edge area of the two-dimensional material heterojunction to expose the edge of the second two-dimensional material layer of the two-dimensional material heterojunction;
forming a source electrode and a drain electrode on the edges of two opposite sides of the second two-dimensional material layer respectively;
and forming a gate electrode on the top surface of the two-dimensional material heterojunction.
In another aspect, the present invention also provides a two-dimensional material superlattice device, comprising:
the array substrate comprises an insulating layer substrate, wherein an array groove is formed in the insulating layer substrate;
the two-dimensional material heterojunction is located on the array groove and comprises a first two-dimensional material layer, a second two-dimensional material layer and a third two-dimensional material layer from bottom to top.
Further, still include:
the source electrode and the drain electrode are respectively positioned on two sides of the two-dimensional material heterojunction;
and the gate electrode is positioned on the top surface of the two-dimensional material heterojunction.
Further, the insulating layer substrate includes:
a Si substrate;
SiO on the Si substrate2An insulating layer.
Further, the area of the area where the array groove is located is larger than or equal to the area of the bottom surface of the two-dimensional material heterojunction.
Further, the SiO2The thickness of the insulating layer is 100 nm-500 nm, and the array groove is positioned in SiO2And on the insulating layer, the depth of each groove in the array grooves is 30 nm-80 nm.
Further, the first two-dimensional material layer and the third two-dimensional material layer are made of the same material and are both boron nitride layers;
the second two-dimensional material layer is any one of the following materials:
graphene, molybdenum disulfide and black phosphorus.
One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:
the invention provides a manufacturing method of a two-dimensional material superlattice device, which comprises the following steps: forming an insulating layer substrate, and forming an array groove on the insulating layer substrate; forming a two-dimensional material heterojunction, wherein the two-dimensional material heterojunction comprises a first two-dimensional material layer, a second two-dimensional material layer and a third two-dimensional material layer from bottom to top; the two-dimensional material heterojunction is transferred to the array groove of the insulating layer substrate, the potential generated by the array groove can influence the energy band characteristic of the two-dimensional material heterojunction, and the array groove of the device and the manufacture of the two-dimensional material heterojunction are separately carried out, so that the impurities generated by directly manufacturing the two-dimensional material heterojunction on the substrate are avoided, the electron mobility is further ensured, and the device performance is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a flow chart illustrating the steps of a method of fabricating a two-dimensional superlattice device in accordance with an embodiment of the invention;
FIG. 2 shows a schematic view of forming an insulating layer substrate in an embodiment of the invention;
FIG. 3 shows a schematic diagram of the formation of array trenches in an embodiment of the present invention;
FIG. 4 shows a schematic diagram of forming a two-dimensional material heterojunction in an embodiment of the invention;
FIG. 5 shows a schematic representation of a two-dimensional material heterojunction transferred onto an insulating layer substrate in an embodiment of the invention;
FIG. 6 shows a schematic diagram of etching the two-dimensional material heterojunction edge in an embodiment of the invention;
FIG. 7 shows a schematic representation of the two-dimensional material heterojunction after edge etching in an embodiment of the invention;
fig. 8 shows a schematic diagram after forming a source electrode, a gate electrode, and a drain electrode in the embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.