阅读说明：本技术 堆叠状的高截止的iii-v族功率半导体二极管 (Stacked high cut-off group III-V power semiconductor diode ) 是由 V·杜德克 于 2020-03-03 设计创作，主要内容包括：一种堆叠状的高截止的III-V族功率半导体二极管,具有p<Sup>+</Sup>或n<Sup>+</Sup>衬底层、p<Sup>-</Sup>层、具有10μm-150μm的层厚度的n<Sup>-</Sup>区域、n<Sup>+</Sup>或p<Sup>+</Sup>层,其中,所有层包括GaAs化合物,还具有第一金属接通层、第二金属接通层和具有至少一个晶种开口的硬掩模层,其中,所述硬掩模层材料锁合地与所述衬底层或材料锁合地与所述p<Sup>-</Sup>层连接,n<Sup>-</Sup>区域在所述晶种开口内延伸,并且延伸到所述硬掩模层的所述上侧的与所述晶种开口邻接的边缘区域的上方,并且n<Sup>-</Sup>区域在所述晶种开口内与所述p<Sup>-</Sup>层或所述n<Sup>+</Sup>层连接,并且在所述硬掩模层的所述上侧的所述边缘区域中材料锁合地与所述硬掩模层连接。(A stacked high-cutoff group III-V power semiconductor diode having p + Or n + Substrate layer, p ‑ Layer, n having a layer thickness of 10 μm to 150 μm ‑ Region, n + Or p + Layers, wherein all layers comprise a GaAs compound, further having a first metal via layer, a second metal via layer and a hard mask layer having at least one seed opening, wherein the hard mask layer is material-locked with the substrate layer or material-locked with the p ‑ Layer connection, n ‑ A region extending within the seed opening and adjacent to the seed opening to the upper side of the hard mask layerAbove the edge region, and n ‑ A region within the seed opening and the p ‑ Layer or said n + A layer is connected and connected to the hard mask layer in the edge region of the upper side of the hard mask layer in a material-locking manner.)

1. A stacked high-cut-off III-V power semiconductor diode (10) having:

p⁺a substrate layer (12), said p⁺The substrate layer has an upper side and a lower side, and said p⁺The substrate layer comprises or consists of a GaAs compound,

p^-layer (14), said p^-The layer has an upper side and a lower side, and the p^-The layer comprises or consists of a GaAs compound,

n^-region (20), said n^-The region has an upper side and a lower side, and n is^-The region has a layer thickness (D20) of 10 to 150 [ mu ] m, and n^-The region comprises or consists of a GaAs compound,

n⁺a layer (22), said n⁺The layer has an upper side and a lower side, and n is⁺The layer comprising a GaAs compound orIs composed of GaAs and is characterized in that,

a first metal via layer (26) and a second metal via layer (24), wherein,

the first metal via layer (26) and the p⁺The lower side of the substrate layer (12) is connected in a material-locking manner,

the second metal via layer (24) and the n⁺The upper sides of the layers (22) are connected in a material-locking manner,

it is characterized in that the preparation method is characterized in that,

a hard mask layer (16) provided with an upper side, a lower side and at least one seed opening (18), wherein,

the underside of the hard mask layer (16) and the p⁺The upper side of the substrate layer (12) is connected or bonded to the p^-The upper sides of the layers (14) are connected in a material-locking manner,

n is^-A region (20) extends above an edge region of the upper side of the hard mask layer (16) adjoining the seed opening (18), and n is^-A region (20) extends above the seed opening (18) and/or within the seed opening (18),

n is^-A region (20) within the seed opening (18) with the p^-The upper sides of the layers (14) are arranged together, and said n^-A region (20) is arranged together with the hard mask layer (16) in an edge region on the upper side of the hard mask layer (16).

2. A stacked high-cut-off III-V power semiconductor diode (10) having:

n⁺a substrate layer (22), said n⁺The substrate layer has an upper side and a lower side, and n⁺The substrate layer comprises or consists of a GaAs compound,

n^-region (20), said n^-The region has an upper side and a lower side, and n is^-The region has a layer thickness (D20) of 10 to 150 [ mu ] m, and n^-The region comprises or consists of a GaAs compound,

p^-layer (14), said p^-The layer has an upper side and a lower side, and the p^-The layer comprises or consists of a GaAs compound,

p⁺layer (12), said p⁺The layer has an upper side and a lower side, and the p⁺The layer comprises a GaAs compound and is,

a first metal via layer (26) and a second metal via layer (24), wherein,

the first metal via layer (26) and the n⁺The lower side of the substrate layer (22) is connected in a material-locking manner,

n is^-The lower side of the region (20) is arranged at the n⁺Above the upper side of the substrate layer (22),

the second metal connection layer (24) and the p⁺The upper sides of the layers (12) are connected in a material-locking manner,

it is characterized in that the preparation method is characterized in that,

a hard mask layer (16) provided with an upper side, a lower side and at least one seed opening (18), wherein,

the underside of the hard mask layer (16) and the n⁺The upper side of the substrate layer (22) is connected in a material-locking manner,

n is^-A region (20) extends within the seed opening (18), and the n^-A region (20) extends above an edge region (22) of the upper side of the hard mask layer (16) adjoining the seed opening (18),

n is^-A region (20) within the seed opening (18) and the n⁺The upper side of the substrate layer (22) is connected in a material-locking manner, and n is^-The region (20) is connected to the hard mask in a material-locking manner in an edge region (22) of the upper side of the hard mask.

3. Stacked high-cut-off group III-V power semiconductor diode (10) according to claim 1, characterized in that the p⁺The backing layer (12) has a thickness of 5.10¹⁸cm^-3To 5.10²⁰cm^-3And has a layer thickness (D12) of 5 to 300 μm.

4. According to the claimsThe stacked III-V power semiconductor diode (10) according to claim 1 or 3, wherein n is⁺The layer (22) has at least 1.10¹⁸cm^-3And has a layer thickness (D22) of less than 30 μm.

5. Stacked high-cut-off group III-V power semiconductor diode (10) according to claim 1 or 3 or 4, characterized in that said n⁺The layer (22) covers said n completely or at least 95%^-A region (20) and the second metal via layer (24) completely or at least 10% covers the n⁺A layer (22).

6. Stacked high-cut-off group III-V power semiconductor diode (10) according to claim 2, characterized in that the n⁺The backing layer (22) has at least 1.10¹⁸cm^-3And has a layer thickness (D22) of 5 to 300 μm.

7. Stack-like high-cut-off group III-V power semiconductor diode (10) according to claim 2 or 6, characterized in that the p⁺The layer (12) has a thickness of 5.10¹⁸cm^-3To 5.10²⁰cm^-3And has a layer thickness (D12) of less than 30 μm.

8. Stacked high-cut-off group III-V power semiconductor diode (10) according to claim 2, 6 or 7, characterized in that p⁺The layer (12) covers said n completely or at least 95%^-A region (20) and the second metal via layer (24) completely or at least 95% covers the p⁺A layer (12).

9. Stacked high-cut-off group III-V power semiconductor diode (10) according to any of the preceding claims, characterized in that the n^-The region (20) has a first diameter above the hard mask layer (16) and the seed opening (18) has a second diameterA diameter, wherein the first diameter is at least 1.5 times the second diameter.

10. The stacked high-cutoff group III-V power semiconductor diode (10) according to any of the preceding claims, characterized in that the seed opening (18) is configured rectangular and has a width (D18) and a length.

11. The stacked high-cutoff group III-V power semiconductor diode (10) according to claim 6, characterized in that the width of the seed opening (18) extends parallel to the direction <011> or direction <001> or direction <111> of the substrate layer, or the width of the seed opening (18) extends at an angle of 15 ° or 30 ° with respect to the direction <011> or direction <001> or direction <111> of the substrate layer.

12. Stacked high-cutoff group III-V power semiconductor diode (10) according to any of the previous claims, characterized in that the upper side of the substrate layer is configured as a GaAs (100) surface or as a GaAs (111) surface.

13. Stacked high-cutoff group III-V power semiconductor diode (10) according to any of the previous claims, characterized in that at least one of the p-doped layers comprises zinc.

14. Stacked high-cutoff group III-V power semiconductor diode (10) according to any of the previous claims, characterized in that the n-doped layer comprises silicon and/or chromium and/or palladium and/or tin.

15. Stacked high-cut-off group III-V power semiconductor diode (10) according to any of the preceding claims, characterized in that all layers of the stacked III-V semiconductor diode are epitaxially produced on the respective previous layer except the substrate layer.

16. Stacked high-cutoff group III-V power semiconductor diode (10) according to any of the previous claims, characterized in that the hard mask layer (16) is made of SiO₂And/or Si₃N₄And (4) forming.

17. Stacked high-cutoff group III-V power semiconductor diode (10) according to any of the previous claims, characterized in that the hard mask layer (16) has a layer thickness of 0.1 μ ι η to 5 μ ι η.

18. Stacked high-cutoff group III-V power semiconductor diode (10) according to any of the previous claims, characterized in that a printed conductor (28) is arranged on the upper side of the hard mask layer (16) and that the printed conductor (28) is connected with the second metal via layer (24).

19. Stacked high-cut-off group III-V power semiconductor diode (10) according to any of the preceding claims, characterized in that the p^-The layer (14) has a thickness of 1.10¹⁴cm^-3To 1.10¹⁷cm^-3And has a layer thickness (D14) of 1 μm to 20 μm.

20. Stacked high-cut-off group III-V power semiconductor diode (10) according to any of the preceding claims, characterized in that the n^-The region (20) has 8-10¹³cm^-3To 1.10¹⁶cm^-3Dopant concentration of (a).

Technical Field

The invention relates to a stacked high-cutoff group III-V power semiconductor diode.

Background

GaAs Power Devices from German Ashkinazi, ISBN 965 7094-19-4, pages 8 and 9, have a p-group of GaAs⁺-n-n⁺The high voltage resistant semiconductor diode of (1). Pages 23 to 26 describe GaAs schottky diodes.

Other stacked high-cutoff group III-V power semiconductor diodes are also known from documents DE 102016013540 Al, DE 102016013541 Al, DE 102016015056 Al, DE 102017002935 Al, CN 103236436A, US 2008/0257409 a1 and DE 102017002936 Al, and corresponding production methods

In a diode, the residual or leakage current in the off-direction of operation (especially generated by the edges of the planar p-n junction or mesa structure) should be as small as possible.

Disclosure of Invention

Against this background, the object of the invention is to specify a device which further improves the prior art. The aim is in particular to reduce the off-current and to increase the breakdown voltage.

This object is achieved by a III-V power semiconductor diode with a stacked high cut-off according to the invention. Advantageous configurations of the invention are preferred embodiments.

The subject matter according to the invention provides a stacked high-cutoff group III-V power semiconductor diode having a p with an upper side and a lower side⁺A substrate layer.

p⁺The substrate layer comprises or consists of a GaAs compound.

Furthermore, a p having an upper side and a lower side is provided^-A layer, and n having an upper side and a lower side is provided^-Layer(s)

n^-The layer has a layer thickness of 10 μm to 150 μm, or in particular between 15 μm and 50 μm, or between 20 μm and 40 μm. p is a radical of^-Layer and n^-The layers comprise or consist of GaAs compounds, respectively.

Furthermore, n is provided having an upper side and a lower side⁺And (3) a layer. n is⁺The layer comprises or consists of a GaAs compound.

A first metal via layer and a second metal via layer are also provided, wherein the first metal via layer is connected with p⁺The lower side of the substrate layer is connected in a material-locking manner, and the second metal connecting layer is connected with n⁺The upper sides of the layers are connected in a material-locking manner.

n⁺The lower side of the layer is arranged at n^-Above the upper side of the region. The two layers are preferably connected to one another in a material-locking manner.

p^-The underside of the layer is preferably joined to p⁺At least a part of the upper side of the substrate layer is connected in a material-locking manner or completely with p⁺The upper side of the substrate layer is connected in a material-locking manner.

n^-Lower side of the region and p^-The upper sides of the layers are preferably connected at least partially or completely by material bonding.

In addition, the stacked high-cutoff III-V power semiconductor diode has a hard mask layer with an upper side, a lower side and at least one seed opening

Lower side of hard mask layer and p⁺Upper side of substrate layer or with p^-The upper sides of the layers are connected in a material-locking manner.

n^-The region is configured to pass through an edge of the upper side of the hard mask layer adjacent to the seed opening, and n^-The region is configured above and/or within the seed opening.

n^-The region is preferably selected from the group consisting of^-The upper side of the layer is connected and is connected in a material-locking manner with the hard mask layer in the edge region of the upper side of the hard mask layer. n is^-Regions especially in the seed opening with p^-The layers are connected in a locked manner.

Alternatively, according to the invention, a stacked high-cut-off group III-V power semiconductor diode is provided, having n⁺A substrate layer of⁺The substrate layer has an upper side and a lower side. n is⁺The substrate layer comprises or consists of a GaAs compound.

Furthermore, n having an upper side and a lower side is provided^-And (4) a region. n is^-The regions preferably have a layer thickness of 10 μm to 150 μm, or preferably a layer thickness between 15 μm and 50 μm, or preferably a layer thickness between 20 μm and 40 μm.

n^-The region comprises or consists of preferably a GaAs compound.

At n^-On the upper side of the region is arranged a p with an upper side and a lower side^-And (3) a layer. It can be understood that p^-The lower side of the layer is arranged at n^-On the upper side of the layer.

p^-The layer comprises or consists of a GaAs compound.

And is also provided with p⁺And (3) a layer. p is a radical of⁺The layer includes an upper side and a lower side. p is a radical of⁺The layer preferably comprises or consists of a GaAs compound.

A first metal connection layer and a second metal connection layer are also arranged, wherein the first metal connection layer is connected with the n⁺The underside of the substrate layer is connected in a material-locking manner. Second metal connection layer and p⁺The upper side of the substrate layer is connected in a material-locking manner.

n^-Lower side of the region and n⁺The upper side of the substrate layer is preferably at least partially connected in a material-locking manner. p is a radical of^-The underside of the layer is preferably in contact with n^-The upper sides of the regions are connected in a material-locking manner.

p⁺The underside of the layer is preferably joined to p^-The upper side of the substrate layer is locked by materials.

In addition, the stacked high-cutoff group III-V power semiconductor diode has a hard mask layer having an upper side, a lower side, and a seed opening.

Lower side of hard mask layer and n⁺The upper side of the substrate layer is connected in a material-locking manner.

n^-The region extends within the seed opening and over an edge region of the upper side of the hard mask layer adjacent to the seed opening.

In the seed crystal opening, n^-Region and n⁺The upper side of the substrate layer is connected in a material-locking manner. In the edge region at the upper side of the hard mask, n^-The regions are arranged on the hard mask and are preferably connected in a material-locking manner.

The stacked high-cut III-V power semiconductor diodes according to the invention can be constructed either in an "n-on-p" configuration (n-auf-p Struktur) or in a "p-on-n" configuration (p-auf-n Struktur). It should be noted that the corresponding substrate layer for an "n on p" structure (i.e., n)⁺Substrate layer or p⁺SubstrateLayer) and n⁺Layer and p for a "p on n" structure⁺The layers are each designed as a highly doped semiconductor contact layer. The semiconductor contact layer is connected in a bonded manner either to the first metal contact layer or to the second metal contact layer.

In other words, the mentioned semiconductor pass-layer is configured to be as low impedance as possible in order to reduce the series resistance in the forward direction (i.e. the conducting direction) and thus to reduce the power loss of the III-V power semiconductor diode.

It is understood that the metal connection region is entirely or partially composed of a metal, for example gold, in particular an alloy.

The metal connection regions can preferably be produced by electron beam evaporation or by sputtering, or in the case of thicker layers also galvanically.

The semiconductor layer of the semiconductor diode is preferably produced epitaxially, at least partially or completely, by means of MOVPE. In an alternative production method, the layer is produced in part by means of Liquid Phase Epitaxy (LPE).

It will be appreciated that GaAs compounds include, in addition to gallium and arsenic and dopants and/or impurities, other elements of the III or V main group, such as indium or aluminum.

It should be noted, however, that the semiconductor layer or semiconductor region of the III-V semiconductor diode according to the present invention comprises or consists of at least gallium and arsenic.

The layers preferably have as low a lattice dislocation (Gitterversetzung) or EL2 centers as possible.

To form the seed opening, a full-surface hard mask layer is formed by means of a masking process. The hard mask layer preferably comprises SiO₂And/or Si₃N₄Or from SiO₂And/or Si₃N₄And (4) forming.

If the substrate layer is constructed as p⁺Substrate layer, it will be understood that p^-The layer covers p either over the whole surface or only in the seed opening (e.g. by deposition after application of a hard mask layer)⁺An upper side of the substrate layer.

For example, p^-Layer before applying mask layer at p⁺The substrate layer is grown over the whole area or, alternatively, by selective epitaxy within the seed opening after the hard mask layer is applied.

N constructing drift region of III-V semiconductor diode^-The region is deposited within the seed opening and beyond the seed opening, not only in height but also in width.

Thus, n^-The height of the region is greater than the depth of the seed opening or the thickness of the hard mask layer.

Further, n is^-The region has a first region having a first diameter within the seed opening and a second region having a second diameter above the seed opening, wherein the first diameter corresponds to the diameter of the seed opening and the second diameter is greater than the diameter of the seed opening.

Thus, n^-The region covers an edge region of the surface of the hard mask layer adjacent to the seed opening. The edge region surrounds the seed opening in a distance to the seed opening, wherein the distance can be varied, for example, in dependence on the direction such that n^-The region covers at least the seed opening in a projection perpendicular to the hard mask layer.

E.g. by deposition of p in a common MOVPE or LPE step^-Layer to realize overgrowth

The other layer preferably completely or at least substantially surrounds n^-A surface of the region adjacent to the hard mask layer. In other words, the other layers extend through n from the upper side of the hard mask layer, respectively^-Regions up to the hard mask layer.

Leakage current in the edge region or a current path extending through the edge is suppressed by the hard mask layer.

The semiconductor diode according to the invention has the advantage of a particularly high breakdown voltage.

According to one embodiment, p⁺The substrate layer has 1.10¹⁸cm^-3To 5.10²⁰cm^-3And has a layer thickness of 2 μm to 300 μmDegree, or n⁺The substrate layer has at least 1.10¹⁸cm^-3And has a layer thickness of 2 μm to 300 μm, wherein n⁺The layer has at least 1.10¹⁸cm^-3And has a layer thickness of less than 30 μm, or p⁺The layer has 5.10¹⁸cm^-3To 5.10²⁰cm^-3And has a layer thickness of less than 30 μm.

In another embodiment, n⁺The layer completely or at least 95% covers n^-The region, and the second metal via layer completely or at least 95% covers n⁺Layer, or, p⁺The layer completely or at least 95% covers n^-Area, and the second metal via layer completely or at least 95% covers p⁺And (3) a layer.

According to another embodiment, n^-The region has a first diameter above the hard mask layer and the seed opening has a second diameter, wherein the first diameter is at least 1.5 times the second diameter.

By sufficient overgrowth (i.e. as wide an edge region as possible surrounding the seed opening, the edge region being defined by n^-Area coverage) to reduce or completely block leakage current.

According to a further embodiment, the seed opening is configured rectangular (e.g. quadrangular or square) and has a width and a length.

In one embodiment, the width of the seed opening extends parallel to the direction <011> or the direction <001> or the direction <111> of the substrate layer or at an angle of 15 ° or 30 ° relative to the direction <011> or the direction <001> or the direction <111> of the substrate layer. The alignment of the seed opening to the underlying layer (especially the substrate layer) affects the degree of overgrowth.

According to a further embodiment, the upper side of the substrate layer is formed as a GaAs (100) surface or as a GaAs (111) surface.

In another embodiment, at least one of the p-doped layers comprises zinc. The at least one n-doped layer preferably comprises silicon and/or chromium and/or palladium and/or tin.

According to a further embodiment, all layers of the stacked III-V semiconductor diode, except for the substrate layer, are produced epitaxially (for example by means of LPE and MOVPE) on the respective preceding layer.

In another embodiment, the hard mask layer is made of SiO₂And/or Si₃N₄And (4) forming. It will be understood that the removal of SiO from the hard mask layer is not excluded thereby₂And/or Si₃N₄With other foreign atoms (e.g., impurities) or layers in addition.

According to another embodiment, the hard mask layer has a layer thickness of 0.5 μm to 1 μm. A sufficient layer thickness ensures reliable suppression of leakage currents.

In a further embodiment, a conductor track is arranged on the upper side of the hard mask layer, wherein the conductor track is electrically connected to the second metal contact layer. The conductor tracks are arranged, for example, on the upper side of the hard mask layer in a circumferential manner at a distance from the seed opening.

The conductor tracks are spaced apart from the second metallization layer or arranged directly adjacent to the second metallization layer, for example. The second metal connection layer can also extend above the upper side of the hard mask layer.

The second metal via layer and the conductor tracks can be used both for making electrical contact and for dissipating heat.

According to another embodiment, p^-The layer has 1.10¹⁴cm^-3To 1.10¹⁷cm^-3And a layer thickness of 1 μm to 40 μm. n is^-The region preferably has a value of 8.10¹³cm^-3To 1.10¹⁶cm^-3Dopant concentration of (a).

Drawings

The invention is explained in more detail below with reference to the drawings. Like parts are herein denoted by the same reference numerals. The illustrated embodiments are very schematic, i.e. the spacings and the transverse and vertical extensions are not to scale and, as long as not stated otherwise, do not have a derivable geometric relationship to one another. The figures show:

FIG. 1 shows a layer view of a first embodiment of a stacked III-V semiconductor diode;

FIG. 2 shows a cross-sectional view of a second embodiment of a stacked III-V semiconductor diode;

FIG. 3 shows a cross-sectional view of a third embodiment of a stacked III-V semiconductor diode;

fig. 4a-c in combination with fig. 1 to 3 show cross-sectional views of metallization variants of stacked III-V semiconductor diodes according to one of the embodiments.

Detailed Description

For clarity, only a cross-sectional view or cross-sectional view of the III-V semiconductor diode 10 is shown in all figures. It should be noted, however, that all III-V semiconductor diodes 10 depicted in cross-sectional view have a square, rectangular or circular periphery in top view.

In other words, the group III-V semiconductor diode has the same layer sequence in a top view as in the corresponding sectional view. Furthermore, for all the embodiments shown, the group III-V semiconductor diode 10 has an upper side and a lower side, wherein the group III-V semiconductor diode is preferably arranged as a so-called "DIE" on a mount which is referred to as a metal frame or metal mount (also "leadframe"), by means of a metal connection via layer which is formed at the lower side. Forming the metal connection-through layer as large as possible, in particular over the entire surface, improves the thermal coupling to the base.

It should be further noted that all semiconductor layers formed from the lower side of the group III-V semiconductor diode are configured to be planar.

It should also be noted that in all of the illustrated embodiments, a substrate layer, i.e., p, is configured at the underside of the group III-V semiconductor diode⁺Substrate layer or n⁺A substrate layer. It will be appreciated that the substrate layer has a thickness in the initial state of between 400 μm and 700 μm, which thickness depends on the size of the initial semiconductor substrate wafer. In other words, a 3-inch semiconductor substrate wafer generally has a smaller thickness than a 6-inch semiconductor substrate wafer.

In order to reduce the series resistance in the forward direction, the semiconductor substrate wafer is thinned before the formation of the metal connection via, wherein the residual thickness is preferably in the range between 80 μm and 200 μm, or preferably in the range from 120 μm to 150 μm, for reasons of mechanical stability.

The drawing of fig. 1 shows a first embodiment of a stacked III-V semiconductor diode 10 with an "n on p" structure. Here, the n-doped semiconductor layer is formed above the p-doped semiconductor layer.

At p with layer thickness D12⁺The upper side of the substrate layer 12 is provided over its entire surface with p having a layer thickness D14^-Layer 14. At p^-On the upper side of the layer 14 is arranged a hard mask layer 16 having a layer thickness D16 and a seed opening 18 having a width D18 and a length (into and out of the image plane) not shown.

At p^-N having a height D20 is arranged within the seed opening 18 on the upper side of the layer 14^- Region 20 in which n^-Region 20 also extends above an edge region 22 of the upper side of hard mask layer 16 adjacent to the seed opening. It will be appreciated that the edge region 22 extends around the seed opening 18, n^-The region 20 extends in all directions beyond the seed opening 18 to above a portion of the upper side of the hard mask layer 16.

n^-The surface of region 20 adjacent to hardmask layer 16 is provided with n of layer thickness D22⁺The layer 22 covers or surrounds. n is⁺The layer 22 is in turn preferably completely covered or surrounded by the second metal via layer 24 with a layer thickness D24.

The first metal via layer 26 with layer thickness D26 is formed in a planar manner at p⁺On the underside of the substrate layer 12. The metal via layer 26 preferably covers p over the entire surface or at least over 90% of the surface area⁺The underside of the substrate layer 12. Thereby improving heat dissipation under high current loads.

A conductor track 28 is arranged around the seed opening 18 and at a distance from the seed opening 18 and the second metal via layer 24, wherein the conductor track 28 is electrically connected to the second metal via layer 24 via at least one via 30. For this purpose, a connection for connecting the contacts is formed on the conductor track 28 and on the second connection layer, respectivelyJoint surface of wire 30

32。

A second embodiment of the semiconductor diode 10 is shown in the drawing of fig. 2. Only the differences from the drawing of fig. 1 are explained below.

P of the semiconductor diode 10^- Layer 14 extends only to p⁺Above the region of the upper side of the substrate layer 12 that is recessed from the hard mask layer 16. Thus n is^- Layer 14 is built up within seed opening 18.

The drawing of fig. 3 shows a third embodiment. Only the differences from the drawing of fig. 1 are explained below.

The stacked III-V semiconductor diode 10 has a "p-on-n" structure, i.e., -n⁺Layer 22 is configured as n with a layer thickness D22⁺The substrate layer 22, and the hard mask layer 16 having a layer thickness D16 are disposed at n⁺On the upper side of the substrate layer 22.

P with layer thickness D14^-Layer 14 covers n^-The upper side of the region 20 is followed by p with a layer thickness D12⁺Layer 12 and a second metal via layer 24 having a layer thickness D24.

One advantage of embodiments of the "p-on-n" structure is that the electrical performance of the III-V semiconductor diode 10 is improved by: p is a radical of⁺The resistance of the layer is n⁺At least 5 times to 10 times the resistance of the layer. This effect is due, inter alia, to the large difference in the effective mass of holes compared to the effective mass of electrons.

Fig. 4a-c show cross-sectional views of a total of three different configurations of the second via layer 24 of the stacked III-V semiconductor diode 10, respectively. For the sake of clarity, only a part of the semiconductor layers is shown in each case. Constructing a semiconductor pass layer HLK having an upper side and a lower side to represent n⁺Layer or p⁺And (3) a layer.

In all three configurations, the upper side of the semiconductor via layer HLK is connected in a material-locking manner to the second metal via layer 24.

At least one respective contact surface 32 is formed on the upper side of the second via layer 24. A bond wire (also known as a bond wire (bonddry)) can be attached to the bond pad (not shown).

In the embodiment of fig. 4a, the second via layer 24 not only completely surrounds the semiconductor via layer HLK in the first region, but is also formed to surround the upper side of the hard mask layer 16 in the second region. In the second region, two joining surfaces 32 are formed on the upper side of the second via layer 24. The bond wires (also referred to as bond wires) can be connected to a bonding surface (not shown).

In the embodiment of fig. 4b, the second via layer 24 surrounds the semiconductor via layer HLK in the first region. A joining surface 32 is formed on the upper side of the second via layer 24.

In the embodiment of fig. 4c, the second via layer 24 is formed only on the cover side of the semiconductor via layer HLK in the first regionIn the above, that is, the second via layer 24 is not formed at the side of the semiconductor via layer HLK. The joining surface 32 is formed on the upper side of the second connection layer 24 formed on the cover side.