阅读说明：本技术 固态摄像装置和电子设备 (Solid-state image pickup device and electronic apparatus ) 是由 大浦雅史 于 2019-03-15 设计创作，主要内容包括：本技术涉及能够提高与晶体管的布置有关的自由度的固态摄像装置和电子设备。本发明设置有：光电转换单元,其被构造成进行光电转换；沟槽,其在深度方向上穿透半导体基板,且形成在分别形成于相邻的像素中的各所述光电转换单元之间；以及PN结区域,其由所述沟槽的侧壁上的P型区域和N型区域构成。这里,在所述光电转换单元周围的侧边的一部分包括：未形成有所述P型区域的区域或较薄地形成有所述P型区域的区域。在所述光电转换单元周围的四个侧边中的至少一个侧边上形成有所述PN结区域,并且在其余的侧边上未形成有所述P型区域。本技术能够应用于例如背面照射式CMOS图像传感器。(The present technology relates to a solid-state image pickup device and an electronic apparatus capable of improving the degree of freedom regarding the arrangement of transistors. The invention is provided with: a photoelectric conversion unit configured to perform photoelectric conversion; a trench penetrating the semiconductor substrate in a depth direction and formed between the photoelectric conversion units respectively formed in adjacent pixels; and a PN junction region composed of a P-type region and an N-type region on a sidewall of the trench. Here, a part of the side around the photoelectric conversion unit includes: a region where the P-type region is not formed or a region where the P-type region is thinly formed. The PN junction region is formed on at least one of four sides around the photoelectric conversion unit, and the P-type region is not formed on the remaining sides. The present technology can be applied to, for example, a backside-illuminated CMOS image sensor.)

1. A solid-state image pickup device comprising:

a photoelectric conversion unit configured to perform photoelectric conversion;

a trench penetrating the semiconductor substrate in a depth direction and formed between the photoelectric conversion units respectively formed in adjacent pixels; and

a PN junction region composed of a P-type region and an N-type region on a sidewall of the trench,

wherein a part of the side around the photoelectric conversion unit includes: a region where the P-type region is not formed or a region where the P-type region is thinly formed.

2. The solid-state image pickup device according to claim 1,

the PN junction region is formed on at least one of four sides around the photoelectric conversion unit, and the P-type region is not formed on the remaining sides.

3. The solid-state image pickup device according to claim 1,

the P-type region for forming the PN junction region is formed to be thinner in thickness than the other P-type regions on at least one of four sides around the photoelectric conversion unit.

4. The solid-state image pickup device according to claim 1,

in a part of the side around the photoelectric conversion unit, the P-type region for forming the PN junction region is formed to be thinner in thickness than the other P-type regions.

5. The solid-state image pickup device according to claim 1,

in a part of the side around the photoelectric conversion unit, the PN junction region is formed to be thinner in thickness than the other PN junction regions.

6. The solid-state image pickup device according to claim 1,

the P-type region and the N-type region are solid phase diffusion layers.

7. An electronic apparatus in which a solid-state image pickup device is mounted, the solid-state image pickup device comprising:

a photoelectric conversion unit configured to perform photoelectric conversion;

a trench penetrating the semiconductor substrate in a depth direction and formed between the photoelectric conversion units respectively formed in adjacent pixels; and

a PN junction region composed of a P-type region and an N-type region on a sidewall of the trench,

wherein a part of the side around the photoelectric conversion unit includes: a region where the P-type region is not formed or a region where the P-type region is thinly formed.

Technical Field

The present technology relates to a solid-state image pickup device and an electronic apparatus, and particularly relates to a solid-state image pickup device and an electronic apparatus as follows: they have a P-type solid-phase diffusion layer and an N-type solid-phase diffusion layer formed on the side walls of the inter-pixel light-shielding walls formed between the pixels to form a strong electric field region and hold electric charges therein, thereby increasing the saturation charge amount Qs of each pixel.

Background

Conventionally, the following techniques are known: for the purpose of increasing the saturation charge amount Qs of each pixel of the solid-state image pickup device, a P-type diffusion layer and an N-type diffusion layer are formed on the side wall of a trench formed between each pixel to form a strong electric field region and hold electric charges therein (for example, see patent document 1).

Reference list

Patent document

Patent document 1: japanese patent application laid-open No. 2015-162603

Disclosure of Invention

Problems to be solved by the invention

However, the configuration disclosed in patent document 1 may weaken pinning of a silicon (Si) substrate on a light incident side, generated charges flow into a photodiode and dark characteristics are deteriorated, such as occurrence of white spots and generation of dark current. Further, the formation of the strong electric field region may limit the region in which the transistor and the like can be arranged.

The present technology has been made in view of the above circumstances, and can suppress degradation of dark characteristics (dark characteristics) and improve the degree of freedom in layout of transistors and the like.

Technical scheme for solving problems

A solid-state image pickup device according to an aspect of the present technology includes: a photoelectric conversion unit configured to perform photoelectric conversion; a trench penetrating the semiconductor substrate in a depth direction and formed between the photoelectric conversion units respectively formed in adjacent pixels; and a PN junction region composed of a P-type region and an N-type region on a sidewall of the trench. Here, a part of the side around the photoelectric conversion unit includes: a region where the P-type region is not formed or a region where the P-type region is thinly formed.

An electronic apparatus according to an aspect of the present technology is an electronic apparatus having a solid-state image pickup device mounted therein, the solid-state image pickup device including: a photoelectric conversion unit configured to perform photoelectric conversion; a trench penetrating the semiconductor substrate in a depth direction and formed between the photoelectric conversion units respectively formed in adjacent pixels; and a PN junction region composed of a P-type region and an N-type region on a sidewall of the trench. Here, a part of the side around the photoelectric conversion unit includes: a region where the P-type region is not formed or a region where the P-type region is thinly formed.

The solid-state image pickup device according to an aspect of the present technology includes: the photoelectric conversion unit configured to perform photoelectric conversion; the trenches penetrating the semiconductor substrate in a depth direction and formed between the photoelectric conversion units respectively formed in adjacent pixels; and the PN junction region including the P-type region and the N-type region on the sidewall of the trench. Further, a part of the side around the photoelectric conversion unit includes: a region where the P-type region is not formed or a region where the P-type region is thinly formed.

The electronic apparatus according to an aspect of the present technology includes the above-described solid-state image pickup device.

The invention has the advantages of

According to the present technology, it is possible to suppress deterioration of dark characteristics and improve the degree of freedom in arrangement of transistors and the like.

Note that the effect described here is not necessarily restrictive, but any effect described in the present disclosure may be exhibited.

Drawings

Fig. 1 is a diagram illustrating a configuration example of an image pickup apparatus.

Fig. 2 is a diagram illustrating a configuration example of an image pickup element.

Fig. 3 is a vertical direction sectional view showing a first configuration example of a pixel to which the present technique is applied.

Fig. 4 is a front side plan view of a first embodiment of a pixel to which the present technology is applied.

Fig. 5 is a circuit diagram of a pixel.

Fig. 6 is a diagram for explaining a DTI82 and a method for manufacturing the periphery thereof.

Fig. 7 is a vertical direction sectional view showing a second configuration example of a pixel to which the present technology is applied.

Fig. 8 is a vertical direction sectional view showing a third configuration example of a pixel to which the present technology is applied.

Fig. 9 is a vertical direction sectional view showing a fourth configuration example of a pixel to which the present technology is applied.

Fig. 10 is a vertical direction sectional view showing a fifth configuration example of a pixel to which the present technology is applied.

Fig. 11 is a vertical direction sectional view showing a sixth configuration example of a pixel to which the present technology is applied.

Fig. 12 is a vertical direction sectional view showing a seventh configuration example of a pixel to which the present technology is applied.

Fig. 13 is a vertical direction sectional view showing an eighth configuration example of a pixel to which the present technology is applied.

Fig. 14 is a vertical direction sectional view showing a ninth configuration example of a pixel to which the present technology is applied.

Fig. 15 is a vertical direction sectional view showing a tenth configuration example of a pixel to which the present technology is applied.

Fig. 16 is a vertical sectional view and a plan view showing an eleventh configuration example of a pixel to which the present technology is applied.

Fig. 17 is a vertical sectional view and a plan view showing a twelfth configuration example of a pixel to which the present technology is applied.

Fig. 18 is a vertical sectional view showing a thirteenth configuration example of a pixel to which the present technology is applied.

Fig. 19 is a vertical direction sectional view showing a fourteenth configuration example of a pixel to which the present technology is applied.

Fig. 20 is a plan view showing one configuration example of a pixel to which the present technology is applied.

Fig. 21 is a plan view showing a fifteenth configuration example of a pixel to which the present technology is applied.

Fig. 22 is a plan view showing another fifteenth configuration example of a pixel to which the present technology is applied.

Fig. 23 is a plan view showing still another fifteenth configuration example of a pixel to which the present technology is applied.

Fig. 24 is a diagram for explaining a manufacturing process of a pixel to which the present technology is applied.

Fig. 25 is a diagram for explaining a manufacturing process of a pixel to which the present technology is applied.

Fig. 26 is a plan view showing a sixteenth configuration example of a pixel to which the present technology is applied.

Fig. 27 is a plan view showing another sixteenth configuration example of a pixel to which the present technology is applied.

Fig. 28 is a diagram for explaining a manufacturing process of a pixel to which the present technology is applied.

Fig. 29 is a diagram for explaining a manufacturing process of a pixel to which the present technology is applied.

Fig. 30 is a diagram for explaining a manufacturing process of a pixel to which the present technology is applied.

Fig. 31 is a plan view showing an eighteenth configuration example of a pixel to which the present technology is applied.

Fig. 32 is a plan view showing another eighteenth configuration example of a pixel to which the present technology is applied.

Fig. 33 is a diagram for explaining a manufacturing process of a pixel to which the present technology is applied.

Fig. 34 is a diagram for explaining a manufacturing process of a pixel to which the present technology is applied.

Fig. 35 is a diagram for explaining a manufacturing process of a pixel to which the present technology is applied.

Fig. 36 is a diagram showing a schematic configuration example of the endoscopic surgery system.

Fig. 37 is a block diagram showing an example of the functional configuration of a camera and a CCU (camera control unit).

Fig. 38 is a block diagram showing a schematic configuration example of the vehicle control system.

Fig. 39 is an explanatory diagram showing an example of the mounting positions of the vehicle exterior information detection unit and the imaging unit.

Detailed Description

Hereinafter, the best mode (hereinafter, referred to as an embodiment) for implementing the present technology will be described in detail with reference to the accompanying drawings.

Since the present technology can be applied to an imaging apparatus, a case where the present technology is applied to an imaging apparatus will be described here as an example. Note that here, even though the description will be given taking an image pickup apparatus as an example, the present technology is not limited to the application of the image pickup apparatus, and the present technology can be applied to various apparatuses such as: an image pickup device such as a digital camera or a photographic camera; a portable terminal device having an image pickup function such as a mobile phone; a copying machine using an image pickup device as an image reading unit; and electronic apparatuses and the like using an image pickup device as an image pickup unit (photoelectric conversion unit). Note that a module-like configuration (i.e., a camera module) mounted on an electronic apparatus may be employed as the image pickup device.

Fig. 1 is a block diagram showing a configuration example of an image pickup apparatus as an example of an electronic apparatus of the present technology. As shown in fig. 1, the image pickup apparatus 10 includes: an optical system including a lens system 11 and the like, an image pickup device 12, a DSP (digital signal processor) circuit 13 as a camera signal processing unit, a frame memory 14, a display unit 15, a recording unit 16, an operating system 17, a power supply system 18, and the like.

Then, the DSP circuit 13, the frame memory 14, the display unit 15, the recording unit 16, the operating system 17, and the power supply system 18 are connected to each other via the bus 19. The CPU 20 controls each unit in the image pickup apparatus 10.

The lens system 11 acquires incident light (image light) from an object and forms an image on an imaging surface of the imaging element 12. The image pickup element 12 converts the light amount of incident light imaged on the image pickup surface by the lens system 11 into an electrical signal in units of pixels, and outputs the electrical signal as a pixel signal. As the image pickup element 12, an image pickup element (image sensor) including the following pixels can be used.

The display unit 15 includes a panel-type display unit such as a liquid crystal display unit or an organic Electro Luminescence (EL) display unit, and displays a moving image or a still image picked up by the image pickup element 12. The recording unit 16 records the moving image or the still image picked up by the image pickup element 12 in a recording medium such as a Hard Disk Drive (HDD) or a memory card.

The operating system 17 issues operation commands for various functions of the image pickup apparatus by user operations. The power supply system 18 appropriately supplies various power supplies serving as operation power supplies of the DSP circuit 13, the frame memory 14, the display unit 15, the recording unit 16, and the operating system 17 to these power supply targets.

< construction of image pickup device >

Fig. 2 is a block diagram showing a configuration example of the image pickup element 12. The image pickup element 12 may be a Complementary Metal Oxide Semiconductor (CMOS) image sensor.

The image pickup element 12 includes a pixel array unit 41, a vertical driving unit 42, a column processing unit 43, a horizontal driving unit 44, and a system control unit 45. The pixel array unit 41, the vertical driving unit 42, the column processing unit 43, the horizontal driving unit 44, and the system control unit 45 are formed on a semiconductor substrate (chip) (not shown).

In the pixel array unit 41, unit pixels (for example, pixels 50 in fig. 3) are two-dimensionally arranged in a matrix, each of which includes a photoelectric conversion element that generates photoelectric charges having a charge amount corresponding to an incident light amount, and the generated photoelectric charges are accumulated inside the photoelectric conversion element. Note that, hereinafter, photoelectric charges having a charge amount corresponding to an incident light amount may be simply described as "charges", and a unit pixel may be simply described as a "pixel".

Further, in the pixel array unit 41, with respect to the pixel arrangement arranged in a matrix manner, a pixel drive line 46 is formed in the left-right direction in fig. 2 (pixel arrangement direction of the pixel row) for each row, and a vertical signal line 47 is formed in the up-down direction in fig. 2 (pixel arrangement direction of the pixel column) for each column. One end of the pixel driving line 46 is connected to an output end of the vertical driving unit 42 corresponding to each row.

The image pickup element 12 further includes a signal processing unit 48 and a data storage unit 49. The processing by the signal processing unit 48 and the data storage unit 49 may be processing by an external signal processing unit (for example, a Digital Signal Processor (DSP)) provided on a substrate separate from the substrate of the image pickup element 12 or by software, or the signal processing unit 48 and the data storage unit 49 may be mounted on the same substrate as the substrate of the image pickup element 12.

The vertical driving unit 42 is a pixel driving unit as follows: which includes a shift register, an address decoder, and the like, and drives all pixels of the pixel array unit 41 simultaneously or drives the pixels of the pixel array unit 41 row by row, and the like. Although illustration of a specific configuration is omitted, the vertical drive unit 42 has a configuration including a readout scanning system and a sweep-out scanning system, or capable of batch sweeping-out (batch sweeping) and batch transfer.

The readout scanning system sequentially selects and scans the unit pixels of the pixel array unit 41 row by row to read signals from the unit pixels. In the case of line driving (rolling shutter operation), regarding scan-out, scan-out scanning is performed earlier than the read-out scanning by a time corresponding to the shutter speed for a read line on which the read-out scanning is to be performed by the read-out scanning system. Further, in the case of global exposure (global shutter operation), the batch scan is performed one time corresponding to the shutter speed ahead of the batch transfer.

By the above-described sweeping out, unnecessary electric charges are swept out (reset) from the photoelectric conversion elements of the unit pixels of the read row. Then, by sweeping out (resetting) unnecessary electric charges, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to an operation of discarding photoelectric charges of the photoelectric conversion element and starting a new exposure (starting accumulation of the photoelectric charges).

The signal read by the readout operation of the readout scanning system corresponds to the amount of light incident since the immediately preceding readout operation or electronic shutter operation. In the case of row driving, a time period from the readout timing of the immediately preceding readout operation or from the sweep-out timing of the electronic shutter operation to the readout timing of the current readout operation is an accumulation period (exposure period) of the photo-charges in the unit pixel. In the case of global exposure, the period from batch sweep to batch transfer is an accumulation period (exposure period).

Pixel signals output from the respective unit pixels in the pixel row selectively scanned by the vertical driving unit 42 are supplied to the column processing unit 43 through the respective corresponding vertical signal lines 47. The column processing unit 43 performs predetermined signal processing on pixel signals output from the respective unit pixels in the selected row through the vertical signal line 47 for each pixel column of the pixel array unit 41, and temporarily holds the pixel signals after the signal processing.

Specifically, the column processing unit 43 performs at least noise removal processing (for example, Correlated Double Sampling (CDS) processing) as signal processing. The correlated double sampling by the column processing unit 43 removes fixed pattern noise (e.g., reset noise and threshold difference of an amplifying transistor, etc.) inherent to the pixel. Note that the column processing unit 43 can have, for example, an analog-to-digital (AD) conversion function in addition to being capable of performing noise removal processing, and the column processing unit 43 can output the signal level as a digital signal.

The horizontal driving unit 44 is configured by a shift register, an address decoder, and the like, and the horizontal driving unit 44 sequentially selects unit circuits corresponding to pixel columns of the column processing unit 43. The pixel signals signal-processed by the column processing unit 43 are sequentially output to the signal processing unit 48 by selective scanning by the horizontal driving unit 44.

The system control unit 45 is constituted by a timing generator or the like that generates various timing signals, and the system control unit 45 carries out driving and control of the vertical driving unit 42, the column processing unit 43, the horizontal driving unit 44, and the like based on the various timing signals generated by the timing generator.

The signal processing unit 48 has at least an addition processing function, and the signal processing unit 48 performs various signal processing such as addition processing on the pixel signal output from the column processing unit 43. The data storage unit 49 temporarily stores data necessary for signal processing in the signal processing unit 48.

< Structure of Unit Pixel >

Next, a specific structure of the unit pixels 50 arranged in a matrix form in the pixel array unit 41 will be explained. According to the pixel 50 described below, it is possible to reduce the possibility of deterioration of dark characteristics (for example, occurrence of white spots and generation of dark current) due to weakening of pinning of a silicon (Si) substrate (Si substrate 70 in fig. 3) on the light incident side and flowing of generated electric charges into a photodiode (PD 71 in fig. 3).

< construction example of pixel of first embodiment >

Fig. 3 is a vertical sectional view of a pixel 50a as a first embodiment of a pixel 50 to which the present technology is applied, and fig. 4 is a plan view of the front side of the pixel 50 a. Note that fig. 3 corresponds to the position of line X-X' in fig. 4.

The pixel 50 will be described below by taking the case of the back-illuminated type as an example. However, the present technology can also be applied to the front-illuminated type.

The pixel 50 shown in fig. 3 has a Photodiode (PD) 71, and the PD71 is a photoelectric conversion element of each pixel formed inside the Si substrate 70. A P-type region 72 is formed on the light incident side (lower side in fig. 3, i.e., the back surface side) of the PD71, and a planarization film 73 is further formed below the P-type region 72. The boundary between the P-type region 72 and the planarization film 73 is the backside Si interface 75.

A light-shielding film 74 is formed in the planarization film 73. The light shielding film 74 is provided for preventing light from leaking into an adjacent pixel, and the light shielding film 74 is formed between the PD71 and the adjacent PD 71. The light shielding film 74 is formed using a metal material such as tungsten (W), for example.

An on-chip lens (OCL) 76 for collecting incident light to the PD71 is formed on the planarization film 73 and on the back surface side of the Si substrate 70. Inorganic materials can be used to form OCL 76. For example, SiN, SiO or SiO can be used_xN_y(Note, 0)<x is less than or equal to 1 and 0<y≤1)。

Although not shown in fig. 3, a configuration may be adopted in which a transparent plate such as a glass cover or resin is bonded on the OCL 76. Further, although not shown in fig. 3, a configuration may be adopted in which a color filter layer is formed between the OCL 76 and the planarization film 73. Further, the color filter layer has a plurality of color filters provided corresponding to each pixel, and the colors of the respective color filters can be arranged according to, for example, a bayer array.

An active region (P well) 77 is formed on the opposite side (upper side in fig. 3, i.e., front surface side) of the light incident side of the PD 71. In the active region 77, an element isolation region (hereinafter referred to as shallow trench isolation) 78 for isolating a pixel transistor or the like is formed.

A wiring layer 79 is formed on the front side (upper side in fig. 3) of the Si substrate 70 and the active region 77, and a plurality of transistors are formed in the wiring layer 79. Fig. 3 shows an example in which the transfer transistor 80 is formed. The transfer transistor (gate) 80 is formed using a vertical type transistor. That is, in the transfer transistor (gate) 80, a vertical-type transistor trench 81 is formed by opening an opening, and a Transfer Gate (TG) 80 for reading charges from the PD71 is formed in the opening.

Further, pixel transistors such as an Amplification (AMP) transistor, a Selection (SEL) transistor, and a Reset (RST) transistor are formed on the front surface side of the Si substrate 70. The arrangement of these transistors will be explained with reference to fig. 4, and their operation will be explained with reference to the circuit diagram in fig. 5.

A trench is formed between the pixels 50 a. This trench is referred to as Deep Trench Isolation (DTI) 82. The DTI82 is formed in a shape penetrating the Si substrate 70 in the depth direction (vertical direction in fig. 3, that is, the direction from the front to the back) between the adjacent pixels 50 a. In addition, the DTI82 also functions as a light shielding wall between pixels so that unnecessary light does not leak into the adjacent pixels 50 a.

Between the PD71 and the DTI82, a P-type solid-phase diffusion layer 83 and an N-type solid-phase diffusion layer 84 are formed in this order in the direction from the DTI82 side toward the PD 71. The P-type solid-phase diffusion layer 83 is formed along the DTI82 and is in contact with the back Si interface 75 of the Si substrate 70. An N-type solid phase diffusion layer 84 is formed along the DTI82 and in contact with the P-type region 72 of the Si substrate 70.

Note that the solid-phase diffusion layer refers to a layer obtained by forming a P-type layer and an N-type layer by impurity doping using a manufacturing method described later. However, in the present technology, the manufacturing method is not limited to a method using solid phase diffusion, but a P-type layer and an N-type layer generated by other manufacturing methods such as ion implantation may be provided between the DTI82 and the PD 71. Further, the PD71 in the present embodiment is constituted by an N-type region. Photoelectric conversion is performed in a partial region or the entire region of the N-type region.

The P-type solid-phase diffusion layer 83 is formed so as to be in contact with the back surface Si interface 75, and the N-type solid-phase diffusion layer 84 is not in contact with the back surface Si interface 75, and therefore, a gap is provided between the N-type solid-phase diffusion layer 84 and the back surface Si interface 75.

With such a configuration, a PN junction region between the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 forms a strong electric field region, and holds electric charges generated in the PD 71. According to this configuration, the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 formed along the DTI82 form a strong electric field region, and can hold electric charges generated in the PD 71.

If the N-type solid-phase diffusion layer 84 is formed along the DTI82 so as to be in contact with the back-surface Si interface 75 of the Si substrate 70, pinning of electric charges is weakened in a portion where the back-surface Si interface 75 of the Si substrate 70 (which is located on the light incident surface side) and the N-type solid-phase diffusion layer 84 are in contact with each other. Therefore, the generated electric charges may flow into the PD71, the dark characteristic may be deteriorated, for example, white spots may occur, and a dark current may be generated.

However, in the pixel 50a shown in fig. 3, the N-type solid phase diffusion layer 84 is configured not to contact the rear surface Si interface 75 of the Si substrate 70, and the N-type solid phase diffusion layer 84 is formed along the DTI82 so as to contact the P-type region 72 of the Si substrate 70. With such a configuration, the pinning of the electric charges can be prevented from being weakened, and therefore, the electric charges can be prevented from flowing into the PD71 and the dark characteristics can be prevented from being deteriorated.

Further, in the pixel 50a shown in fig. 3, SiO is formed on the inner wall of the DTI82₂ A sidewall film 85 is formed, and a filling material 86 made of polysilicon is buried inside the sidewall film.

The pixel 50a of the first embodiment has the following configuration: wherein the P-type region 72 is provided on the back surface side, and the PD71 and the N-type solid-phase diffusion layer 84 are absent in the vicinity of the back surface Si interface 75. With this configuration, pinning reduction near the back surface Si interface 75 does not occur. Therefore, it is possible to prevent the generated electric charges from flowing into the PD71 and prevent the dark characteristic from deteriorating.

Note that in DTI82, SiN may be employed instead of SiO employed for the sidewall film 85₂. In addition, doped polysilicon may be used in place of the polysilicon used for the fill material 86. Pinning of the sidewalls of DTI82 can be enhanced by applying a negative bias in the case where doped polysilicon is filled, or in the case where doped with an N-type impurity or a P-type impurity is used after the polysilicon is filled. Therefore, the dark characteristics can be further improved.

The arrangement of transistors formed in the pixel 50a and the operation of each transistor will be described with reference to fig. 4 and 5. Fig. 4 is a plan view of 3 × 39 pixels 50a arranged in the pixel array section 41 (fig. 2) as viewed from the front surface side (upper side of fig. 3), and fig. 5 is a circuit diagram for explaining the connection relationship between the transistors shown in fig. 4.

In fig. 4, one square represents one pixel 50 a. As shown in fig. 4, the DTI82 is formed in a manner to surround the pixel 50a (to surround the PD71 included in the pixel 50 a). Further, a transfer transistor (gate) 80, a Floating Diffusion (FD) 91, a reset transistor 92, an amplification transistor 93, and a selection transistor 94 are formed on the front surface side of the pixel 50 a.

The PD71 generates charges (signal charges) corresponding to the received light amount and accumulates the charges. The anode terminal of the PD71 is grounded, and the cathode terminal is connected to the FD 91 via the transfer transistor 80.

When the transfer transistor 80 is turned on by the transfer signal TR, the transfer transistor 80 reads out the electric charges generated in the PD71 and transfers the read-out electric charges to the FD 91.

The FD 91 holds the charge read out from the PD 71. When the reset transistor 92 is turned on by a reset signal RST, the reset transistor 92 resets the potential of the FD 91 when the charges accumulated in the FD 91 are discharged to the drain (constant voltage source Vdd).

The amplification transistor 93 outputs a pixel signal in accordance with the potential of the FD 91. That is, the amplifying transistor 93 constitutes a source follower circuit together with a load MOS (not shown) as a constant current source connected via the vertical signal line 33. A pixel signal indicating a level corresponding to the electric charge accumulated in the FD 91 is output from the amplification transistor 93 to the column processing unit 43 via the selection transistor 94 and the vertical signal line 47 (fig. 2).

When the pixel 31 is selected by the selection signal SEL, the selection transistor 94 is turned on, and the selection transistor 94 outputs a pixel signal of the pixel 31 to the column processing unit 43 via the vertical signal line 33. Each signal line for transmitting the transmission signal TR, the selection signal SEL, and the reset signal RST corresponds to the pixel driving line 46 in fig. 2.

The pixel 50a can be configured as described above, but the configuration is not limited thereto, and other configurations can be employed.

< methods for producing DTI82 and the periphery thereof >

Fig. 6 is a diagram for explaining DTI82 and a method of manufacturing the periphery of DTI 82.

When an opening for forming the DTI82 is opened in the Si substrate 70, as shown in a of fig. 6, use of SiN and SiO is utilized₂Covers the Si substrate 70 except for the position where the DTI82 is to be formed, and dry-etches the portion not covered by the hard mask to open a groove in the vertical direction up to a predetermined depth in the Si substrate 70.

Next, SiO containing phosphorus (P) as an N-type impurity is formed on the inner side of the opened groove₂Film, then heat-treated, thereby forming a film on the surface of SiO₂The film is doped with phosphorus P (hereinafter referred to as solid phase diffusion) in a portion on the Si substrate 70 side.

Next, as shown in B of FIG. 6, SiO containing phosphorus formed on the inner side of the opened groove is removed₂The film is then again subjected to heat treatment to diffuse phosphorus (P) into the inside of the Si substrate 70, and thus, an N-type solid-phase diffusion layer 84 self-aligned with the current groove shape is formed. Thereafter, the bottom of the groove is etched by dry etching, so that the groove is elongated in the depth direction.

Next, as shown in C of fig. 6, SiO containing boron (B) as a P-type impurity is formed inside the extended groove₂Film, then heat-treated, thus from SiO₂Solid phase diffusion of boron (B) is performed from the film to the Si substrate 70 side, and a P-type solid phase diffusion layer 83 self-aligned to the elongated groove shape is formed.

Thereafter, SiO containing boron (B) formed on the inner wall of the groove is removed₂And (3) a membrane.

Next, as shown in D of FIG. 6, SiO is formed on the inner wall of the opened groove₂The sidewall film 85 is formed and filled with polysilicon to form DTI 82. After that, a pixel transistor and a wiring are formed. Then, the Si substrate 70 is thinned from the back surface side. In the thinning, the bottom portion of the DTI82 including the P-type solid-phase diffusion layer 83 is simultaneously thinned. The thinning treatment is performed to a depth not reaching the N-type solid phase diffusion layer 84.

Through the above steps, a strong electric field region including the N-type solid phase diffusion layer 84 not in contact with the back surface Si interface 75 and the P-type solid phase diffusion layer 83 in contact with the back surface Si interface 75, which is adjacent to the PD71, can be formed.

< second embodiment >

Fig. 7 is a vertical sectional view of a pixel 50b of a second embodiment to which the present technique is applicable.

The second embodiment is different from the first embodiment in that a DTI82 is formed in the STI 78, and the other configuration is the same as the first embodiment. Like parts are denoted by like reference numerals, and descriptions thereof are omitted as appropriate. In the following description of the pixel 50, the same portions of the pixel 50b as those in the first embodiment are denoted by the same reference numerals, and the description thereof is appropriately omitted.

In the pixel 50b shown in fig. 7, the STI 78b formed in the active region 77 is formed up to the portion where the DTI82b is formed (formed up to the end of the pixel 50 b). Then, DTI82b is formed below STI 78 b.

In other words, the STI 78b is formed at a portion where the DTI82b is formed, and the STI 78b and the DTI82b are formed at a position where the STI 78b and the DTI82b contact each other.

By such formation, the size of the pixel 50b can be reduced as compared with the case where the STI 78b and the DTI82b are formed at different positions, for example, the pixel 50a (fig. 3) in the first embodiment.

Further, the pixel 50b of the second embodiment can also obtain the same effect as the pixel 50a of the first embodiment, that is, the effect of being able to prevent the dark characteristic from deteriorating.

< third embodiment >

Fig. 8 is a vertical sectional view of a pixel 50c of a third embodiment to which the present technique is applicable.

The third embodiment differs from the pixel 50a in the first embodiment and the pixel 50b in the second embodiment in that: a film 101 having negative fixed charges is formed on the side wall of the DTI82c, and SiO is formed₂The filler 86c is filled inside the film 101.

The pixel 50a in the first embodiment has the following configuration: wherein, SiO is formed and used on the side wall of DTI82₂And filled with polysilicon. And the pixel 50c in the third embodiment has such a configuration as follows: therein, DTI82cHas a film 101 having negative fixed charges formed on the side wall thereof, and SiO₂Filling the inside of the film 101.

The film 101 having negative fixed charges formed on the sidewall of the DTI82c can use, for example, hafnium oxide (HfO)₂) Film, alumina (Al)₂O₃) Film, zirconium oxide (ZrO)₂) Film, tantalum oxide (Ta)₂O₅) Films or titanium oxide (TiO)₂) A film is formed. These types of films have been used as a gate insulating film or the like of an insulated gate field effect transistor (insulated gate field effect transistor), and thus, a film forming method has been established. Therefore, such a film can be easily formed.

Examples of the above film formation method include a chemical vapor deposition method, a sputtering method, an atomic layer deposition method, and the like. SiO capable of reducing interface level during film formation in the case of using atomic layer deposition method₂The layer can be formed to be about 1nm thick at the same time, so that this method is preferable.

Further, examples of materials other than the above materials include: lanthanum oxide (La)₂O₃) Praseodymium oxide (Pr)₂O₃) Cerium oxide (CeO)₂) Neodymium oxide (Nd)₂O₃) Promethium oxide (Pm)₂O₃) Samarium oxide (Sm)₂O₃) Europium oxide (Eu)₂O₃) Gadolinium oxide (Gd)₂O₃) Terbium oxide (Tb)₂O₃) Dysprosium oxide (Dy)₂O₃) Holmium oxide (Ho)₂O₃) Erbium oxide (Er)₂O₃) Thulium oxide (Tm)₂O₃) Ytterbium oxide (Yb)₂O₃) Lutetium oxide (Lu)₂O₃) And yttrium oxide (Y)₂O₃)。

The film 101 having negative fixed charges can be formed using a hafnium nitride film, an aluminum nitride film, a hafnium oxynitride film, or an aluminum oxynitride film.

The film 101 having negative fixed charges described above may have silicon (Si) or nitrogen (N) added thereto as long as insulation is not impaired. The concentration of the additive is appropriately determined within a range not to impair the insulating properties of the film. Note that in order not to cause image defects such as white spots, it is preferable to add an additive such as the above-described silicon or nitrogen to the front surface of the film 101 having negative fixed charges, that is, the surface opposite to the above-described PD71 side. As described above, by adding silicon (Si) or nitrogen (N), the heat resistance of the film can be improved, and the ability to prevent ion implantation during processing can be improved.

In the third embodiment, pinning of the trench sidewalls of the DTI82 can be enhanced. Therefore, for example, the pixel 50c can more reliably prevent the dark characteristic from deteriorating than, for example, the pixel 50a in the first embodiment.

In order to form the DTI82 in the third embodiment, the back surface side in the state shown in D of fig. 6 is polished until the polysilicon filled as the filler 86 is exposed, and then the filler 86 (polysilicon) and the sidewall film 85 (SiO) inside the groove are removed by photoresist and wet etching₂) And forming a film 101, thereafter, with SiO₂Filling the groove.

Note that instead of SiO as the filler material₂The inside of the groove may be filled with a metal material such as tungsten (W). In this case, since light transmission of the DTI82 to incident light from an oblique direction is suppressed, color mixing can be improved.

< fourth embodiment >

Fig. 9 is a vertical sectional view of a pixel 50d of a fourth embodiment to which the present technique is applicable.

In the fourth embodiment, the pixel 50d is different from the pixel 50a in the first embodiment in that: the N-type solid-phase diffusion layer 84d formed along the DTI82 has a concentration gradient in the depth direction of the Si substrate 70, and the other configuration is the same as that of the pixel 50a in the first embodiment.

The N-type impurity concentration of the N-type solid-phase diffusion layer 84 of the pixel 50a in the first embodiment is independent of the depth direction and is constant, whereas the N-type impurity concentration of the N-type solid-phase diffusion layer 84d of the pixel 50d in the fourth embodiment differs depending on the depth direction.

That is, the N-type solid-phase diffusion layer 84d-1 near the front side of the N-type solid-phase diffusion layer 84d of the pixel 50d is formed to have a high N-type impurity concentration, and the N-type solid-phase diffusion layer 84d-2 near the back side is formed to have a low N-type impurity concentration.

The pixel 50d in the fourth embodiment has a new effect of easily reading out charges, since the pixel 50d in the fourth embodiment has a shallow potential on the back surface side because of having the N-type solid-phase diffusion layer 84d with a concentration gradient, in addition to the same effect as the pixel 50a in the first embodiment.

In order to provide a concentration gradient in the N-type solid-phase diffusion layer 84d, etching damage is made on the side wall of the groove when the groove of the DTI82 is opened, for example. Therefore, the difference in the amount of solid-phase diffusion doping due to the amount of damage can be utilized.

Note that, instead of providing a concentration gradient in the N-type solid-phase diffusion layer 84d, the P-type impurity concentration of the P-type solid-phase diffusion layer 83d near the front surface side may be made low, and the P-type impurity concentration of the P-type solid-phase diffusion layer 83d near the back surface side may be made high. Even in this case, the same effect as that in the case where the concentration gradient is provided in the N-type solid-phase diffusion layer 84d can be obtained.

Further, both the N-type solid-phase diffusion layer 84d and the P-type solid-phase diffusion layer 83d may have a concentration gradient.

< fifth embodiment >

Fig. 10 is a vertical sectional view of a pixel 50e of a fifth embodiment to which the present technique is applicable.

The pixel 50e in the fifth embodiment is different from the first embodiment in that: formed of SiO on the inner wall of DTI82e₂The resultant sidewall film 85e is formed thicker than the sidewall film 85 of the pixel 50a in the first embodiment, and the other configuration is the same as that of the first embodiment.

Due to SiO₂Is lower than that of Si, incident light entering the Si substrate 70 is reflected according to Snell's law, thereby suppressing the light from being transmitted to the adjacent pixel 50. However, if the film thickness of the side wall film 85 is thin, snell's law cannot be fully established, and the transmitted light may increase.

Since the film thickness of the sidewall film 85e of the pixel 50e in the fifth embodiment is formed thick, deviation from snell's law can be reduced, and reflection of incident light on the sidewall film 85e increases, so that transmission of incident light to the adjacent pixel 50e can be reduced. Therefore, the pixel 50e in the fifth embodiment can obtain the same effect as the pixel 50a in the first embodiment, and can also have an effect of suppressing occurrence of color mixing with the adjacent pixel 50e due to oblique incident light.

< sixth embodiment >

Fig. 11 is a vertical sectional view of a pixel 50f of a sixth embodiment to which the present technique is applicable.

The pixel 50f in the sixth embodiment is different from the pixel 50a in the first embodiment in that: a concentration gradient is set by doping a P-type impurity in the region 111 between the PD71 and the back Si interface 75 so that the P-type impurity concentration in the Si substrate 70 is higher on the back side than on the front side, while the other configuration of the pixel 50f in the sixth embodiment is the same as that of the pixel 50a in the first embodiment.

Referring again to fig. 3, the pixel 50a in the first embodiment has no concentration gradient in the Si substrate 70, and a P-type region 72 is formed between the Si substrate 70 and the backside Si interface 75. The pixel 50f in the sixth embodiment has a concentration gradient in the Si substrate 70. The concentration gradient is a concentration gradient in which the P-type impurity concentration on the back surface side (P-type region 111 side) of the substrate is higher than the P-type impurity concentration on the front surface side.

The pixel 50f in the sixth embodiment having such a concentration gradient can further obtain the following effects in addition to the same effects as the pixel 50a of the first embodiment: it is easier to read out the electric charges than the pixel 50a in the first embodiment.

< seventh embodiment >

Fig. 12 is a vertical sectional view of a pixel 50g of a seventh embodiment to which the present technique is applicable.

The pixel 50g of the seventh embodiment differs from the pixel 50a of the first embodiment in that: the thickness of the Si substrate 70 is larger than that of the Si substrate 70 of the pixel 50a, and as the thickness of the Si substrate 70 increases, the DTI82 and the like are formed deeper.

In the pixel 50g of the seventh embodiment, the Si substrate 70g is formed thick. As the Si substrate 70g is formed thicker, the area (volume) of the PD71 g increases, and the DTI82 g is formed deeper. Since the DTI82 g is formed deeper, the P-type solid-phase diffusion layer 83g and the N-type solid-phase diffusion layer 84g are also formed deeper (wider).

Since the P-type solid-phase diffusion layer 83g and the N-type solid-phase diffusion layer 84g are wide, the area of the PN junction region formed by the P-type solid-phase diffusion layer 83g and the N-type solid-phase diffusion layer 84g is large. Therefore, the pixel 50g of the seventh embodiment can obtain the same effects as the pixel 50a of the first embodiment, and can also increase the saturation charge amount Qs as compared with the pixel 50a of the first embodiment.

< eighth embodiment >

Fig. 13 is a vertical sectional view of a pixel 50h of an eighth embodiment to which the present technique is applicable.

As with the pixel 50g of the seventh embodiment shown in fig. 12, the pixel 50h of the eighth embodiment is a pixel in which the length in the depth direction of the Si substrate 70g is extended.

Further, in the pixel 50h, a P-type region 121-1, an N-type region 122, and a P-type region 121-2 are formed on the back side of the PD71 by ion implantation. Since a strong electric field is generated in the PN junction portion formed by P-type region 121-1, N-type region 122, and P-type region 121-2, electric charges can be held.

Therefore, the pixel 50h of the eighth embodiment can obtain the same effect as the pixel 50g of the seventh embodiment, and can also increase the saturation charge amount Qs.

< ninth embodiment >

Fig. 14 is a vertical sectional view of a pixel 50i of a ninth embodiment to which the present technique is applicable.

The pixel 50i of the ninth embodiment differs from the pixel 50a of the first embodiment in that: a MOS capacitor 131 and a pixel transistor (not shown) are formed on the front face side of the Si substrate 70, and the other configuration is the same as that of the pixel 50a in the first embodiment.

In general, even if the saturation charge amount Qs of the PD71 is made large, unless the conversion efficiency is lowered, the output is limited by the amplitude limit of the vertical signal line VSL (the vertical signal line 47 shown in fig. 2), and therefore it is difficult to sufficiently utilize the increased saturation charge amount Qs.

In order to reduce the conversion efficiency of the PD71, it is necessary to add capacitance to the FD 91 (fig. 4). Therefore, the pixel 50i of the ninth embodiment has the following configuration: in which a MOS capacitor 131 is added as a capacitance to be added to the FD 91 (not shown in fig. 14).

The pixel 50i of the ninth embodiment can obtain the same effect as the pixel 50a of the first embodiment, and the pixel 50i can reduce the conversion efficiency of the PD71 and can make full use of the increased saturation charge amount Qs due to the addition of the MOS capacitor 131 to the FD 91.

< tenth embodiment >

Fig. 15 is a vertical sectional view of a pixel 50j of a tenth embodiment to which the present technique is applied.

The pixel 50j of the tenth embodiment is different from the pixel 50a of the first embodiment in that: two contacts 152 are formed in the well contact portion 151 formed in the active region 77, and the contacts 152 are connected to the Cu wiring 153, but the other configuration is the same as that of the pixel 50a of the first embodiment.

As described above, a configuration including the well contact 151 can be adopted. Note that fig. 15 shows an example in which two contacts 152 are formed. However, two or more contacts 152 may be formed in the well contact portion 151.

In addition to obtaining the same effect as the pixel 50a of the first embodiment, the pixel 50j of the tenth embodiment can improve the re-defect generation rate.

< eleventh embodiment >

Fig. 16 is a vertical sectional view and a plan view of a pixel 50k of an eleventh embodiment to which the present technique is applicable.

The pixel 50k of the eleventh embodiment is different from the pixel 50a of the first embodiment in that: a vertical-type transistor trench 81k is opened in the center of the pixel 50k, and a transfer transistor (gate) 80k is formed, while the other configuration is the same as that of the pixel 50a in the first embodiment.

The pixel 50k shown in fig. 16 is formed in the following state: the transfer transistors (gates) 80k are located at positions equidistant from the respective outer peripheries of the PDs 71. Therefore, the pixel 50k of the eleventh embodiment can improve the transfer of electric charges because the transfer transistors (gates) exist at positions equidistant from the respective outer peripheries of the PDs 71, in addition to obtaining the same effects as the pixel 50a of the first embodiment.

< twelfth embodiment >

Fig. 17 is a vertical sectional view and a plan view of a pixel 50m of a twelfth embodiment to which the present technique is applicable.

The pixel 50m of the twelfth embodiment is different from the pixel 50a of the first embodiment in that: the transfer transistor 80m is formed using two vertical-type transistor trenches 81-1 and 81-2, and has a similar configuration in other respects.

The pixel 50a (fig. 3) of the first embodiment has a configuration in which the transfer transistor 80 includes one vertical-type transistor trench 81, while the pixel 50m of the twelfth embodiment has a configuration in which the transfer transistor 80m is formed using two vertical-type transistor trenches 81-1 and 81-2.

As described above, by adopting the configuration in which the two vertical-type transistor trenches 81-1 and 81-2 are provided, the following property of the electric potential of the region sandwiched between the two vertical-type transistor trenches 81-1 and 81-2 when the electric potential of the transfer transistor 80k is changed is improved. Therefore, the modulation degree can be improved. As a result, the charge transfer efficiency can be improved.

Further, the same effect as the pixel 50a of the first embodiment can be obtained.

Note that here, the explanation is given of the transfer transistor 80k by taking an example including two vertical-type transistor trenches 81-1 and 81-2 as an example. However, more than two vertical-type transistor trenches 81 may be formed in each pixel region.

Further, an example in which the two vertical-type transistor trenches 81-1 and 81-2 are formed to have the same size (the same length and thickness) has been described. However, in the case where a plurality of vertical-type transistor trenches 81 are formed, the plurality of vertical-type transistor trenches 81 may be formed to have different sizes. For example, one of the two vertical-type transistor trenches 81-1 and 81-2 may be formed longer than the other or formed thicker than the other.

< thirteenth embodiment >

Fig. 18 is a vertical sectional view of a pixel 50n of a thirteenth embodiment to which the present technique is applicable.

The pixel 50n of the thirteenth embodiment is different from the pixel 50a of the first embodiment in the configuration of the light shielding film 74, and the other configuration is the same as that of the pixel 50a of the first embodiment.

In the pixel 50n of the thirteenth embodiment, a light shielding film 74n-1 and a light shielding film 74n-2 are formed on the upper side and the lower side of the DTI82 n, respectively. In the pixel 50a (fig. 3) of the first embodiment, the light shielding film 74 covering the back surface side (lower side in fig. 3) of the DTI82 is formed, and in the pixel 50n (fig. 18), the inside of the DTI82 n is filled with the same metal material (for example, tungsten) as the light shielding film 74, and the front surface side (upper side in fig. 18) of the Si substrate 70 is also covered with the metal material.

That is, the pixels 50n have a configuration in which each pixel region is surrounded by a metal material except for the rear surface (except for the light incident surface). Note that, in the case where the pixel 50n has a structure in which the pixel is surrounded by a metal material except for the rear surface of the pixel 50n, an opening is appropriately opened in a necessary portion, for example, a portion of the light shielding film 74n-2 where the transfer transistor 80n is provided, so that a terminal for connection to the outside is formed.

Note that a metal material other than tungsten (W) may be used for the light shielding film 74 and the like.

The pixel 50n in the thirteenth embodiment can prevent incident light from leaking into the adjacent pixel 50n, so that color mixing can be suppressed.

Further, light incident from the back surface side but not photoelectrically converted to reach the front surface side can be reflected by the metal material (light shielding film 74n-2) and enter the PD71 again. Therefore, the pixel 50n of the thirteenth embodiment can improve the sensitivity of the PD71, in addition to obtaining the same effect as the pixel 50a of the first embodiment.

< fourteenth embodiment >

Fig. 19 is a vertical sectional view of a pixel 50p of a fourteenth embodiment to which the present technology is applied.

The pixel 50P of the fourteenth embodiment is different from the pixel 50a of the first embodiment in that the shape of the P-type solid-phase diffusion layer 83P and the sidewall film 85P formed on the back surface side is different from that of the first embodiment, and the other configuration is the same as that of the pixel 50a of the first embodiment.

The P-type solid-phase diffusion layer 83P on the back surface side of the pixel 50P is formed in a shape protruding below the N-type solid-phase diffusion layer 84P. The pixel 50P has the P-type solid-phase diffusion layer 83P as follows: which is formed at the end of the P-type region 72P in a shape protruding into the P-type region 72P. The sidewall film 85P formed on the P-type solid-phase diffusion layer 83P is also formed in a shape protruding toward the P-type region 72P. The filler 86P formed in the sidewall film 85P is also formed in a shape protruding toward the P-type region 72P.

With such a shape, the N-type solid phase diffusion layer 84p can be surely kept from contacting the rear surface Si interface 75 of the Si substrate 70. Therefore, the pinning of the electric charges can be prevented from being weakened, and the electric charges can be prevented from flowing into the PD71 and the dark characteristics from being deteriorated.

The depth and concentration of the N-type solid-phase diffusion layer 84p may vary when it is formed. For example, the depth of the N-type solid phase diffusion layer 84 of the a pixel 50 may be formed deeper than the depth of the N-type solid phase diffusion layer 84 of the B pixel 50. In this case, the N-type solid phase diffusion layer 84 formed deeper may reach into the P-type region 72, or may penetrate the P-type region 72 and reach the back surface Si interface 75 of the Si substrate 70.

Further, for example, there is a possibility that the N-type impurity concentration of the N-type solid-phase diffusion layer 84 of the a pixel 50 is formed to be larger than the N-type impurity concentration of the N-type solid-phase diffusion layer 84 of the B pixel 50. In this case, the N-type solid-phase diffusion layer 84 formed to have a greater concentration may reach into the P-type region 72, or may penetrate the P-type region 72 and reach the back surface Si interface 75 of the Si substrate 70.

In the pixel 50P, not only the P-type region 72P but also the P-type solid-phase diffusion layer 83P is formed in a protruding shape protruding to the lower side of the N-type solid-phase diffusion layer 84P on the back surface Si interface 75 side of the N-type solid-phase diffusion layer 84P. Therefore, even if the depth and concentration of the N-type solid phase diffusion layer 84P change, the change can be reliably absorbed, and therefore, the P-type solid phase diffusion layer 83P can prevent the N-type solid phase diffusion layer 84P from coming into contact with the rear surface Si interface 75 of the Si substrate 70.

The pixel 50p of the fourteenth embodiment can obtain the same effects as the pixel 50a of the first embodiment.

< construction for increasing the degree of freedom relating to arrangement of transistors >

As shown in fig. 20, for example, the pixel 50 of any of the first to fourteenth embodiments described above is formed so as to be surrounded by the DTI82 in a plan view. On the side wall of the DTI82, a PN junction region formed by forming the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 is formed, and the PN junction region forms a strong electric field region. Note that, in the above and the following description, it is needless to say that the PN junction region includes a case where the PN junction region is constituted only by the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84, but the PN junction region also includes a case where a depletion layer region exists between the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84.

As shown in fig. 20, the PD71 is surrounded by the N-type solid-phase diffusion layer 84. The N-type solid-phase diffusion layer 84 is surrounded by the P-type solid-phase diffusion layer 83. Further, the P-type solid-phase diffusion layer 83 is surrounded by the DTI 82. Further, as described with reference to fig. 4, a transfer transistor 80, an FD 91, a reset transistor 92, an amplification transistor 93, and a selection transistor 94 are formed in the pixel 50.

When the strong electric field region is formed on the entire surface of the DTI82, the above-described pixel transistor must be arranged in a region surrounded by the strong electric field region. For this reason, the degree of freedom of arrangement of the pixel transistors becomes low, and a region for arranging the pixel transistors may be narrowed. Therefore, as described below, by providing the side edge where the strong electric field region is not formed or the portion where the strong electric field region is thinly formed, the region for arranging the pixel transistor is secured, thereby increasing the degree of freedom in arrangement of the pixel transistor.

Hereinafter, thickness variations (shades) of strong electric field regions will be explained as fifteenth to eighteenth embodiments. Any one of the fifteenth to eighteenth embodiments can be combined with any one of the first to fourteenth embodiments described above.

< fifteenth embodiment >

Fig. 21 is a horizontal sectional view (plan view) of a pixel 50q of a fifteenth embodiment to which the present technique is applicable.

The pixel 50q of the fifteenth embodiment has a configuration in which a strong electric field region surrounding the PD71 is not partially formed. When attention is paid to the PD71-1 included in the pixel 50q by referring to the pixel 50q shown in fig. 21, an intense electric field region is formed on two sides of four sides around the PD71-1, and no intense electric field region is formed on the other two sides.

In this case, a P-type solid phase diffusion layer 83-1 and an N-type solid phase diffusion layer 84-1 are formed in DTI82-1 on the left side of PD71-1 in FIG. 21, and a P-type solid phase diffusion layer 83-2 and an N-type solid phase diffusion layer 84-2 are formed in DTI82-2 on the right side of PD71-1 in FIG. 21. Therefore, strong electric field regions are formed on the left and right sides of the PD71-1 of fig. 21, respectively.

Meanwhile, in DTI82-11 on the upper side of PD71-1 in FIG. 21, an N-type solid phase diffusion layer 84-11 is formed, but a P-type solid phase diffusion layer 83 is not formed. In addition, in DTI82-12 on the lower side of PD71-1 in FIG. 21, an N-type solid phase diffusion layer 84-12 is formed, but a P-type solid phase diffusion layer 83 is not formed. Therefore, strong electric field regions are not formed on the upper and lower sides of the PD71-1 of fig. 21.

By providing the side on which the strong electric field region is not formed in this manner, the pixel transistor (or a part of the pixel transistor) can be arranged on the side, and the region for arranging the pixel transistor becomes wider, so that the degree of freedom relating to the arrangement of the pixel transistor can be improved.

Fig. 21 shows a case where a strong electric field region (which is a region where the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 are formed) is formed on two sides among four sides of one pixel 50q when focusing on the pixel 50 q. However, for example, the present technology can be applied to a case where the strong electric field region is formed on only one side, or can be applied to a case where the strong electric field region is formed on three sides.

For example, as shown in fig. 22, in the case where two pixels 50, which are a pixel 50q-3 including the PD 71-3 and a pixel 50q-1 including the PD71-1 arranged in the vertical direction, share a predetermined transistor, the strong electric field region may not be formed on the side between the pixels as the shared pixel, but may be formed on the other three sides.

In the example shown in fig. 22, DTI82-11 between PD 71-3 and PD71-1 is DTI82-11 where P-type solid-phase diffusion layer 83 is not formed, and therefore, a pixel transistor can be arranged on DTI82-11 or in the vicinity of DTI 82-11.

As shown in fig. 23, a structure in which the P-type solid-phase diffusion layer 83 is not formed in a part of the side of one pixel 50q can be employed. In the example shown in a of fig. 23, a region excluding the P-type solid-phase diffusion layer 83 is formed near the center of the right and left sides of the pixel 50 q.

For example, the P-type solid phase diffusion layer 83-1 on the left side of the PD71-1 has an opening formed in the central portion. Further, the P-type solid-phase diffusion layer 83-2 on the right side of the PD71-1 has an opening formed in the central portion. In this way, a portion where the P-type solid phase diffusion layer 83 is not formed (an opening where the P-type solid phase diffusion layer 83 is provided) can be provided on a predetermined side.

Further, fig. 23 shows a case where portions where the P-type solid-phase diffusion layer 83 is not formed (openings are formed) are formed on two sides among the four sides of the pixel 50 q. However, the above-described opening may be formed in one side, three sides, or four sides among the four sides.

Further, the openings may be formed at the same positions for the adjacent pixels 50q, for example, as shown in a of fig. 23, the openings may be formed all at the central portions of the side edges. Alternatively, the openings may also be formed at different positions for the adjacent pixels 50q, for example, as shown in B of fig. 23, the opening may be formed on the upper side of the P-type solid-phase diffusion layer 83-2 on the right side of the PD71-1, and the opening may also be formed on the lower side of the P-type solid-phase diffusion layer 83-3 on the left side of the PD 71-2.

Further, the number of openings formed in one side may be one or more. Further, the size of one opening can be appropriately set according to the size of a transistor to be arranged or the like.

A method of manufacturing a strong electric field region in each case where a region where the P-type solid-phase diffusion layer 83 is formed and a region where the P-type solid-phase diffusion layer 83 is not formed are provided in the side wall of the DTI82 will be described with reference to fig. 24 and 25.

In step S51 (fig. 24), a substrate for forming the DTI82 is prepared. A silicon oxide film 200 is formed on the substrate, and an insulating film (insulating material) 201 is buried in the formed groove. For example, LP-TEOS is deposited as silicon oxide film 200.

In step S52, a part of the silicon oxide film 200, a part of the insulating film 201, a part of SiN, and a part of the Si substrate 70 are dug out by dry etching. Through step S52, a deep groove (deep trench) is formed. For example, as shown in fig. 21, the shape of the deep trench in a plan view is a lattice shape, and the depth of the deep trench is set to the lower end of the region where the N-type region is to be formed by solid phase diffusion in the subsequent step.

In step S53, a phosphorus (P) -containing silicon oxide film (PSG)202 is deposited on the entire surface of the wafer using an Atomic Layer Deposition (ALD) method. Through the process in step S53, the PSG film 202 is formed on the front surface of the wafer where the deep trench is not formed, the side surface of the deep trench, and the bottom surface of the deep trench. Since phosphorus (P) is used here, the PSG film 202 is formed as an N-type film.

In step S54, a thermal diffusion process is performed. In step S54, the wafer is annealed so that solid phase diffusion of phosphorus (P) occurs from the PSG film 202 to the Si substrate 70 in the region where the PSG film 202 and the Si substrate 70 contact each other. As a result, as shown in step S54, the N-type impurity region 203 is formed. The N-type impurity region 203 is a region serving as the N-type solid-phase diffusion layer 84.

In step S55, the PSG film 202 on the wafer is removed. The removal of the PSG film 202 can be performed by, for example, wet etching using hydrofluoric acid.

In step S56 (fig. 24), the silicon on the bottom surfaces of the deep trenches of the wafer is further excavated by dry etching.

In step S57, a boron (B) -containing silicon oxide film (BSG)204 is deposited on the entire surface of the wafer using the ALD method. Through the process in step S57, the BSG film 204 is formed on the front surface of the wafer where the deep trench is not formed, the side surface of the deep trench, and the bottom surface of the deep trench. Since boron (B) is used here, the BSG film 204 is formed as a P-type film.

The BSG film 204 is a portion which becomes a P-type impurity region and a P-type solid-phase diffusion layer 83 by performing thermal diffusion treatment in subsequent processes. In the case where the portion where the P-type solid phase diffusion layer 83 is formed and the portion where the P-type solid phase diffusion layer 83 is not formed are provided, the thermal diffusion process is performed after the processes in steps S58 to S60 are performed.

In step S58 and thereafter, it will be assumed that the left side in fig. 25 is a portion (side) where the P-type solid phase diffusion layer 83 is formed and the right side in fig. 25 is a portion (side) where the P-type solid phase diffusion layer 83 is not formed, and the description will be continued on this basis.

In step S58, a resist 205 is coated on the entire surface of the wafer. The resist 205 is formed into a film on the surface of the wafer and is filled into the deep trench.

In step S59, the resist 205 applied to the portion corresponding to the portion where the P-type solid-phase diffusion layer 83 is not to be formed is removed. For example, the resist 205 applied to the portion corresponding to the portion where the P-type solid phase diffusion layer 83 is not to be formed is removed by using a mask for the resist 205 applied to the portion corresponding to the portion where the P-type solid phase diffusion layer 83 is not to be formed, exposing the mask to light, and peeling off the mask. In step S59, a process of leaving the resist 205 applied onto a portion corresponding to the portion where the P-type solid-phase diffusion layer 83 is to be formed is performed.

In step S60, the BSG film 204 in the opening of the resist 205 on the wafer (the portion where the resist 205 has been removed in step S59) is removed. The BSG film 204 is removed by wet etching using hydrofluoric acid, for example. After the BSG film 204 is removed, the remaining resist 205 is also peeled off.

In step S61, a thermal diffusion process is performed. In step S61, the wafer is annealed so that solid phase diffusion of boron (B) occurs from the BSG film 204 to the Si substrate 70 in a region where the BSG film 204 and the Si substrate 70 contact each other. As a result, as shown in step S61 in fig. 25, the P-type impurity region 206 is formed. The P-type impurity region 206 is a region serving as the P-type solid-phase diffusion layer 83.

Further, in step S61, the BSG film 204 is removed. The removal of the BSG film 204 may be performed by, for example, wet etching using hydrofluoric acid as in step S60.

In step S62, polysilicon is buried as the filling material 86 in the trench, and unnecessary polysilicon deposited on the upper surface of the wafer is removed. Further, a pixel transistor, a wiring, and the like are also formed. After that, the Si substrate 70 is thinned from the back surface side. The thinning is performed until the bottom of the deep trench is exposed.

In this way, as shown in fig. 21 to 23, a pixel 50q in which a portion in which the P-type solid phase diffusion layer 83 is formed and a portion in which the P-type solid phase diffusion layer 83 is not formed are mixed is formed. The pixel 50q formed as described above can have a configuration in which the N-type solid-phase diffusion layer 84 is not in contact with the back surface Si interface 75 of the Si substrate 70, and therefore, the pinning of charges can be prevented from being weakened, and the charges can be prevented from flowing into the PD71 and the dark characteristics from being deteriorated. Further, the arrangement region of the transistors can be increased, and the degree of freedom relating to the arrangement of the transistors can be improved.

< sixteenth embodiment >

Fig. 26 is a plan view of a pixel 50r of a sixteenth embodiment to which the present technique is applicable.

The pixel 50r of the sixteenth embodiment has a configuration in which a strong electric field region surrounding the PD71 is partially thinned. When focusing on the PD71-1 included in the pixel 50r by referring to the pixel 50r shown in fig. 26, strong electric field regions are formed on four sides around the PD71-1, but the P-type solid-phase diffusion layers 83 formed on the upper and lower both sides are thinner in thickness than the P-type solid-phase diffusion layers 83 formed on the left and right both sides.

In this case, a P-type solid phase diffusion layer 83-1 and an N-type solid phase diffusion layer 84-1 are formed in DTI82-1 on the left side of PD71-1 in FIG. 26, and a P-type solid phase diffusion layer 83-2 and an N-type solid phase diffusion layer 84-2 are formed in DTI82-2 on the right side of PD71-1 in FIG. 26. Therefore, strong electric field regions are formed on the left and right sides of the PD71-1 of fig. 26, respectively.

Meanwhile, in DTI82-11 on the upper side of PD71-1 of FIG. 26, P type solid phase diffusion layer 83-11 and N type solid phase diffusion layer 84-11 are formed, but P type solid phase diffusion layer 83-11 is formed thinner. Further, in DTI82-12 on the lower side of PD71-1 in FIG. 26, P type solid phase diffusion layer 83-12 and N type solid phase diffusion layer 84-12 are formed, but P type solid phase diffusion layer 83-12 is formed thinner.

The N-type solid phase diffusion layers 84-1, 84-2, 84-11, and 84-12 formed on the four sides of the PD71-1 are formed to have substantially the same thickness.

Of the P-type solid-phase diffusion layers 83-1, 83-2, 83-11, and 83-12 formed on the four sides of the PD71-1, the P-type solid-phase diffusion layers 83-1 and 83-2 are formed to have substantially the same thickness, and the P-type solid-phase diffusion layers 83-11 and 83-12 are formed to have substantially the same thickness. Further, the P-type solid phase diffusion layers 83-11 and 83-12 are formed thinner than the P-type solid phase diffusion layers 83-1 and 83-2.

Note that the thickness is thick or thin means that the width of the solid phase diffusion layer is thick or thin in physical quantity, and also means that the concentration of an N-type or P-type impurity is high or low. The following description will be continued on the assumption that the thickness becomes thicker and the impurity concentration becomes higher and the thickness becomes thinner and the impurity concentration becomes lower.

By providing the side on which the strong electric field region is thin in this manner, the pixel transistor (or a part of the pixel transistor) can be arranged on the side, and the region for arranging the pixel transistor becomes wide, so that the degree of freedom relating to the arrangement of the pixel transistor can be improved.

Fig. 26 shows a case where a strong electric field region is thinly formed on two sides out of four sides of one pixel 50r (the P-type solid-phase diffusion layer 83 is thin) when focusing on the pixel 50 r. However, for example, the present technology can be applied to a case where a strong electric field region is thinly formed on one side or three sides.

For example, although not shown, in the case where two pixels in which pixels 50r arranged in the vertical direction share a predetermined transistor are shared as in the pixel 50p shown in fig. 22, an intense electric field region thinner than that on the other sides may be formed on the side between the pixels as the shared pixel.

Further, as shown in fig. 27, a configuration in which a thin P-type solid-phase diffusion layer 83 is formed on a part of the side of one pixel 50r can be employed. In the example shown in a of fig. 27, regions in which the P-type solid-phase diffusion layer 83 is formed to be thin are provided near the centers of the right and left sides of the pixel 50 r. The region having the P-type solid-phase diffusion layer 83 formed thinner is described as a depression.

For example, the P-type solid phase diffusion layer 83-1 on the left side of the PD71-1 has a depression formed in the central portion. Further, the P-type solid phase diffusion layer 83-2 of the right side of the PD71-1 has a depression formed in the central portion. In this way, a portion where the thin P-type solid phase diffusion layer 83 is formed (a depression of the P-type solid phase diffusion layer 83 is provided) can be provided on a predetermined side.

Further, fig. 27 shows a case where portions where the thin P-type solid-phase diffusion layers 83 are formed (depressions are formed) are formed on two sides among the four sides of the pixel 50 r. However, such depressions may be formed in one side, three sides, or four sides among the four sides.

Further, the recesses may be formed at the same positions for the adjacent pixels 50r, for example, as shown in a of fig. 27, the recesses may be formed at the central portions of the side edges. Alternatively, the depressions may be formed at different positions for the adjacent pixels 50r, for example, as shown in B of fig. 27, the depression may be formed at the upper side of the P-type solid phase diffusion layer 83-2 at the right side of the PD71-1, and the depression may be formed at the lower side of the P-type solid phase diffusion layer 83-3 at the left side of the PD 71-2.

Further, the number of the depressions formed in one side may be one or more. Further, for example, the size of one recess can be set appropriately according to the size of a transistor to be arranged.

A manufacturing method of the strong electric field region in the case where the region in which the P-type solid-phase diffusion layer 83 is formed thinner than the predetermined thickness and the region in which the P-type solid-phase diffusion layer 83 is formed to have the predetermined thickness are provided in the side wall of the DTI82 will be described with reference to fig. 28 and 29.

The flow of forming the P-type solid phase diffusion layer 83 after forming the N-type solid phase diffusion layer 84 on the side surface of the DTI82 is the same as the manufacturing flow of the pixel 50q of the fifteenth embodiment. The process up to the formation of the N-type solid phase diffusion layer 84 is the same as the manufacturing process of the pixel 50q of the fifteenth embodiment, and therefore, the description thereof is omitted.

By performing the processing in steps S51 to S56 shown in fig. 24, the N-type impurity region 203 serving as the N-type solid-phase diffusion layer 84 is formed on the side surface of the DTI 82. When the N-type impurity region 203 is formed, a resist 301 is applied to the entire surface of the wafer in step S101 (fig. 28). A resist 301 is formed on the front surface of the wafer and is filled into the deep trench.

In step S101 and thereafter, it will be assumed that the left side of fig. 28 is a portion (side) where the P-type solid phase diffusion layer 83 is formed to have a predetermined thickness, and the right side of fig. 28 is a portion (side) where the P-type solid phase diffusion layer 83 is formed to be thinner than the predetermined thickness, and the description will be continued on this basis.

In step S102, the resist 301 applied to the portion corresponding to the portion where the P-type solid-phase diffusion layer 83 is to be formed thin is removed. For example, the resist 301 applied to the portion corresponding to the portion where the P-type solid phase diffusion layer 83 is to be formed thin is removed by applying a mask to the resist 301 applied to the portion corresponding to the portion where the P-type solid phase diffusion layer 83 is to be formed thin, exposing the mask to light, and peeling off the mask. In step S102, a process of leaving the resist 301 applied to a portion corresponding to a portion where the P-type solid-phase diffusion layer 83 having a predetermined thickness is to be formed is performed.

In step S103, ion implantation is performed on the wafer from a diagonal direction using P-type ions (e.g., phosphorus (P)). By performing implantation from an oblique direction, a portion without the resist 301 can be damaged by the implantation. As shown in step S103 of fig. 28, an implantation damage layer 302 (a portion marked with a cross in fig. 28) is formed on the side surface (the side surface on the right side of fig. 28) and the bottom surface of the deep trench.

In step S104, the resist 301 is stripped, and a boron (B) -containing silicon oxide film (BSG)303 is deposited over the entire surface of the wafer using ALD. Through the process in step S104, the BSG film 303 is formed on the front surface of the wafer where the deep trench is not formed, the side surface of the deep trench (the side surface containing the implant damage layer 302), and the bottom surface of the deep trench (the bottom surface containing the implant damage layer 302). Since boron (B) is used here, the BSG film 303 is formed as a P-type film.

In step S105 (fig. 29), a thermal diffusion process is performed. In step S105, the wafer is annealed so that solid phase diffusion of boron (B) occurs from the BSG film 303 to the Si substrate 70 in a region where the BSG film 303 and the Si substrate 70 contact each other. At this time, boron (B) also solid-phase diffuses into the implantation damage layer 302.

As shown in step S105 of fig. 28, P- type impurity regions 304 and 305 are formed. The P-type impurity region 305 is a region formed in the implantation damage layer 302. The P-type impurity region 304 is a region serving as the P-type solid-phase diffusion layer 83 having a predetermined thickness, and the P-type impurity region 305 is a region serving as the P-type solid-phase diffusion layer 83 thinner than the predetermined thickness.

In step S106, the BSG film 303 is removed. The removal of the BSG film 303 can be performed by, for example, wet etching using hydrofluoric acid. The implantation damage layer 302 is also etched when the BSG film 303 is removed. Therefore, the side walls of the deep trenches shown on the right side of fig. 28 (which are also the Si substrate 70 that has undergone solid phase diffusion) are also etched. That is, P-type impurity region 305 is cut to a small thickness.

In this way, a variation in thickness of the P-type solid-phase diffusion layer 83 can be produced.

In step S107, polysilicon is buried into the trenches as the fill material 86, and unnecessary polysilicon deposited on the upper surface of the wafer is removed. Further, a pixel transistor, a wiring, and the like are also formed. After that, the Si substrate 70 is thinned from the back surface side. This thinning is performed until the bottom of the deep trench is exposed.

In this way, as shown in fig. 26 and 27, the pixel 50r in which the portion in which the P-type solid-phase diffusion layer 83 is formed to have a predetermined thickness and the portion in which the P-type solid-phase diffusion layer 83 is formed to be thinner than the predetermined thickness are mixed is formed. The pixel 50r formed as described above can be configured such that the N-type solid phase diffusion layer 84 does not contact the back surface Si interface 75 of the Si substrate 70, and thus the pinning of charges can be prevented from being weakened, and hence the inflow of charges into the PD71 and the degradation of dark characteristics can be prevented. Further, the arrangement region of the transistors can be widened, and the degree of freedom regarding the arrangement of the transistors can be improved.

< seventeenth embodiment >

Another manufacturing process of the pixel 50r of the sixteenth embodiment described by referring to fig. 26 and 27 will be explained.

In the case of manufacturing the pixel 50r in which the portion in which the P-type solid-phase diffusion layer 83 is formed to have a predetermined thickness and the portion in which the P-type solid-phase diffusion layer 83 is formed to be thinner than the predetermined thickness are mixed, the pixel 50r can be manufactured by the manufacturing process shown in fig. 30.

Even in this case, the flow of forming the P-type solid phase diffusion layer 83 after forming the N-type solid phase diffusion layer 84 on the side surface of the DTI82 is the same as the manufacturing flow of the pixel 50q of the fifteenth embodiment. Therefore, since the processes up to the formation of the N-type solid-phase diffusion layer 84 have been described in the manufacture of the pixel 50q of the fifteenth embodiment, the description thereof is omitted here.

By performing the processing in steps S51 to S56 shown in fig. 24, the N-type impurity region 203 serving as the N-type solid-phase diffusion layer 84 is formed on the side surface of the DTI 82. Further, by performing steps S57 to S61 in fig. 25, the P-type impurity region 206 is formed in a portion where the P-type solid-phase diffusion layer 83 is to be formed to have a predetermined thickness.

The same state as step S61 in fig. 25 is shown in step S151 (fig. 30). In step S151, the P-type impurity region 206 is formed by performing thermal diffusion processing. The P-type impurity region 206 is a region serving as the P-type solid-phase diffusion layer 83 formed to have a predetermined thickness. In step S151, when the P-type impurity region 206 is formed, the BSG film 204 (not shown in fig. 30) is removed.

In step S152, a boron (B) -containing silicon oxide film (BSG)351 is deposited on the entire surface of the wafer using the ALD method. Through the process in step S152, the BSG film 351 is formed on the front surface of the wafer where the deep trench is not formed, the side surface of the deep trench (the side surface of the P-type impurity region 206), and the bottom surface of the deep trench (the bottom surface of the P-type impurity region 206).

In step S153, thermal diffusion processing is performed. In step S153, the wafer is annealed so that solid phase diffusion of boron (B) occurs from the BSG film 351 to the Si substrate 70 in a region where the BSG film 351 and the Si substrate 70 contact each other. At this time, the already formed P-type impurity region 206 is also subjected to solid phase diffusion. Therefore, the thickness of the P-type impurity region 206 becomes thick (concentration becomes high).

Therefore, by performing P-type solid phase diffusion twice, as shown in step S153 in fig. 30, P-type impurity regions 352 and 353 are formed. P-type impurity region 352 is a region where P-type impurity region 206 has been formed in the first P-type impurity region forming process. The P-type impurity region 352 is a region serving as the P-type solid-phase diffusion layer 83 having a predetermined thickness, and the P-type impurity region 353 is a region serving as the P-type solid-phase diffusion layer 83 thinner than the predetermined thickness.

In step S154, polysilicon is buried into the trenches as the fill material 86, and unnecessary polysilicon deposited on the upper surface of the wafer is removed. Further, a pixel transistor, a wiring, and the like are also formed. After that, the Si substrate 70 is thinned from the back surface side. This thinning is performed until the bottom of the deep trench is exposed.

In this way, the pixel 50r in which the portion in which the P-type solid-phase diffusion layer 83 is formed to have a predetermined thickness and the portion in which the P-type solid-phase diffusion layer 83 is formed to be thinner than the predetermined thickness are mixed as shown in fig. 26 and 27 is formed. The pixel 50r formed as described above can be configured in such a manner that the N-type solid-phase diffusion layer 84 does not contact the back surface Si interface 75 of the Si substrate 70, and thus the pinning of charges can be prevented from being weakened, and hence the inflow of charges into the PD71 and the degradation of dark characteristics can be prevented. Further, the arrangement region of the transistors can be widened, and the degree of freedom regarding the arrangement of the transistors can be improved.

< eighteenth embodiment >

Fig. 31 is a plan view of a pixel 50s of an eighteenth embodiment to which the present technique is applied.

The pixel 50r explained with reference to fig. 26 and 27 is an embodiment in which a part of the strong electric field region surrounding the PD71 is formed thin. Specifically, in the above embodiment, the P-type solid phase diffusion layer 83 is formed to be thin, while the N-type solid phase diffusion layer 84 is not formed to be thin.

The pixel 50s of the eighteenth embodiment is similar to the pixel 50r described above in that a part of the strong electric field region surrounding the PD71 is formed thin, but differs in that in the thus formed thin part, both the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 are formed thin.

The pixel 50s of the eighteenth embodiment has a configuration in which a strong electric field region surrounding the PD71 is partially thinned. When attention is paid to the PD71-1 included in the pixel 50s by referring to the pixel 50s shown in fig. 31, strong electric field regions are formed on four sides around the PD71-1, but the P-type solid-phase diffusion layers 83 formed on the upper and lower both sides are thinner than the P-type solid-phase diffusion layers 83 formed on the left and right both sides, and the N-type solid-phase diffusion layers 84 formed on the upper and lower both sides are thinner than the N-type solid-phase diffusion layers 84 formed on the left and right both sides.

In this case, a P-type solid phase diffusion layer 83-1 and an N-type solid phase diffusion layer 84-1 are formed in the DTI82-1 on the left side of the PD71-1 of FIG. 31, and a P-type solid phase diffusion layer 83-2 and an N-type solid phase diffusion layer 84-2 are formed in the DTI82-2 on the right side of the PD71-1 of FIG. 31. Therefore, strong electric field regions are formed on the left and right sides of the PD71-1 of fig. 31, respectively.

Further, in the DTI82-11 on the upper side of the PD71-1 of FIG. 31, the P type solid phase diffusion layer 83-11 and the N type solid phase diffusion layer 84-11 are formed, but both the P type solid phase diffusion layer 83-11 and the N type solid phase diffusion layer 84-11 are formed thin. Further, in DTI82-12 on the lower side of PD71-1 in FIG. 31, P type solid phase diffusion layer 83-12 and N type solid phase diffusion layer 84-12 are formed, but both P type solid phase diffusion layer 83-12 and N type solid phase diffusion layer 84-12 are formed thin.

Of the P-type solid-phase diffusion layers 83-1, 83-2, 83-11, and 83-12 formed on the four sides of the PD71-1, the P-type solid-phase diffusion layers 83-1 and 83-2 are formed to have substantially the same thickness, and the P-type solid-phase diffusion layers 83-11 and 83-12 are formed to have substantially the same thickness. Further, the P-type solid phase diffusion layers 83-11 and 83-12 are formed thinner in thickness than the P-type solid phase diffusion layers 83-1 and 83-2.

Of the N-type solid-phase diffusion layers 84-1, 84-2, 84-11, and 84-12 formed on the four sides of the PD71-1, the N-type solid-phase diffusion layers 84-1 and 84-2 are formed to have substantially the same thickness, and the N-type solid-phase diffusion layers 84-11 and 84-12 are formed to have substantially the same thickness. Further, the N-type solid phase diffusion layers 84-11 and 84-12 are formed thinner in thickness than the N-type solid phase diffusion layers 84-1 and 84-2.

By providing the side on which the strong electric field region is thin in this manner, the pixel transistor (or a part of the pixel transistor) can be arranged on the side, and the region for arranging the pixel transistor becomes wide, so that the degree of freedom relating to the arrangement of the pixel transistor can be improved.

Fig. 31 shows a case where thin strong electric field regions (the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 are thin) are formed on two sides among the four sides of the pixel 50s when focusing on one pixel 50 s. However, the present technology can be applied to a case where a thin strong electric field region is formed on one side or three sides, for example.

For example, although not shown, in the case where two pixels, in which pixels 50s arranged in the vertical direction share a predetermined transistor, are shared as in the pixel 50p shown in fig. 22, a strong electric field region thinner than that on the other side may be formed on the side between the pixels as the shared pixel.

Further, as shown in fig. 32, the following configuration can be adopted: in which the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 are formed thin on a part of the side of one pixel 50 s. In the example shown in fig. 32, regions in which the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 are formed to be thin are provided near the centers of the right and left sides of the pixel 50 s. The region having the P-type solid phase diffusion layer 83 and the N-type solid phase diffusion layer 84 formed thin is described as a depression.

For example, the P-type solid phase diffusion layer 83-1 and the N-type solid phase diffusion layer 84-1 on the left side of the PD71-1 have a depression formed at the central portion. Further, the P-type solid phase diffusion layer 83-2 and the N-type solid phase diffusion layer 84-2 on the right side of the PD71-1 have a depression formed at the central portion. In this way, portions where the P-type solid phase diffusion layer 83 and the N-type solid phase diffusion layer 84 are formed thin can be provided on predetermined sides (recesses of the P-type solid phase diffusion layer 83 and the N-type solid phase diffusion layer 84 are provided).

Further, fig. 32 shows a case where portions (where recesses are formed) where the thin P-type solid-phase diffusion layers 83 and the N-type solid-phase diffusion layers 84 are formed on two sides among the four sides of the pixel 50 s. However, such depressions may be formed in one side, three sides, or four sides among the four sides.

The number of depressions formed in one side may be one or more. Further, for example, the size of one recess can be set appropriately according to the size of a transistor to be arranged.

A manufacturing method of a strong electric field region in the case where a region in which the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 are formed thinner than a predetermined thickness and a region in which the P-type solid-phase diffusion layer 83 and the N-type solid-phase diffusion layer 84 are formed to have a predetermined thickness are provided in the side wall of the DTI82 will be described with reference to fig. 33 and 35. .

Even in this case, the flow of forming the P-type solid phase diffusion layer 83 after forming the N-type solid phase diffusion layer 84 on the side surface of the DTI82 is the same as the manufacturing flow of the pixel 50q of the fifteenth embodiment. When the N-type solid-phase diffusion layer 84 is formed on the side surface of the DTI82, N-type solid-phase diffusion is performed twice. After that, when the P-type solid-phase diffusion layer 83 is formed, P-type solid-phase diffusion is performed twice.

Steps S201 to S203 (fig. 33) are steps including the same processing as steps S51 to S53 in fig. 24. That is, in step S201, a substrate for forming the DTI82 is prepared. A silicon oxide film 200 is formed on the substrate, and an insulating film (insulating material) 201 is buried in the formed groove. For example, LP-TEOS is deposited as silicon oxide film 200.

In step S202, a part of the silicon oxide film 200, a part of the insulating film 201, a part of SiN, and a part of the Si substrate 70 are dug out by dry etching. Through step S202, a deep groove (deep trench) is formed.

In step S203, a silicon oxide film (PSG)202 containing phosphorus (P) is deposited on the entire surface of the wafer using the ALD method. Since phosphorus (P) is used here, the PSG film 202 is formed as an N-type film.

In step S204, a process of leaving the resist 401 applied to a portion corresponding to a portion where the N-type solid-phase diffusion layer 84 of a predetermined thickness is to be formed is performed. In step S204 and thereafter, it will be assumed that the left side of fig. 33 is a portion (side) in which the N-type solid phase diffusion layer 84 and the P-type solid phase diffusion layer 83 are formed to have a predetermined thickness and the right side of fig. 33 is a portion (side) in which the N-type solid phase diffusion layer 84 and the P-type solid phase diffusion layer 83 are formed to be thinner than the predetermined thickness, on the basis of which the description is continued.

Step S204 in fig. 33 shows a state where the resist 401 is left. For example, the same steps as steps S101 and S102 in fig. 28 are performed so that the resist 401 in the portion corresponding to the portion where the N-type solid-phase diffusion layer 84 is to be formed with a predetermined thickness is left.

A resist 401 is first applied to the entire surface of the wafer, a mask is used on the resist 401, the mask is exposed to light and then peeled off, whereby the resist 401 applied to a portion corresponding to a portion where the thin N-type solid phase diffusion layer 84 is to be formed is removed, whereby the resist 401 applied to a portion corresponding to a portion where the N-type solid phase diffusion layer 84 of a predetermined thickness is to be formed is left.

Further, in step S204, the PSG film 202 is removed except for the portion covered with the resist 401. The removal of the PSG film 202 can be performed by, for example, wet etching using hydrofluoric acid. By this process, the PSG film 202 other than the PSG film 202 covered with the resist 401 is removed.

In step S205, the resist 401 is removed, and thermal diffusion treatment is performed, so that solid phase diffusion of phosphorus (P) occurs from the PSG film 202 to the Si substrate 70 in a region where the PSG film 202 and the Si substrate 70 are in contact, and the N-type impurity region 203 is formed. The N-type impurity region 203 is a region serving as the N-type solid-phase diffusion layer 84 having a predetermined thickness.

In step S206 (fig. 34), the PSG film 202 remaining on the wafer is removed. The removal of the PSG film 202 can be performed by, for example, wet etching using hydrofluoric acid.

In step S207, a silicon oxide film (PSG)402 containing phosphorus (P) is deposited on the entire surface of the wafer using the ALD method.

In step S208, a thermal diffusion process is performed so that solid phase diffusion of phosphorus (P) occurs from the PSG film 402 to the Si substrate 70 in a region where the PSG film 402 and the Si substrate 70 contact each other. At this time, the N-type impurity region 203 which has been formed is also subjected to solid phase diffusion. Therefore, the thickness of the N-type impurity region 203 becomes thick (the concentration becomes high).

Therefore, by performing N-type solid phase diffusion twice, as shown in step S209 in fig. 34, N-type impurity regions 403 and 404 are formed. The N-type impurity region 403 is a region where the N-type impurity region 203 has been formed in the first N-type impurity region forming process. The N-type impurity region 403 is a region serving as the N-type solid-phase diffusion layer 84 having a predetermined thickness, and the N-type impurity region 404 is a region serving as the N-type solid-phase diffusion layer 84 thinner than the predetermined thickness.

Next, a portion serving as the P-type solid-phase diffusion layer 83 is formed. The P-type solid-phase diffusion layer 83 is also formed by performing P-type solid-phase diffusion twice. By performing solid-phase diffusion twice, the process for forming the P-type solid-phase diffusion layer 83 can be performed similarly to the case described with reference to fig. 30.

In step S210, a boron (B) -containing silicon oxide film (BSG)412 is deposited on the entire surface of the wafer using the ALD method. Further, in step S210, a process of leaving the resist 411 applied to a portion corresponding to a portion where the P-type solid-phase diffusion layer 83 of a predetermined thickness is to be formed is performed.

Step S210 in fig. 34 shows a state where the resist 411 is left. For example, as in step S204, a resist 411 is applied to the entire surface of the wafer, a mask is used on the resist 411, and the mask is exposed to light and then peeled off, thereby removing the resist 411 applied to a portion corresponding to a portion where the thin P-type solid phase diffusion layer 83 is to be formed, and therefore, the resist 411 applied to a portion corresponding to a portion where the P-type solid phase diffusion layer 83 of a predetermined thickness is to be formed is left.

In step S211 (fig. 35), the BSG film 412 except for the portion covered with the resist 411 is removed. The removal of the BSG film 412 can be performed by, for example, wet etching using hydrofluoric acid. By this process, the BSG film 412 is removed except that the BSG film 412 is covered with the resist 411.

In step S212, the P-type impurity region 413 is formed by performing thermal diffusion treatment. The P-type impurity region 413 is a region serving as the P-type solid-phase diffusion layer 83 having a predetermined thickness. In step S212, when the P-type impurity region 413 is formed, the BSG film 412 is removed.

In step S213, a second P-type impurity region is formed. A boron (B) -containing silicon oxide film (BSG)414 is deposited on the entire surface of the wafer using an ALD method. Then, in step S214, a thermal diffusion process is performed. At this time, the already formed P-type impurity region 413 is also subjected to solid phase diffusion. Therefore, the thickness of P-type impurity region 413 becomes thick (concentration becomes high).

Therefore, the P- type impurity regions 415 and 416 are formed by performing P-type solid-phase diffusion twice. P-type impurity region 415 is a region in which P-type impurity region 413 has been formed in the first P-type impurity region forming process. The P-type impurity region 415 is a region serving as the P-type solid-phase diffusion layer 83 having a predetermined thickness, and the P-type impurity region 416 is a region serving as the P-type solid-phase diffusion layer 83 thinner than the predetermined thickness.

In step S215, polysilicon as the filling material 86 is buried in the trench, and unnecessary polysilicon deposited on the upper surface of the wafer is removed. Further, a pixel transistor, a wiring, and the like are also formed. After that, the Si substrate 70 is thinned from the back surface side. The thinning is performed until the bottom of the deep trench is exposed.

In this way, the pixel 50s having the depressions formed in the P-type solid phase diffusion layer 83 and the N-type solid phase diffusion layer 84 as shown in fig. 31 and 32 is formed. The pixel 50s formed as described above can be configured in such a manner that the N-type solid-phase diffusion layer 84 does not contact the back surface Si interface 75 of the Si substrate 70, and thus the pinning of charges can be prevented from being weakened, and the charges can be prevented from flowing into the PD71 and the dark characteristics from being deteriorated. Further, the arrangement region of the transistors can be widened, and the degree of freedom regarding the arrangement of the transistors can be improved.

< example of application of endoscopic surgery System >

Further, for example, the technique according to the present disclosure (present technique) may be applied to an endoscopic surgery system.

Fig. 36 is a diagram showing a schematic configuration example of an endoscopic surgery system to which the technique according to the present disclosure (present technique) is applied.

Fig. 36 shows a case where an operator (doctor) 11131 is performing an operation on a patient 11132 on a bed 11133 using an endoscopic surgery system 11000. As shown in fig. 36, the endoscopic surgery system 11000 includes: an endoscope 11100; other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment tool 11112; a support arm device 11120 for supporting the endoscope 11100; and a cart 11200 on which various devices for endoscopic surgery are mounted.

The endoscope 11100 includes a lens barrel (lens-barrel)11101 and a camera 11102. A region having a predetermined length from the distal end of the lens barrel 11101 is inserted into a body cavity of the patient 11132. The camera 11102 is connected to the proximal end of the lens barrel 11101. Fig. 36 shows an endoscope 11100 configured as a so-called hard endoscope including a hard barrel 11101. However, the endoscope 11100 may also be configured as a so-called soft endoscope including a soft lens barrel.

At the distal end of the lens barrel 11101, an opening portion is provided in which an objective lens is fitted. The light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the distal end of the lens barrel 11101 through a light guide member extending inside the lens barrel 11101, and the observation target in the body cavity of the patient 11132 is irradiated with the light through the above-described objective lens. Note that the endoscope 11100 may be a forward-looking endoscope (forward-viewing endoscope), may be an oblique-viewing endoscope (oblique-viewing endoscope), or may be a side-viewing endoscope (side-viewing endoscope).

An optical system and an image pickup element are provided inside the camera 11102, and reflected light (observation light) from an observation target is condensed onto the image pickup element by the optical system. Observation light is photoelectrically converted by the image pickup element, and an electric signal corresponding to the observation light, in other words, an image signal corresponding to an observation image is generated. The image signal is sent as raw data to a Camera Control Unit (CCU) 11201.

The CCU11201 includes a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and the like, and generally controls the operations of the endoscope 11100 and the display device 11202. Further, the CCU11201 receives an image signal from the camera 11102, and performs various image processes such as a development process (demosaicing process) on the image signal to cause an image based on the image signal to be displayed.

Under the control of the CCU11201, the display device 11202 displays an image based on the image signal subjected to the image processing by the CCU 11201.

The light source device 11203 includes a light source such as a Light Emitting Diode (LED), for example, and supplies irradiation light to the endoscope 11100 when photographing a surgical site or the like.

The input device 11204 is an input interface of the endoscopic surgical system 11000. The user can input various information and instructions to the endoscopic surgery system 11000 through the input device 11204. For example, the user can input an instruction or the like for changing the imaging conditions (the type, magnification, focal length, and the like of the irradiation light) of the endoscope 11100.

Treatment tool control device 11205 controls the driving of energy treatment tool 11112 for cauterizing or incising tissue, and for sealing blood vessels, etc. The pneumoperitoneum device 11206 delivers gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to enlarge the body cavity, thereby ensuring the field of view of the endoscope 11100 and ensuring the working space of the operator. The recorder 11207 is a device capable of recording various information relating to the operation. The printer 11208 is a device capable of printing various information related to the operation in various formats (e.g., text, images, and diagrams).

Note that, for example, the light source device 11203 that supplies irradiation light to the endoscope 11100 at the time of imaging the surgical site can be configured by a white light source, which can be configured by an LED, a laser light source, or a combination of an LED and a laser light source. In the case where the white light source is constituted by a combination of RGB laser light sources, the output intensity and the output timing of each color (each wavelength) can be controlled with high accuracy. Therefore, the light source device 11203 can adjust the white balance of the captured image. Further, in this case, the observation target is irradiated with the laser light from each of the RGB laser light sources in a time-division manner, and the driving of the image pickup element of the camera 11102 is controlled in synchronization with the irradiation timing, so that images corresponding to R, G and B, respectively, can be captured in a time-division manner. According to this method, a color image can be obtained without providing a color filter for the image pickup element.

Further, the driving of the light source device 11203 may be controlled to change the light intensity to be output every predetermined time. Driving of the image pickup element of the camera 11102 is controlled in synchronization with the timing of change in light intensity and images are acquired in a time-division manner and synthesized, whereby a high dynamic range image free from so-called ghost black (clipped black) and halation highlight (flaredhigh) can be produced.

Further, the light source device 11203 may be configured to be able to provide light of a predetermined wavelength band corresponding to a special light observation. In special light observation, for example, so-called Narrow Band Imaging (NBI: Narrow Band Imaging) is performed by irradiating Band light narrower than irradiation light at the time of ordinary observation (in other words, white light) and photographing a predetermined tissue such as blood vessels in a mucosal surface layer with high contrast, utilizing the wavelength dependence of light absorption of human tissue. Alternatively, in the special light observation, an image may be obtained by fluorescence generated by irradiation with excitation light, thereby performing fluorescence imaging. In fluorescence imaging, for example, the following operations can be performed: a fluorescence image is obtained by irradiating human tissue with excitation light to observe fluorescence from the human tissue (autofluorescence observation), or injecting a reagent such as indocyanine green (ICG: indocyanine green) into the human tissue and irradiating the human tissue with excitation light corresponding to a fluorescence wavelength of the reagent. The light source device 11203 may be configured to provide narrow-band light and/or excitation light corresponding to such special light observations.

Fig. 37 is a block diagram showing an example of the functional configuration of the camera 11102 and the CCU11201 shown in fig. 36.

The camera 11102 includes a lens unit 11401, an image pickup unit 11402, a drive unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU11201 are communicably connected to each other by a transmission cable 11400.

The lens unit 11401 is an optical system, which is provided at a connecting portion between the camera 11102 and the lens barrel 11101. Observation light introduced from the distal end of the lens barrel 11101 is guided to the camera 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of a plurality of lenses (including a zoom lens and a focus lens).

The image pickup element constituting the image pickup unit 11402 may be one image pickup element (so-called monolithic image pickup element) or may be a plurality of image pickup elements (so-called multi-chip image pickup element). For example, in the case where the image pickup unit 11402 is configured of a multi-sheet type image pickup element, a color image can be obtained by generating image signals corresponding to R, G and B, respectively, by the respective image pickup elements and synthesizing the image signals. Alternatively, the image pickup unit 11402 may be configured by a pair of image pickup elements for acquiring an image signal for the right eye and an image signal for the left eye corresponding to three-dimensional (3D) display, respectively. With the 3D display, the operator 11131 can grasp the depth of the biological tissue in the surgical site more accurately. Note that in the case where the image pickup unit 11402 is configured by a multi-chip image pickup element, a plurality of systems of the lens unit 11401 may be provided corresponding to each image pickup element.

Further, the image pickup unit 11402 is not necessarily provided in the camera 11102. For example, the image pickup unit 11402 may be disposed inside the lens barrel 11101 and immediately behind the objective lens.

The driving unit 11403 is constituted by an actuator, and the driving unit 11403 moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control unit 11405. With this movement, the magnification and focus of the captured image of the image pickup unit 11402 can be appropriately adjusted.

A communication unit 11404 is constituted by a communication device for transmitting various information to the CCU11201 or receiving various information from the CCU 11201. The communication unit 11404 transmits an image signal obtained from the image pickup unit 11402 to the CCU11201 as RAW (RAW) data through the transmission cable 11400.

Further, the communication unit 11404 receives a control signal for controlling driving of the camera 11102 from the CCU11201, and supplies the control signal to the camera control unit 11405. For example, the control signal includes information related to the imaging conditions, such as: information for specifying the frame rate of a captured image, information for specifying the exposure value at the time of image capturing, and/or information for specifying the magnification and focus of a captured image, and the like.

Note that the above-described image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU11201 based on the acquired image signal. In the latter case, a so-called Auto Exposure (AE) function, Auto Focus (AF) function, and Auto White Balance (AWB) function are included in the endoscope 11100.

The camera control unit 11405 controls driving of the camera 11102 based on a control signal from the CCU11201 received through the communication unit 11404.

The communication unit 11411 is constituted by a communication device for transmitting and receiving various information to and from the camera 11102. The communication unit 11411 receives an image signal transmitted from the camera 11102 through the transmission cable 11400.

Further, the communication unit 11411 transmits a control signal for controlling driving of the camera 11102 to the camera 11102. The image signal and the control signal may be transmitted by electrical communication, optical communication, or the like.

The image processing unit 11412 performs various image processes on the image signal transmitted from the camera 11102 as raw data.

The control unit 11413 executes various controls related to imaging of a surgical site or the like by the endoscope 11100 and display of a captured image obtained by imaging of the surgical site or the like. For example, the control unit 11413 generates a control signal for controlling driving of the camera 11102.

Further, based on the image signal on which the image processing unit 11412 has performed the image processing, the control unit 11413 displays the captured image of the surgical site or the like on the display device 11202. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition techniques. For example, the control unit 11413 can recognize a surgical instrument such as forceps, a specific biological site, bleeding, mist when the energy treatment tool 11112 is used, or the like by detecting the shape, color, or the like of the edge of an object included in a captured image. When the control unit 11413 displays the captured image on the display device 11202, the control unit 11413 may superimpose and display various kinds of operation assistance information on the image of the surgical site using the recognition result. By the superimposition and display of the operation assistance information and the presentation to the operator 11131, the burden on the operator 11131 can be reduced, and the operator 11131 can surely perform an operation.

The transmission cable 11400 connecting the camera 11102 and the CCU11201 together is an electric signal cable corresponding to communication of electric signals, an optical fiber corresponding to optical communication, or a composite cable of an electric signal cable and an optical fiber.

Here, in the example shown, the communication has been performed in a wired manner using the transmission cable 11400. However, communication between the camera 11102 and the CCU11201 may also be performed in a wireless manner.

Note that the endoscopic surgical system has been described here as an example. However, for example, the technique according to the present disclosure may also be applied to a microscope surgery or the like.

< application example of Mobile body >

Further, for example, the technology according to the present disclosure may be implemented as an apparatus mounted on any type of moving body including: automobiles, electric cars, hybrid cars, motorcycles, bicycles, personal mobile devices, airplanes, unmanned planes, boats, robots, and the like.

Fig. 38 is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technique according to the present disclosure is applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in fig. 38, the vehicle control system 12000 includes: a drive system control unit 12010, a vehicle body system control unit 12020, a vehicle exterior information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound image output unit 12052, and a vehicle-mounted network Interface (I/F: Interface)12053 are shown.

The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device of each of the following devices: a driving force generation device such as an internal combustion engine or a drive motor for generating a driving force of the vehicle; a driving force transmission mechanism for transmitting a driving force to a wheel; a steering mechanism for adjusting a steering angle of the vehicle; and a brake apparatus for generating a braking force of the vehicle, and the like.

The vehicle body system control unit 12020 controls the operations of various devices mounted on the vehicle body according to various programs. For example, the vehicle body system control unit 12020 functions as a control device for each of the following devices: a keyless entry system; a smart key system; a power window device; and various lamps such as front lamps, rear lamps, brake lamps, turn signal lamps, and fog lamps. In this case, a radio wave transmitted from the mobile device in place of the key or a signal of various switches can be input to the vehicle body system control unit 12020. The vehicle body system control unit 12020 receives input of these radio waves or signals, and controls the door lock device, the power window device, the lamp, and the like of the vehicle.

Vehicle exterior information detection section 12030 detects information on the exterior of the vehicle to which vehicle control system 12000 is attached. For example, the imaging unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the outside of the vehicle, and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing on a pedestrian, a vehicle, an obstacle, a sign, or characters on the road surface, or the like.

The image pickup unit 12031 is an optical sensor for receiving light and outputting an electric signal according to a light-receiving amount of the light. The imaging unit 12031 can output the electrical signal as an image and can output the electrical signal as distance measurement information. Further, the light received by the image pickup unit 12031 may be visible light, or may be non-visible light such as infrared light.

The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 for detecting the state of the driver is connected to the in-vehicle information detection unit 12040. For example, the driver state detection unit 12041 includes a camera for photographing the driver, and based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver, or may determine whether the driver is asleep.

The microcomputer 12051 calculates a control target value of the driving force generation device, the steering mechanism, or the brake device based on the vehicle external and internal information acquired in the vehicle external information detection unit 12030 or the vehicle internal information detection unit 12040, and is able to output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can execute cooperative control for realizing Advanced Driver Assistance System (ADAS) functions including: collision avoidance or collision mitigation of the vehicle, follow-up running based on a vehicle pitch, vehicle speed maintenance running, collision warning of the vehicle, lane departure warning of the vehicle, and the like.

Further, the microcomputer 12051 controls the driving force generation device, the steering mechanism, the brake device, or the like based on the information in the vicinity of the vehicle acquired in the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, thereby executing cooperative control for automatic driving or the like that autonomously travels without depending on the operation of the driver.

Further, the microcomputer 12051 can output a control command to the vehicle body system control unit 12020 based on the information outside the vehicle acquired in the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control for realizing no glare by, for example, controlling headlights and switching from high beams to low beams in accordance with the position of a preceding vehicle or an oncoming vehicle detected in the vehicle exterior information detecting unit 12030.

The sound-image output unit 12052 transmits an output signal of at least one of sound or image to an output device capable of visually and aurally notifying a passenger on the vehicle or the outside of the vehicle of information. In the example of fig. 38, as output devices, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplarily shown. For example, the display unit 12062 may include at least one of an on-board display (on-board display) or a head-up display (head-up display).

Fig. 39 is a diagram illustrating an example of the mounting position of the imaging unit 12031.

In fig. 39, as the image pickup unit 12031, image pickup units 12101, 12102, 12103, 12104, and 12105 are included.

For example, the image pickup units 12101, 12102, 12103, 12104, and 12105 are disposed at the following positions: such as the nose, side mirrors, rear bumper, trunk door, and the upper portion of the windshield in the vehicle cabin of vehicle 12100. The camera unit 12101 provided on the nose and the camera unit 12105 provided on the upper portion of the windshield in the vehicle compartment mainly acquire a front image of the vehicle 12100. The camera units 12102 and 12103 provided on the side mirrors mainly acquire side images of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or the trunk door mainly acquires a rear image of the vehicle 12100. The camera unit 12105 provided on the upper portion of the windshield in the vehicle compartment is mainly used to detect a preceding vehicle, a pedestrian, an obstacle, a traffic signal, a traffic sign, a lane, or the like.

Note that fig. 39 shows an example of the shooting ranges of the image pickup units 12101 to 12104. An imaging range 12111 represents an imaging range of the imaging unit 12101 provided on the nose, imaging ranges 12112 and 12113 represent imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and an imaging range 12114 represents an imaging range of the imaging unit 12104 provided on the rear bumper or the trunk door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's eye view image of the vehicle 12100 viewed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera including a plurality of image sensors, or may be an imaging element having pixels for phase difference detection.

For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 obtains the distances from the respective three-dimensional objects within the imaging ranges 12111 to 12114 and the changes in the distances with time (relative speed with respect to the vehicle 12100), thereby extracting, as the preceding vehicle, the three-dimensional object that is closest to the vehicle 12100, especially on the traveling road, and that travels at a predetermined speed (for example, greater than or equal to 0km/h) in substantially the same direction as the vehicle 12100. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured from the preceding vehicle in advance, and can execute automatic braking control (including following stop control), automatic acceleration control (including following start control), and the like. In this way, it is possible to execute cooperative control for the purpose of realizing automatic driving or the like for autonomous traveling without depending on the operation of the driver.

For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 classifies three-dimensional object data relating to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles for extraction, and can use these data to automatically avoid obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles visually recognizable by the driver of the vehicle 12100 and obstacles visually unrecognizable by the driver. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle, and in the case where the collision risk is greater than or equal to the set value and there is a possibility of collision, the microcomputer 12051 can output a warning to the driver through the audio speaker 12061 or the display unit 12062, and perform forced deceleration or avoidance steering through the drive system control unit 12010 to perform driving assistance for avoiding collision.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 determines whether or not a pedestrian is present in the captured images of the image capturing units 12101 to 12104, thereby identifying the pedestrian. Such identification of pedestrians is performed, for example, by the following procedure: a process of extracting feature points in a captured image of the imaging units 12101 to 12104 as the infrared cameras; and a process of performing pattern matching processing on a series of feature points representing the outline of the object and determining whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the image capturing units 12101 to 12104 and recognizes the pedestrian, the sound image output unit 12052 causes the display unit 12062 to display a rectangular outline for emphasis superimposed on the recognized pedestrian. Further, the sound-image output unit 12052 may also cause the display unit 12062 to display an icon or the like representing a pedestrian at a desired position.

Note that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

The present technology can also have the following configuration.

(1) A solid-state image pickup device comprising:

a photoelectric conversion unit configured to perform photoelectric conversion;

a trench penetrating the semiconductor substrate in a depth direction and formed between the photoelectric conversion units respectively formed in adjacent pixels; and

a PN junction region composed of a P-type region and an N-type region on a sidewall of the trench,

wherein a part of the side around the photoelectric conversion unit includes: a region where the P-type region is not formed or a region where the P-type region is thinly formed.

(2) The solid-state image pickup device according to (1),

the PN junction region is formed on at least one of four sides around the photoelectric conversion unit, and the P-type region is not formed on the remaining sides.

(3) The solid-state image pickup device according to (1),

the P-type region for forming the PN junction region is formed to be thinner in thickness than the other P-type regions on at least one of four sides around the photoelectric conversion unit.

(4) The solid-state image pickup device according to (1),

in a part of the side around the photoelectric conversion unit, the P-type region for forming the PN junction region is formed to be thinner in thickness than the other P-type regions.

(5) The solid-state image pickup device according to (1),

in a part of the side around the photoelectric conversion unit, the PN junction region is formed to be thinner in thickness than the other PN junction regions.

(6) The solid-state image pickup device according to any one of (1) to (5),

the P-type region and the N-type region are solid phase diffusion layers.

(7) An electronic apparatus in which a solid-state image pickup device is mounted,

the solid-state image pickup device includes:

a photoelectric conversion unit configured to perform photoelectric conversion;

a trench penetrating the semiconductor substrate in a depth direction and formed between the photoelectric conversion units respectively formed in adjacent pixels; and

a PN junction region composed of a P-type region and an N-type region on a sidewall of the trench,

wherein a part of the side around the photoelectric conversion unit includes: a region where the P-type region is not formed or a region where the P-type region is thinly formed.

List of reference numerals

10 image pickup device

11 lens system

12 image pickup element

13 DSP circuit

14 frame memory

15 display unit

16 recording unit

17 operating system

18 power supply system

19 bus

20 CPU

31 pixel

33 vertical signal line

41 pixel array unit

42 vertical drive unit

43 columns of processing units

44 horizontal driving unit

45 system control unit

46 pixel drive line

47 vertical signal line

48 signal processing unit

49 data storage unit

50 pixels

70 Si substrate

72P type region

73 planarizing film

74 light-shielding film

75 back side Si interface

77 active region

79 wiring layer

80 pass transistor

81 vertical transistor trench

83P type solid phase diffusion layer

84N type solid phase diffusion layer

85 side wall film

86 filler material

92 reset transistor

93 amplifying transistor

94 select transistor

101 film

121P type region

122N type region

131 MOS capacitor

151 well contact

152 contact member

153 Cu wiring

200 silicon oxide film

201 insulating film

202 PSG (phosphosilicate glass) film

203 impurity region

204 BSG (borosilicate glass) film

205 resist

206 impurity region

301 resist

302 injection of damaged layer

303 BSG film