阅读说明：本技术 耦合型场效应晶体管 (Coupled field effect transistor ) 是由 井野户秀和 高田修 寺田直纯 北原宏良 于 2019-06-11 设计创作，主要内容包括：实施方式提供的能够降低噪声的耦合型场效应晶体管具备：第1导电型的第1半导体层；元件分离绝缘体,设置于第1半导体层的上层部分,划分出有源区域；第2半导体层,设置于有源区域内的第1半导体层上,为第2导电型,且第1方向的端部从元件分离绝缘体分离；源极层,设置于第2半导体层上,为第2导电型,杂质浓度比第2半导体层的杂质浓度高；漏极层,设置于第2半导体层上,在与第1方向交叉的第2方向上从源极层分离,为第2导电型,杂质浓度比第2半导体层的杂质浓度高；以及栅极层,设置于第2半导体层上,配置于源极层与漏极层之间,从源极层及漏极层分离,为第1导电型。(The embodiment provides a coupling type field effect transistor capable of reducing noise, which comprises: a 1 st semiconductor layer of a 1 st conductivity type; an element isolation insulator provided in an upper layer portion of the 1 st semiconductor layer and defining an active region; a 2 nd semiconductor layer of a 2 nd conductivity type provided on the 1 st semiconductor layer in the active region, and having an end portion in a 1 st direction separated from the element isolation insulator; a source layer of a 2 nd conductivity type provided on the 2 nd semiconductor layer and having an impurity concentration higher than that of the 2 nd semiconductor layer; a drain layer of the 2 nd conductivity type provided on the 2 nd semiconductor layer, separated from the source layer in a 2 nd direction intersecting the 1 st direction, and having an impurity concentration higher than that of the 2 nd semiconductor layer; and a gate layer of 1 st conductivity type disposed on the 2 nd semiconductor layer and separated from the source layer and the drain layer, and disposed between the source layer and the drain layer.)

1. A coupling type field effect transistor is provided with:

a 1 st semiconductor layer of a 1 st conductivity type;

an element isolation insulator provided in an upper portion of the 1 st semiconductor layer and defining an active region;

a 2 nd semiconductor layer of a 2 nd conductivity type provided on the 1 st semiconductor layer in the active region, and having a 1 st direction end separated from the element isolation insulator;

a source layer of the 2 nd conductivity type provided on the 2 nd semiconductor layer, the source layer having an impurity concentration higher than that of the 2 nd semiconductor layer;

a drain layer provided on the 2 nd semiconductor layer, separated from the source layer in a 2 nd direction intersecting the 1 st direction, having the 2 nd conductivity type, and having an impurity concentration higher than that of the 2 nd semiconductor layer; and

and a gate layer of the 1 st conductivity type provided on the 2 nd semiconductor layer, disposed between the source layer and the drain layer, and separated from the source layer and the drain layer.

2. The coupled field effect transistor of claim 1,

an end portion of the gate layer in the 1 st direction is in contact with the 1 st semiconductor layer.

3. The coupled field effect transistor of claim 1 or 2,

the source layer, the drain layer and the gate layer extend in the 1 st direction.

4. The coupled field effect transistor of claim 1 or 2,

self-aligned silicide layers are formed on the upper surfaces of the source layer, the drain layer and the gate layer, respectively.

5. The coupled field effect transistor according to claim 1 or 2, further comprising:

a 3 rd semiconductor layer which is disposed on the 2 nd semiconductor layer, is of the 1 st conductivity type between the source layer and the gate layer, and has an impurity concentration lower than that of the gate layer; and

and a 4 th semiconductor layer which is disposed on the 2 nd semiconductor layer between the drain layer and the gate layer, has the 1 st conductivity type, and has an impurity concentration lower than that of the gate layer.

6. The coupled field effect transistor of claim 5,

a lower surface of the 3 rd semiconductor layer is located above a lower surface of the gate layer,

the lower surface of the 4 th semiconductor layer is located above the lower surface of the gate layer.

Technical Field

Background

Conventionally, a coupling type field effect transistor (JFET) has been developed. The JFET is used, for example, as an element for converting the output voltage of the sensor into a constant current. With the increase in sensitivity of sensors, it is desired to reduce noise of JFETs.

Disclosure of Invention

Drawings

Fig. 1 is a plan view showing a coupling type field effect transistor according to embodiment 1.

Fig. 2A is a sectional view taken along line a-a 'of fig. 1, and fig. 2B is a sectional view taken along line B-B' of fig. 1.

Fig. 3 is a cross-sectional view taken along line C-C' of fig. 1.

Fig. 4 is a cross-sectional view showing a coupling type field effect transistor according to embodiment 1.

Embodiments relate to a coupled field effect transistor.