Semiconductor device with dual work function gate structure

文档序号：1158077 发布日期：2020-09-15 浏览：8次中文

阅读说明：本技术 具有双功函数栅极结构的半导体器件 (Semiconductor device with dual work function gate structure ) 是由吴泰京李振烈金银贞金东洙于 2015-09-02 设计创作，主要内容包括：一种半导体器件,包括：衬底,沟槽形成在衬底中；第一杂质区和第二杂质区,形成在衬底中,通过沟槽彼此分开；栅电极,形成为填充沟槽的下部；以及覆盖层,形成在栅电极之上以填充沟槽的上部。栅电极包括：第一功函数内衬,形成在沟槽的下部的底表面和侧壁之上,与第一杂质区和第二杂质区不重叠,且包括含铝金属氮化物；以及第二功函数内衬,形成在沟槽的下部的在第一功函数内衬之上的侧壁之上,与第一杂质区和第二杂质区重叠,且包括含硅非金属材料。(A semiconductor device, comprising: a substrate in which a trench is formed; a first impurity region and a second impurity region formed in the substrate, separated from each other by a trench; a gate electrode formed to fill a lower portion of the trench; and a capping layer formed over the gate electrode to fill an upper portion of the trench. The gate electrode includes: a first work function liner formed on a bottom surface and sidewalls of a lower portion of the trench, not overlapping the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; and a second work function liner formed on a sidewall of a lower portion of the trench above the first work function liner, overlapping the first impurity region and the second impurity region, and including a silicon-containing nonmetal material.)

1. A semiconductor device, comprising:

a substrate in which a trench is formed;

a first impurity region and a second impurity region formed in the substrate, separated from each other by a trench;

a gate electrode formed to fill a lower portion of the trench; and

a capping layer formed over the gate electrode to fill an upper portion of the trench,

wherein the gate electrode includes:

a first work function liner formed on the bottom surface and the lower sidewall of the lower portion of the trench, not overlapping the first impurity region and the second impurity region, and formed of titanium aluminum nitride;

a second work function liner formed on an upper sidewall of a lower portion of the trench above the first work function liner, overlapping the first impurity region and the second impurity region, and including a silicon-containing nonmetal material;

a first low resistivity electrode partially filling a lower portion of the trench above the first work function liner; and

a second low resistivity electrode formed over the first low resistivity electrode to fill a remaining lower portion of the trench over the second work function liner,

wherein each of the first and second low-resistivity electrodes comprises a material that reacts with the second work function liner.

2. The semiconductor device of claim 1, wherein the gate electrode further comprises:

a lower barrier between the first work function liner and the first low resistivity electrode; and

an upper barrier between the second work function liner and the second low resistivity electrode.

3. The semiconductor device of claim 2, wherein the gate electrode further comprises:

an intermediate barrier between the first low resistivity electrode and the second work function liner.

4. The semiconductor device of claim 1, wherein the first and second low-resistivity electrodes comprise tungsten.

5. The semiconductor device of claim 1, wherein the second work function liner comprises N-type impurity doped polysilicon.

6. The semiconductor device of claim 1, further comprising:

a fin region formed under a trench having a first low resistivity electrode formed therein.

7. A semiconductor device, comprising:

a substrate in which a trench is formed;

a first impurity region and a second impurity region formed in the substrate, separated from each other by a trench;

a gate electrode formed to fill a lower portion of the trench; and

a capping layer formed over the gate electrode to fill an upper portion of the trench,

wherein the gate electrode includes:

a low resistivity electrode substantially filling a lower portion of the trench above the first and second work function liners,

wherein the low resistivity electrode is formed of a single layer.

8. The semiconductor device of claim 7, wherein the low-resistivity electrode comprises:

a lower portion formed over the first work function liner to partially fill a lower portion of the trench; and

an upper portion formed over the second work function liner to fill a remaining lower portion of the trench and having sloped sidewalls.

9. The semiconductor device of claim 7 wherein the low resistivity electrode comprises a material that is non-reactive to the second work function liner.

10. The semiconductor device of claim 7, wherein the low resistivity electrode comprises a fluorine-free material and is non-reactive with the second work function liner.

11. The semiconductor device of claim 7, wherein the low-resistivity electrode comprises titanium nitride.

12. The semiconductor device of claim 7, wherein the low resistivity electrode comprises a material that is reactive to the second work function liner.

13. The semiconductor device of claim 12, wherein the gate electrode further comprises:

a barrier between the second work function liner and the low resistivity electrode and between the first work function liner and the low resistivity electrode.

14. The semiconductor device of claim 12, wherein the gate electrode further comprises:

a first barrier between the first work function liner and the low resistivity electrode; and

a second barrier between the second work function liner and the low resistivity electrode.

15. The semiconductor device of claim 14, wherein the low-resistivity electrode comprises tungsten and the first and second barriers comprise titanium nitride.

16. The semiconductor device of claim 7, wherein the second work function liner comprises N-type impurity doped polysilicon.

17. The semiconductor device of claim 7, further comprising:

a bit line electrically coupled to the first impurity region; and

and a memory element electrically coupled to the second impurity region.

Technical Field

Exemplary embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device having a dual work function gate structure, a method for manufacturing the same, a memory cell having the same, and an electronic device having the same.

Background

Due to the high integration of semiconductor devices, Gate Induced Drain Leakage (GIDL) characteristics in non-planar transistors have a significant impact on the performance of semiconductor devices.

Disclosure of Invention

Various embodiments relate to a semiconductor device capable of improving a Gate Induced Drain Leakage (GIDL) current and a current driving capability, and a method for manufacturing the same.

Further, various embodiments relate to a memory cell capable of improving refresh characteristics.

Furthermore, various embodiments relate to an electronic device with improved performance.

In an embodiment, a semiconductor device may include: a substrate in which a trench is formed; a first impurity region and a second impurity region formed in the substrate, separated from each other by a trench; a gate electrode formed to fill a lower portion of the trench; and a capping layer formed over the gate electrode to fill an upper portion of the trench, the gate electrode including: a first work function liner formed on a bottom surface and sidewalls of a lower portion of the trench, not overlapping the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; and a second work function liner formed on a sidewall of a lower portion of the trench above the first work function liner, overlapping the first impurity region and the second impurity region, and including a silicon-containing nonmetal material. The first work function liner has a work function greater than the second work function liner. The first work function liner has a high work function greater than a mid-gap work function of silicon, and the second work function liner has a low work function lower than the mid-gap work function of silicon. The first work function liner comprises titanium aluminum nitride. The second work function liner comprises N-type impurity doped polysilicon. The gate electrode further includes: a first low resistivity electrode partially filling a lower portion of the trench above the first work function liner; and a second low resistivity electrode formed over the first resistivity electrode to fill a remaining lower portion of the trench over the second work function liner. The second low resistivity electrode is a material that is non-reactive to the second work function liner. The first low resistivity electrode comprises a fluorine-free material and is non-reactive with the second work function liner. The second low resistivity electrode comprises a material that is reactive to the second work function liner, and the first low resistivity electrode comprises a fluorine-free material and is non-reactive with the second work function liner. The semiconductor device further includes: a fin region formed under a trench having a first low resistivity electrode formed therein.

In an embodiment, a semiconductor device may include: a substrate in which a trench is formed; a first impurity region and a second impurity region formed in the substrate, separated from each other by a trench; a gate electrode formed to fill a lower portion of the trench; and a capping layer formed over the gate electrode to fill an upper portion of the trench, the gate electrode including: a first work function liner formed on a bottom surface and sidewalls of a lower portion of the trench, not overlapping the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; a second work function liner formed on a sidewall of a lower portion of the trench above the first work function liner, overlapping the first impurity region and the second impurity region, and including a silicon-containing nonmetal material; a first low resistivity electrode partially filling a lower portion of the trench above the first work function liner; and a second low resistivity electrode formed over the first low resistivity electrode to fill a remaining lower portion of the trench over the second work function liner, wherein each of the first and second low resistivity electrodes comprises a material that reacts with the second work function liner. The gate electrode further includes: a lower barrier between the first work function liner and the first low resistivity electrode; and an upper barrier between the second work function liner and the second low resistivity electrode. The gate electrode further includes: an intermediate barrier between the first low resistivity electrode and the second work function liner. The first and second low-resistivity electrodes comprise tungsten. The first work function liner comprises titanium aluminum nitride and the second work function liner comprises N-type impurity doped polysilicon. The semiconductor device further includes: a fin region formed under a trench having a first low resistivity electrode formed therein.

In an embodiment, a semiconductor device may include: a substrate in which a trench is formed; a first impurity region and a second impurity region formed in the substrate to be separated from each other by the trench; a gate electrode formed to fill a lower portion of the trench; and a capping layer formed over the gate electrode to fill an upper portion of the trench, the gate electrode including: a first work function liner formed on a bottom surface and sidewalls of a lower portion of the trench, not overlapping the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; a second work function liner formed on a sidewall of a lower portion of the trench above the first work function liner, overlapping the first impurity region and the second impurity region, and including a silicon-containing nonmetal material; and a low resistivity electrode filling a lower portion of the trench above the first and second work function liners. The low resistivity electrode includes: a lower portion formed over the first work function liner to partially fill a lower portion of the trench; and an upper portion formed over the second work function liner to fill a remaining lower portion of the trench and having sloped sidewalls. The low resistivity electrode comprises a material that is non-reactive to the second work function liner. The low resistivity electrode comprises a fluorine-free material and is non-reactive with the second work function liner. The low resistivity electrode comprises titanium nitride. The low resistivity electrode comprises a material that is reactive to the second work function liner. The gate electrode further includes: a barrier between the second work function liner and the low resistivity electrode and between the first work function liner and the low resistivity electrode. The gate electrode further includes: a first barrier between the first work function liner and the low resistivity electrode; a second barrier between the second work function liner and the low resistivity electrode. The low resistivity electrode comprises tungsten and the first barrier and the second barrier comprise titanium nitride. The first work function liner comprises titanium aluminum nitride and the second work function liner comprises N-type impurity doped polysilicon.

In an embodiment, a method for manufacturing a semiconductor device may include: forming a trench in a substrate; forming a gate dielectric layer over the resulting structure including the trench; forming a gate electrode over the gate dielectric layer to fill a lower portion of the trench; forming a capping layer over the gate electrode to fill an upper portion of the trench; and forming a first impurity region and a second impurity region in the substrate at both sides of the gate electrode, wherein forming the gate electrode includes: forming a first work function liner over a bottom surface and sidewalls of a lower portion of the trench, the first work function liner not overlapping the first impurity region and the second impurity region, the first work function liner comprising an aluminum-containing metal nitride; and forming a second work function liner over sidewalls of a lower portion of the trench over the first work function liner, the second work function liner overlapping the first and second impurity regions and comprising a silicon-containing non-metallic material. The first work function liner is formed of titanium aluminum nitride. The second work function liner is formed of N-type impurity doped polysilicon. Forming the gate electrode further includes: forming a first work function liner layer over the gate dielectric layer; forming a first low resistivity layer over the first work function liner layer to fill the trench; recessing the first work function liner layer and the first low resistivity layer to form a first work function liner and a first low resistivity electrode, the first work function liner and the first low resistivity electrode partially filling a lower portion of the trench; forming a second work function liner layer over the resulting structure comprising the first work function liner and the first low resistivity electrode; recessing the second work function liner layer to form a preliminary second work function liner formed over a sidewall of the trench over the first work function liner and overlapping the first and second impurity regions; forming a second low resistivity layer over the resulting structure including the preliminary second work function liner to fill the trench; and recessing the second low resistivity layer and the preliminary second work function liner to form a second low resistivity electrode and a second work function liner, the second low resistivity electrode and the second work function liner filling the remaining lower portion of the trench. The second low resistivity electrode is formed of a material that is non-reactive with the second work function liner, and the first low resistivity electrode is formed of a fluorine-free material and is non-reactive with the second work function liner. The first and second low-resistivity electrodes are formed of titanium nitride. The first and second low resistivity electrodes are formed of a material that reacts to the second work function liner. Forming the gate electrode further includes: forming a lower barrier disposed between the first work function liner and the first low resistivity electrode; and forming an upper barrier disposed between the second work function liner and the second low resistivity electrode. The first and second low-resistivity electrodes comprise tungsten and the lower and upper barriers comprise titanium nitride. Forming the gate electrode further includes: forming a lower barrier disposed between the first work function liner and the first low resistivity electrode; forming an intermediate barrier disposed between the first low resistivity electrode and the second work function liner; and forming an upper barrier disposed between the second work function liner and the second low resistivity electrode. The first and second low-resistivity electrodes comprise tungsten and the lower, intermediate and upper barriers comprise titanium nitride. Forming the gate electrode further includes: forming a first work function liner layer over the gate dielectric layer; forming a low resistivity layer over the first work function liner layer to fill the trench; recessing the low resistivity layer and the first work function liner layer to form a low resistivity electrode and a first work function liner, the low resistivity electrode and the first work function liner filling a lower portion of the trench; forming a gap overlapping the first impurity region and the second impurity region by removing an upper portion of the first work function liner; and forming a second work function liner filling the gap. A method for fabricating a semiconductor device, wherein forming a gate electrode further comprises, prior to forming a second work function liner: the upper sidewall of the low resistivity electrode is recessed to enlarge the gap. The low resistivity electrode is formed of a fluorine-free material and is non-reactive with the second work function liner. The low resistivity electrode is formed of titanium nitride. The low resistivity electrode is formed of a material that reacts to the second work function liner. Forming the gate electrode further includes: a barrier is formed interposed between the first work function liner and the low resistivity electrode and between the low resistivity electrode and the second work function liner. Forming the gate electrode further includes: forming a lower barrier disposed between the first work function liner and the low resistivity electrode; and forming an upper barrier disposed between the low resistivity electrode and the second work function liner. The low resistivity electrode comprises tungsten.

In an embodiment, a transistor circuit may include a non-planar transistor and a planar transistor, the non-planar transistor being formed in a first region of a substrate and including: a source region and a drain region formed in the first region of the substrate, separated from each other by a trench; a buried gate electrode formed to fill a lower portion of the trench; and a capping layer formed over the buried gate electrode to fill an upper portion of the trench, the planar transistor being formed in the second region of the substrate and including a planar gate electrode, wherein the buried gate electrode includes: a first work function liner formed on a bottom surface and sidewalls of a lower portion of the trench, not overlapping the source and drain regions, and comprising titanium aluminum nitride; and a second work function liner formed on the sidewall of the lower portion of the trench above the first work function liner, overlapping the source and drain regions, and comprising N-type doped polysilicon.

In an embodiment, the storage unit may include: a substrate in which a trench is formed; a first impurity region and a second impurity region formed in the substrate, separated from each other by a trench; a buried word line formed to fill a lower portion of the trench; a capping layer formed over the buried word line to fill an upper portion of the trench; a bit line electrically coupled to the first impurity region; and a memory element electrically coupled to the second impurity region, wherein the buried word line includes: a first work function liner formed on a bottom surface and sidewalls of a lower portion of the trench, not overlapping the first impurity region and the second impurity region, and including titanium aluminum nitride; and a second work function liner formed on a sidewall of a lower portion of the trench above the first work function liner, overlapping the first impurity region and the second impurity region, and including N-type doped polysilicon.

In an embodiment, an electronic device may include at least one non-planar semiconductor device comprising: a substrate in which a trench is formed; a first impurity region and a second impurity region formed in the substrate, separated from each other by a trench; a buried gate electrode formed to fill a lower portion of the trench; and a capping layer formed over the buried gate electrode to fill an upper portion of the trench, wherein the buried gate electrode includes: a first work function liner formed on a bottom surface and sidewalls of a lower portion of the trench, not overlapping the first impurity region and the second impurity region, and including titanium aluminum nitride; and a second work function liner formed on a sidewall of a lower portion of the trench above the first work function liner, overlapping the first impurity region and the second impurity region, and including N-type doped polysilicon.

Drawings

Fig. 1 is a plan view illustrating a semiconductor device according to a first embodiment.

Fig. 2A is a sectional view taken along line a-a' in fig. 1.

Fig. 2B is a sectional view taken along line B-B' in fig. 1.

Fig. 3A and 3B are sectional views illustrating a buried gate type fin channel transistor to which the first embodiment is applied.

Fig. 4A to 4E are sectional views illustrating modifications of the first embodiment.

Fig. 5A to 5H are sectional views describing a method for manufacturing the semiconductor device shown in fig. 1.

Fig. 6A to 6G are sectional views describing a method for manufacturing the semiconductor device shown in fig. 4E.

Fig. 7 is a sectional view illustrating a semiconductor device according to a second embodiment.

Fig. 8A to 8D are sectional views illustrating modifications of the second embodiment.

Fig. 9A to 9F are sectional views describing a method for manufacturing a semiconductor device according to the second embodiment.

Fig. 10A to 10I are sectional views describing a method for manufacturing the semiconductor device shown in fig. 8D.

Fig. 11 is a sectional view illustrating a semiconductor device according to a third embodiment.

Fig. 12 is a sectional view illustrating a transistor circuit including a semiconductor device according to an embodiment.

Fig. 13 is a cross-sectional view illustrating a memory cell including a semiconductor device according to an embodiment.

Fig. 14 is a diagram illustrating an electronic device including a semiconductor device according to an embodiment.

Detailed Description

Various embodiments will be described in more detail below with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate but also to the case where a third layer exists between the first layer and the second layer or the substrate.

Fig. 1 is a plan view illustrating a semiconductor device according to a first embodiment. Fig. 2A is a sectional view taken along line a-a' in fig. 1. Fig. 2B is a sectional view taken along line B-B' in fig. 1.

Referring to fig. 1, 2A, and 2B, the semiconductor device 100 may include a gate structure 100G, a first impurity region 117, and a second impurity region 118. Isolation layer 102 and active region 104 may be formed in substrate 101. The first impurity region 117 and the second impurity region 118 may be disposed in the active region 104. A trench (i.e., gate trench 105) may be formed across active region 104 and isolation layer 102. The gate structure 100G may be formed in the gate trench 105. The first impurity region 117 and the second impurity region 118 may be separated from each other by the gate trench 105.

The semiconductor device 100 may include a transistor. The first embodiment and its modifications can be applied to a non-planar transistor (for example, a buried gate type transistor).

The semiconductor device 100 according to the first embodiment will be described in detail below.

The semiconductor device 100 is formed in a substrate 101. The substrate 101 may include a semiconductor substrate. The substrate 101 may be formed of a silicon-containing material. The substrate 101 may comprise silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon doped silicon, combinations thereof, or multilayers thereof. The substrate 101 may comprise another semiconductor material, such as germanium. Also, the substrate 101 may comprise a III-V semiconductor, e.g., a compound semiconductor substrate such as GaAs. Further, the substrate 101 may include a silicon-on-insulator (SOI) substrate.

Isolation layer 102 and active region 104 may be formed in substrate 101. Active region 104 may be defined by isolation layer 102. The isolation layer 102 may be a Shallow Trench Isolation (STI) region formed by trench etching. The isolation layer 102 may be formed by filling a dielectric material in a shallow trench (e.g., the isolation trench 103).

The gate trench 105 may be formed in the substrate 101. The gate trench 105 may have a straight line shape extending in any one direction when viewed in a plan view. The gate trench 105 may extend across the active region 104 and the isolation layer 102. The gate trench 105 may have a shallower depth than the isolation trench 103. The gate trench 105 may include a first trench 105A and a second trench 105B. A first trench 105A may be formed in the active region 104. A second trench 105B may be formed in the isolation layer 102. The second trench 105B may continuously extend from the first trench 105A. The bottom surfaces of the first trench 105A and the second trench 105B may be located at the same level at a given depth from the top surface of the active region 104. The bottom surface of the gate trench 105 may have a curvature.

The first impurity region 117 and the second impurity region 118 may be formed in the active region 104. The first impurity region 117 and the second impurity region 118 are regions doped with a conductive type impurity. For example, the conductive type impurity may include phosphorus (P), arsenic (As), antimony (Sb), or boron (B). The first impurity region 117 and the second impurity region 118 may be doped with the same conductive type impurity. The first impurity region 117 and the second impurity region 118 may be disposed in the active region 104 at both sides of the gate trench 105. The first impurity region 117 and the second impurity region 118 may correspond to a source region and a drain region, respectively. The bottom surfaces of the first impurity region 117 and the second impurity region 118 may be located at the same level at a predetermined depth from the top surface of the active region 104. The first impurity region 117 and the second impurity region 118 may contact sidewalls of the gate trench 105. The bottom surfaces of the first impurity region 117 and the second impurity region 118 may be located at a higher level than the bottom surface of the gate trench 105.

The gate structure 100G may be disposed in the gate trench 105. The gate structure 100G may be disposed in the active region 104 between the first impurity region 117 and the second impurity region 118 and extend to the isolation layer 102. A bottom surface of a portion of the gate structure 100G disposed in the active region 104 and a bottom surface of a portion of the gate structure 100G disposed in the isolation layer 102 may be at the same level.

The gate structure 100G may include a gate dielectric layer 106, a gate electrode 107, and a capping layer 116. The top surface of the gate electrode 107 may be located at a lower level than the top surface of the active region 104. The gate electrode 107 may fill a lower portion of the gate trench 105. Accordingly, the gate electrode 107 may be referred to as a buried gate electrode. A capping layer 116 may be disposed on the gate electrode 107 to fill an upper portion of the gate trench 105. A gate dielectric layer 106 may be formed on the bottom surface and sidewalls of the gate trench 105.

The gate dielectric layer 106 may comprise silicon oxide, silicon nitride, silicon oxynitride, high-k material, or combinations thereof. The high-k material may include a material having a dielectric constant greater than that of silicon oxide. For example, the high-k material may include a material having a dielectric constant greater than 3.9. For another example, the high-k material may include a material having a dielectric constant greater than 10. For yet another example, the high-k material may include a material having a dielectric constant in a range from about 10 to about 30. The high-k material may include at least one metal element. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxynitride, or combinations thereof. In another embodiment, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. Other high-k materials known in the art may be selectively used as the high-k material.

The gate electrode 107 may include a low resistivity portion and a work function portion. The work function portion may include a first work function liner 109 and a second work function liner 113. The low-resistivity portion may include a first low-resistivity electrode 111 and a second low-resistivity electrode 115. A channel 120 may be formed along the gate electrode 107 between the first impurity region 117 and the second impurity region 118. The channel 120 has a longer channel length than conventional planar transistors. Accordingly, short channel effects can be prevented.

Hereinafter, the first work function liner 109 and the first low-resistivity electrode 111 will be collectively referred to as a lower buried portion 108. Second work function liner 113 and second low resistivity electrode 115 will be collectively referred to as upper buried portion 112.

The lower buried portion 108 may include a first work function liner 109 and a first low resistivity electrode 111. The first low-resistivity electrode 111 may partially fill a lower portion of the gate trench 105. A first work function liner 109 may be disposed between the first low resistivity electrode 111 and the gate dielectric layer 106. The top surfaces of the first work function liner 109 and the first low-resistivity electrode 111 may be located at the same level. The first work function liner 109 may be formed on the bottom surface and the sidewall of the gate trench 105 without overlapping the first impurity region 117 and the second impurity region 118. The lower buried portion 108 may overlap the channel 120. Accordingly, the first work function liner 109 may overlap the channel 120.

Upper buried portion 112 may include a second work function liner 113 and a second low resistivity electrode 115. A second low resistivity electrode 115 may fill the remaining lower portion of the gate trench 105 over the lower buried portion 108. A second work function liner 113 may be placed between second low resistivity electrode 115 and gate dielectric layer 106. The second work function liner 113 may have a shape of a spacer disposed on both sidewalls of the gate trench 105, respectively. The second work function liner 113 may not be interposed between the first low-resistivity electrode 111 and the second low-resistivity electrode 115. The top surfaces of the second work function liner 113 and the second low-resistivity electrode 115 may be located at the same level. The second work function liner 113 may be formed on sidewalls of the gate trench 105 and overlap the first and second impurity regions 117 and 118.

The capping layer 116 may fill an upper portion of the gate trench 105 on the upper buried portion 112. The capping layer 116 may be used to protect the gate electrode 107. The capping layer 116 may comprise a dielectric material. The capping layer 116 may comprise silicon nitride, silicon oxynitride, or a combination thereof. In another embodiment, capping layer 116 may comprise a combination of silicon nitride and silicon oxide. For example, to form the capping layer 116, a spin-on dielectric (SOD) may be filled after performing lining by using silicon nitride.

The gate electrode 107 will be described in detail below.

The first and second work function liners 109 and 113 may be conductive materials. The first and second work function liners 109 and 113 are formed of different work function materials. The first work function liner 109 may have a work function greater than the second work function liner 113. The first work function liner 109 may include a high work function material. The second work function liner 113 may include a low work function material. A high work function material is a material having a work function greater than the mid-gap work function of silicon. A low work function material is a material having a work function lower than the mid-gap work function of silicon. That is, the high work function material may have a work function greater than 4.5eV, and the low work function material may have a work function lower than 4.5 eV. The first work function liner 109 may include a metal-containing material. The second work function liner 113 may comprise a non-metallic material.

The first work function liner 109 may comprise a metal nitride and the second work function liner 113 may comprise a silicon-containing material. The first work function liner 109 may contain a first work function adjusting substance to have a high work function. The first work function adjusting substance may include aluminum (Al). Accordingly, the first work function liner 109 may include a metal nitride including aluminum. The work function of metal nitrides containing aluminum is greater than that of metal nitrides that do not contain aluminum. In the current embodiment, the first work function liner 109 may include aluminum-containing titanium nitride. The aluminum-containing titanium nitride may be referred to as titanium aluminum nitride (TiAlN) or aluminum-doped titanium nitride (Al-doped TiN). The first work function liner 109 may protect the gate dielectric layer 106 from the first low resistivity electrode 111. For example, the first work function liner 109 may prevent impurities contained in the first low resistivity electrode 111 from diffusing into the gate dielectric layer 106.

The second work function liner 113 has a low work function. The second work function liner 113 may contain a second work function adjusting substance to have a low work function. The second work function adjusting substance may include an N-type dopant. Accordingly, the second work function liner 113 may include a silicon-containing material including N-type dopants. In the current embodiment, the second work function liner 113 may include polysilicon, for example, may include polysilicon doped with N-type dopants (hereinafter, referred to as N-type doped polysilicon). N-type doped polysilicon has a low work function. The N-type dopant may include phosphorus (P) or arsenic (As). The second work function liner 113 may overlap the first impurity region 117 and the second impurity region 118. For example, the second work function liner 113 may horizontally overlap the first impurity region 117 and the second impurity region 118.

The first low resistivity electrode 111 comprises a material having a lower specific resistivity than the first work function liner 109. The second low resistivity electrode 115 includes a material having a lower specific resistivity than the second work function liner 113. The first low-resistivity electrode 111 and the second low-resistivity electrode 115 may be formed of the same material or different materials. The first and second low- resistivity electrodes 111 and 115 may be formed of a low-resistivity material. Accordingly, the resistivity of the gate electrode 107 is reduced by the first low-resistivity electrode 111 and the second low-resistivity electrode 115. The first low-resistivity electrode 111 and the second low-resistivity electrode 115 comprise a low-resistivity metal-containing material. In order to reduce the resistivity of the gate electrode 107, the second work function liner 113 may be formed to a thin thickness. Therefore, the resistivity of the gate electrode 107 can be significantly reduced by increasing the amount of the metal material.

In the first embodiment, the second low-resistivity electrode 115 may be formed of a material that is not reactive to the second work function liner 113. That is, the second low resistivity electrode 115 may be formed of a material that does not react with the second work function liner 113. For example, in the case where titanium nitride is used as the second low-resistivity electrode 115, silicon of the second work function liner 113 and the second low-resistivity electrode 115 do not react with each other. Accordingly, the barrier may be omitted between the second low resistivity electrode 115 and the second work function liner 113.

As such, the second low-resistivity electrode 115 may be formed of a low-resistivity metal-containing material having a lower specific resistivity than the second work function liner 113 and being non-reactive with the second work function liner 113.

The first low-resistivity electrode 111 may be formed of a low-resistivity metal-containing material having a lower specific resistivity than the first and second work function liners 109 and 113 and being non-reactive with the second work function liner 113. In addition, the first low resistivity electrode 111 may be formed of a material that does not attack the gate dielectric layer 106. For example, the first low-resistivity electrode 111 may be formed of a material that does not contain impurities such as fluorine. The first low-resistivity electrode 111 may be formed of a fluorine-free material.

The first low-resistivity electrode 111 and the second low-resistivity electrode 115 may include titanium nitride. Since the second low-resistivity electrode 115 is a material that is not reactive to the second work function liner 113 and the first low-resistivity electrode 111 is a material that does not contain fluorine, the gate electrode 107 may not need a barrier, and thus is referred to as a non-blocking gate electrode. In another embodiment, the first and second low- resistivity electrodes 111 and 115 may include tungsten that does not contain fluorine (i.e., fluorine-free tungsten (FFW)).

The first impurity region 117, the second impurity region 118, and the gate structure 100G may constitute a transistor. For example, the transistor may be referred to as a buried gate transistor. The channel 120 may be defined along the surface of the gate trench 105 between the first impurity region 117 and the second impurity region 118. In an embodiment, the channel 120 may include dopants that are doped by channel doping.

According to a first embodiment, the threshold voltage (Vt) is controlled by the first work function liner 109. The threshold voltage may be shifted by the first work function liner 109. For example, the aluminum of the first work function liner 109 forms a dipole layer at the interface between the first work function liner 109 and the gate dielectric layer 106. The dipole layer may change the work function of the lower buried portion 108 and, accordingly, may shift the threshold voltage. As a result, the dose of the channel 120 can be reduced by the first work function liner 109.

Since the gate trench 105 has a high aspect ratio, it is difficult to sufficiently perform doping on the bottom portion of the gate trench 105 by channel doping known in the art. Therefore, after the initial channel doping, additional channel doping is locally performed on the bottom portion of the gate trench 105, which is referred to as local channel doping. In the case where the implant is applied by local channel doping, this is referred to as Local Channel Implant (LCI).

Since the channel dose may be reduced by the first work function liner 109, the dose of the local channel doping may be significantly reduced or may be omitted. As a result, in the embodiment, since the channel dose is reduced, the junction leakage characteristics can be improved.

Furthermore, in the first embodiment, since the second work function liner 113 has a low work function, Gate Induced Drain Leakage (GIDL) at the first and second impurity regions 117 and 118 may be suppressed. In the case where the high work function first work function liner 109 overlaps the first and second impurity regions 117 and 118, gate induced drain leakage may increase. Accordingly, the first work function liner 109 may be adjusted in height so as not to overlap with the first impurity region 117 and the second impurity region 118. For example, a low work function metal material (i.e., an N-type work function metal) may be used as the second work function liner 113. Since the N-type work function metal has a work function greater than that of the N-type doped polysilicon, it is difficult to obtain a low work function corresponding to the N-type doped polysilicon by using the N-type work function metal.

Although the specific resistivity of the second work function liner 113 may be relatively higher than other metal materials, the effect on the resistivity of the gate electrode 107 may be minimized by reducing the ratio (i.e., thickness) of the second work function liner 113 in the gate electrode 107. In addition, since the second work function liner 113 is not present on the top surface of the first low resistivity electrode 111, the ratio of the second work function liner 113 in the gate electrode 107 can be further reduced.

Gate electrode 107 can be a dual work function buried gate electrode. For example, the dual work function buried gate electrode includes a first work function liner 109 having a high work function and a second work function liner 113 having a low work function.

The gate electrode 107 according to the first embodiment can be applied to a buried gate type fin channel transistor.

Fig. 3A and 3B are sectional views illustrating a buried gate type fin channel transistor to which the first embodiment is applied. Fig. 3A is a sectional view taken along line a-a' in fig. 1. Fig. 3B is a sectional view taken along line B-B' in fig. 1. Some components of the semiconductor device 100 may be the same as those of the semiconductor device 100 according to the first embodiment. In fig. 2A to 3B, the same reference numerals are used to refer to the same elements.

Referring to fig. 3A and 3B, the gate trench 105 includes a first trench 105AF and a second trench 105 BF. The first trench 105AF is formed in the active region 104. The second trench 105BF is formed in the isolation layer 102. The second trench 105BF may continuously extend from the first trench 105 AF. In the gate trench 105, bottom surfaces of the first trench 105AF and the second trench 105BF may be located at different levels from the top surface of the active region 104. For example, the bottom surface of the first trench 105AF may be located at a higher level than the bottom surface of the second trench 105 BF. Since the isolation layer 102 is recessed, the depths of the first trench 105AF and the second trench 105BF are different. Accordingly, the second trench 105BF may include a recessed region R having a lower bottom surface than the bottom surface of the first trench 105 AF.

The fin region 104F is formed in the active region 104 due to a difference in depth of the first trench 105AF and the second trench 105 BF. Thus, active region 104 includes fin region 104F.

As such, the fin region 104F is formed under the first trench 105AF, and the sidewall of the fin region 104F is exposed by the recessed isolation layer 102F. Fin region 104F is the portion where the channel is formed. Fin region 104F is referred to as a saddle fin. By forming the fin region 104F, the channel width can be increased, and the electrical characteristics can be improved.

The gate structure 100G of the semiconductor device 100 includes a gate dielectric layer 106, a gate electrode 107, and a capping layer 116. The gate electrode 107 may include a lower buried portion 108 and an upper buried portion 112. Gate dielectric layer 106 may be formed on the sidewalls and top surface of fin region 104F. The lower buried portion 108 may be formed on both sidewalls and a top surface of the fin region 104F. The lower buried portion 108 is formed in the gate trench 105 while filling the recessed region R. The cross-sectional area of the lower buried portion 108 may be larger in the isolation layer 102 than in the active region 104. The upper buried portion 112 is not located around the sidewall of the fin region 104F. The channel dose of fin 104F is affected by first workfunction liner 109.

Fig. 4A to 4E are sectional views illustrating modifications of the first embodiment. Some components of the semiconductor device 100 according to the modification of the first embodiment may be the same as those of the semiconductor device 100 according to the first embodiment. The remaining components except for the gate structures 1001G, 1002G, 1003G, 1004G, and 1005G may be the same as those of the first embodiment.

Referring to fig. 4A, the gate structure 1001G of the semiconductor device 100 according to the first modification may include a gate dielectric layer 106, a gate electrode 107, and a capping layer 116. The gate electrode 107 may fill a lower portion of the gate trench 105, and the capping layer 116 may fill an upper portion of the gate trench 105 above the gate electrode 107. The gate electrode 107 may include a lower buried portion 108 and an upper buried portion 112.

Upper buried portion 112 may include a second work function liner 113, an upper barrier 114, and a second low resistivity electrode 115. A second low resistivity electrode 115 may fill the remaining lower portion of the gate trench 105 over the lower buried portion 108. A second work function liner 113 may be placed between second low resistivity electrode 115 and gate dielectric layer 106. The second work function liner 113 may have a spacer shape disposed on both sidewalls of the gate trench 105, respectively. The second work function liner 113 may not be interposed between the first low-resistivity electrode 111 and the second low-resistivity electrode 115. The top surfaces of the second work function liner 113 and the second low-resistivity electrode 115 may be located at the same level. Upper barrier 114 may be disposed between second work function liner 113 and second low resistivity electrode 115 and between first low resistivity electrode 111 and second low resistivity electrode 115.

In the first modification, the second low-resistivity electrode 115 may be formed of a material having low resistivity and reacting with the second work function liner 113. That is, the second low resistivity electrode 115 may be formed of a material that easily reacts with the second work function liner 113. For example, tungsten may be used as the second low-resistivity electrode 115. Since the silicon of the second work function liner 113 and the tungsten of the second low resistivity electrode 115 react with each other, tungsten silicide may be formed. The resistivity may be increased by tungsten silicide. Therefore, in order to prevent such a silicide reaction, an upper barrier 114 is interposed between the second low-resistivity electrode 115 and the second work function liner 113. The upper barrier 114 may be formed of a material having a lower specific resistivity than the second work function liner 113.

According to a first variant, the first work function liner 109 may comprise titanium aluminium nitride and the second work function liner 113 may comprise N-doped polysilicon. The first low-resistivity electrode 111 may include titanium nitride. The second low-resistivity electrode 115 may comprise tungsten. The upper barrier 114 may include titanium nitride.

Referring to fig. 4B, the gate structure 1002G of the semiconductor device 100 according to the second modification may include a gate dielectric layer 106, a gate electrode 107, and a capping layer 116. The gate electrode 107 may fill a lower portion of the gate trench 105, and the capping layer 116 may fill an upper portion of the gate trench 105 above the gate electrode 107. The gate electrode 107 may include a lower buried portion 108 and an upper buried portion 112.

The lower buried portion 108 may include a first work function liner 109, a lower barrier 110, and a first low resistivity electrode 111. The first low-resistivity electrode 111 may partially fill a lower portion of the gate trench 105. A first work function liner 109 may be placed between the first low resistivity electrode 111 and the gate dielectric layer 106. The top surfaces of the first work function liner 109 and the first low-resistivity electrode 111 may be located at the same level. The lower barrier 110 may be interposed between the first work function liner 109 and the first low resistivity electrode 111.

In a second variation, the first low-resistivity electrode 111 may be formed of a material having low resistivity and including impurities that attack the gate dielectric layer 106. For example, tungsten may be used as the first low-resistivity electrode 111. When tungsten is deposited by using a source gas such as tungsten hexafluoride, the gate dielectric layer 106 may be attacked by fluorine. Therefore, to prevent such fluorine attack, a lower barrier 110 is interposed between the first low resistivity electrode 111 and the first work function liner 109. Although the first work function liner 109 may serve as a barrier for preventing fluorine erosion, fluorine erosion may be further prevented by the lower barrier 110. The lower barrier 110 may be formed of a material having a low specific resistance.

Second low-resistivity electrode 115 may be formed of a low-resistivity metal-containing material having a lower specific resistivity than first and second work function liners 109 and 113 and being non-reactive with second work function liner 113. Accordingly, the upper barrier 114 in fig. 4A is not required.

According to a second variant, the first work function liner 109 may comprise titanium aluminium nitride and the second work function liner 113 may comprise N-doped polysilicon. The first low-resistivity electrode 111 may comprise tungsten. The second low-resistivity electrode 115 may include titanium nitride. The lower barrier 110 may include titanium nitride.

Referring to fig. 4C, the buried gate structure 1003G of the semiconductor device 100 according to the third modification may include a gate dielectric layer 106, a gate electrode 107, and a capping layer 116. The gate electrode 107 may fill a lower portion of the gate trench 105, and the capping layer 116 may fill an upper portion of the gate trench 105 above the gate electrode 107. The gate electrode 107 may include a lower buried portion 108, an upper buried portion 112, and an intermediate barrier 119 between the lower buried portion 108 and the upper buried portion 112.

The first resistivity electrode 111 may be formed of a material having low resistivity and including impurities that erode the gate dielectric layer 106. For example, tungsten may be used as the first low-resistivity electrode 111. When using a tungsten hexafluoride (WF) for example₆) The gate dielectric layer 106 may be attacked by fluorine when tungsten is deposited from the source gas. Therefore, to prevent such fluorine attack, a lower barrier 110 is interposed between the first low resistivity electrode 111 and the first work function liner 109. Although the first work function liner 109 may serve as a barrier for preventing fluorine attack, fluorine attack may be further prevented by the lower barrier 110. The lower barrier 110 may be formed of a material having a low specific resistance.

A third variation may include an intermediate barrier 119. An intermediate barrier 119 may be disposed between the lower buried portion 108 and the upper buried portion 112. The reaction of the second work function liner 113 with the first low resistivity electrode 111 may be prevented by the intermediate barrier 119. In the case where the thickness of the second work function liner 113 is thick, the second work function liner 113 and the first low resistivity electrode 111 may contact each other. Accordingly, in order to prevent the reaction of the second work function liner 113 with the first low resistivity electrode 111, an intermediate barrier 119 may be formed. The intermediate barrier 119 may be formed of a material that is non-reactive with the second work function liner 113. The intermediate barrier 119 may be formed of titanium nitride.

According to a third variant, the first work function liner 109 may comprise titanium aluminium nitride and the second work function liner 113 may comprise N-doped polysilicon. The first low-resistivity electrode 111 may comprise tungsten. The second low-resistivity electrode 115 may include titanium nitride. The lower barrier 110 and the intermediate barrier 119 may include titanium nitride.

Referring to fig. 4D, the buried gate structure 1004G of the semiconductor device 100 according to the fourth modification may include a gate dielectric layer 106, a gate electrode 107, and a capping layer 116. The gate electrode 107 may fill a lower portion of the gate trench 105, and the capping layer 116 may fill an upper portion of the gate trench 105 above the gate electrode 107. The gate electrode 107 may include a lower buried portion 108 and an upper buried portion 112.

Upper buried portion 112 may include a second work function liner 113, an upper barrier 114, and a second low resistivity electrode 115. A second low resistivity electrode 115 may fill the remaining lower portion of the gate trench 105 over the lower buried portion 108. A second work function liner 113 may be placed between second low resistivity electrode 115 and gate dielectric layer 106. The second work function liner 113 may have a shape of a spacer disposed on both sidewalls of the gate trench 105, respectively. The second work function liner 113 may not be interposed between the first low-resistivity electrode 111 and the second low-resistivity electrode 115. Upper barrier 114 may be disposed between second work function liner 113 and second low resistivity electrode 115 and between first low resistivity electrode 111 and second low resistivity electrode 115. The top surfaces of the second work function liner 113 and the second low-resistivity electrode 115 may be located at the same level.

The second low-resistivity electrode 115 may be formed of a material having low resistivity and reacting with the second work function liner 113. Thus, the upper barrier 114 is interposed between the second low resistivity electrode 115 and the second work function liner 113.

As described above, the first low-resistivity electrode 111 and the second low-resistivity electrode 115 may be formed of a material that reacts with the second work function liner 113. To prevent erosion of the gate dielectric layer 106, a lower barrier 110 may be formed. In order to prevent the reaction of the second low resistivity electrode 115 with the second work function liner 113, an upper barrier 114 may be formed.

Referring to fig. 4E, a buried gate structure 1005G of the semiconductor device 100 according to the fifth modification may include a gate dielectric layer 106, a gate electrode 107, and a capping layer 116. The gate electrode 107 may fill a lower portion of the gate trench 105, and the capping layer 116 may fill an upper portion of the gate trench 105 above the gate electrode 107. The gate electrode 107 may include a lower buried portion 108, an upper buried portion 112, and a middle barrier 119.

Upper buried portion 112 may include a second work function liner 113, an upper barrier 114, and a second low resistivity electrode 115. A second low resistivity electrode 115 may fill the remaining lower portion of the gate trench 105 over the lower buried portion 108. A second work function liner 113 may be placed between second low resistivity electrode 115 and gate dielectric layer 106. The second work function liner 113 may have a shape of a spacer disposed on both sidewalls of the gate trench 105, respectively. The second work function liner 113 may not be interposed between the first low-resistivity electrode 111 and the second low-resistivity electrode 115. Upper barrier 114 may be disposed between second work function liner 113 and second low resistivity electrode 115 and between first low resistivity electrode 111 and second low resistivity electrode 115. The top surfaces of the second work function liner 113 and the second low-resistivity electrode 115 may be located at the same level.

An intermediate barrier 119 may be disposed between the lower buried portion 108 and the upper buried portion 112.

The first low-resistivity electrode 111 may be formed of a material having low resistivity and including impurities that erode the gate dielectric layer 106. Thus, the lower barrier 110 is interposed between the first low resistivity electrode 111 and the first work function liner 109. The first low-resistivity electrode 111 may comprise tungsten. The first low resistivity electrode 111 may be a material that is reactive to the second work function liner 113. In the case where the thickness of the second work function liner 113 is thick, the second work function liner 113 and the first low resistivity electrode 111 may contact each other. Accordingly, an intermediate barrier 119 may be formed. The intermediate barrier 119 may be formed of a material that is non-reactive with the second work function liner 113.

The above-described modification can be applied to a buried gate type fin channel transistor.

Hereinafter, a method for manufacturing the semiconductor device according to the first embodiment will be described.

Fig. 5A to 5H are sectional views describing a method for manufacturing the semiconductor device shown in fig. 1. Fig. 5A-5H are cross-sectional views of the illustrated process steps taken along line a-a' in fig. 1.

As shown in fig. 5A, an isolation layer 12 is formed in a substrate 11. The active region 14 is defined by the isolation layer 12. The isolation layer 12 may be formed by a Shallow Trench Isolation (STI) process. For example, after forming a pad layer (not shown) on the substrate 11, the pad layer and the substrate 11 are etched by using an isolation mask (not shown). As a result, the isolation trench 13 is formed. The isolation trench 13 is filled with a dielectric material, thereby forming an isolation layer 12. The isolation layer 12 may comprise silicon oxide, silicon nitride, or a combination thereof. A Chemical Vapor Deposition (CVD) process or other deposition process may be performed to fill the isolation trenches 13 with a dielectric material. A planarization process such as a Chemical Mechanical Polishing (CMP) process may be additionally performed.

A gate trench 15 is formed in the substrate 11. The gate trench 15 may be formed in a straight line shape across the active region 14 and the isolation layer 12. The gate trench 15 may be formed by forming a mask pattern (not shown) on the substrate 11 and performing an etching process using the mask pattern as an etching mask. The gate trench 15 may be formed shallower than the isolation trench 13. The gate trench 15 may have a sufficient depth to increase an average cross-sectional area of a gate electrode to be formed later, so that the resistivity of the gate electrode may be reduced. The bottom of the gate trench 15 may have a curvature. By forming the gate trench 15 to have a curvature, the roughness of the bottom of the gate trench 15 can be minimized, and accordingly, the filling of the gate electrode can be easily performed. Further, since the gate trench 15 has curvature, the corner shape may be removed at the corner of the bottom of the gate trench 15, so that the concentration of the electric field may be mitigated.

As shown in fig. 5B, a gate dielectric layer 16A may be formed on the resulting structure including the gate trench 15. Prior to forming the gate dielectric layer 16A, a specific process may be performed to minimize/reduce etching damage to the surface of the gate trench 15. For example, after a sacrificial oxide (not shown) is formed through a thermal oxidation process, the sacrificial oxide may be removed.

The gate dielectric layer 16A may be formed by a thermal oxidation process. In another embodiment, the gate dielectric layer 16A may be formed by a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process. Gate dielectric layer 16A may comprise a high-k material, an oxide, a nitride, an oxynitride, or combinations thereof. The high-k material may include a hafnium-containing material. The hafnium-containing material may include hafnium oxide, hafnium silicon oxynitride, or combinations thereof. In another embodiment, the high-k material may include lanthanum oxide, lanthanum aluminum oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof. Other high-k materials known in the art may be selectively used as the high-k material.

A first work function liner layer 17A may be formed on the gate dielectric layer 16A. The first work function liner 17A may be conformally formed on the surface of the gate dielectric layer 16A. The first work function liner layer 17A has a work function larger than the intermediate band gap work function of silicon (4.5 eV). The first work function liner layer 17A may be referred to as a high work function layer. The first work function liner layer 17A may be formed of a metal-containing material. The first work function liner 17A may include aluminum-containing titanium nitride. The aluminum-containing titanium nitride may be referred to as titanium aluminum nitride (TiAlN) or aluminum-doped titanium nitride (Al-doped TiN). As a method for forming aluminum-doped titanium nitride (Al-doped TiN), doping such as aluminum implantation may be performed after depositing titanium nitride (TiN). As a method for forming titanium aluminum nitride (TiAlN), an aluminum-containing material may be added in an in-situ aluminum-doped manner during a deposition process in which titanium nitride (TiN) is deposited. For example, when titanium nitride (TiN) is deposited by a Chemical Vapor Deposition (CVD) process, a titanium source material, a nitrogen-containing material, and an aluminum source material are simultaneously flowed. Titanium aluminum nitride (TiAlN) has a larger work function than titanium nitride (TiN).

A first low resistivity layer 19A may be formed on the first work function liner layer 17A. The first low-resistivity layer 19A may fill the gate trench 15. The first low-resistivity layer 19A includes a low-resistivity metal material. The first low-resistivity layer 19A may be formed of a material that does not contain impurities such as fluorine to prevent erosion of the gate dielectric layer 16A. Further, the first low-resistivity layer 19A may be formed of a material that is not reactive to a second work function liner layer to be formed later. The first low-resistivity layer 19A may be formed of titanium nitride. The first low resistivity layer 19A may be deposited by chemical vapor deposition (C)VD) process or an Atomic Layer Deposition (ALD) process. In another embodiment, in the case where the first low-resistivity layer 19A is formed of tungsten, since tungsten is formed by using tungsten such as tungsten hexafluoride (WF)₆) So that the gate dielectric layer 16A may be attacked by fluorine. In order to prevent such erosion of the gate dielectric layer 16A, a lower barrier layer may be formed in advance before the first low resistivity layer 19A is formed. The lower barrier layer may be conformally formed on the surface of the first work function liner layer 17A. The lower barrier layer may be formed of a metal-containing material. The lower barrier layer may include a metal nitride. For example, the lower barrier layer may include titanium nitride. The lower barrier layer may become a lower barrier (110 in fig. 4B to 4E) by a first recess process to be performed later.

As shown in fig. 5C, a first recess process is performed in such a manner that the first work function liner 17 and the first low-resistivity electrode 19 remain in the gate trench 15. The first recess process may be performed by a dry etching process (e.g., an etch-back process). The first work function liner 17 is formed by an etch back process for the first work function liner layer 17A. The first low-resistivity electrode 19 is formed by a back-etching process of the first low-resistivity layer 19A. In another embodiment, the first recess process may be performed in such a manner that after the planarization process is performed, an etch-back process is subsequently performed.

The lower buried portion 20 is formed by the first recess process described above. The lower buried portion 20 comprises a first work function liner 17 and a first low resistivity electrode 19. The lower buried portion 20 may be recessed to be lower than the top surface of the active region 14.

As shown in fig. 5D, a second work function liner layer 21A may be formed. The second work function liner layer 21A may be conformally formed on the surfaces of the lower buried portion 20 and the gate dielectric layer 16A. The second work function liner layer 21A may be a different work function material from the first work function liner 17. The second work function liner layer 21A includes a low work function material. The second work function liner layer 21A may be formed of a non-metal material. The second work function liner layer 21A may include polysilicon doped with N-type impurities.

As shown in fig. 5E, a second recess process may be performed on the second work function liner layer 21A (shown in fig. 5D). That is, the second work function liner layer 21A may be etched. For example, the second work function liner layer 21A may be etched back. Accordingly, a preliminary second work function liner 21B may be formed on the sidewalls of the gate trench 15 over the first work function liner 17. The preliminary second work function liner 21B may have a shape of a spacer. By the preliminary second work function liner 21B, the top surface of the first low resistivity electrode 19 may be exposed. The preliminary second work function liner 21B and the first work function liner 17 may be in contact with each other. The preliminary second work function liner 21B and the second work function liner 17 may be formed to have the same thickness. The top surface of the preliminary second work function liner 21B may be located at the same level as the top surface of the active region 14.

As shown in fig. 5F, a second low-resistivity layer 23A is formed on the resulting structure including the preliminary second work function liner 21B and the lower buried portion 20. The second low-resistivity layer 23A may fill the remaining portion of the gate trench 15 on the preliminary second work function liner 21B and the lower buried portion 20. The second low-resistivity layer 23A may be formed of the same material as the first low-resistivity electrode 19. The second low-resistivity layer 23A includes a low-resistivity metal material. The second low-resistivity layer 23A may be formed of a material that is not reactive to the preliminary second work function liner 21B. The second low-resistivity layer 23A may be formed of titanium nitride. The second low-resistivity layer 23A may be formed through a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process. In another embodiment, in the case where the second low-resistivity layer 23A is formed of a material (such as tungsten) that is reactive to the preliminary second work function liner 21B, an upper barrier layer may be formed in advance before the second low-resistivity layer 23A is formed. An upper blocking layer may be conformally formed on the surfaces of the preliminary second work function liner 21B and the lower buried portion 20. The upper barrier layer may be formed of a metal-containing material. The upper barrier layer may include a metal nitride. For example, the upper barrier layer may include titanium nitride. The upper barrier layer may be formed of the same material as the lower barrier layer. The upper barrier layer may become an upper barrier (114 in fig. 4A, 4D, and 4E) by a third recess process to be subsequently performed.

As shown in fig. 5G, a third recess process is performed in such a manner that the second work function liner 21 and the second low-resistivity electrode 23 remain in the gate trench 15. The third recess process may be performed by a dry etching process (e.g., a back etching process). The second low-resistivity electrode 23 is formed by a back-etching process of the second low-resistivity layer 23A. The second work function liner 21 is formed by an etch back process to the preliminary second work function liner 21B. The third recess process may be performed in such a manner that after a planarization process is performed until the surface of the gate dielectric layer 16A on the top surface of the active region 14 is exposed, an etch-back process is subsequently performed. The top surfaces of the second low resistivity electrode 23 and the second work function liner 21 may be at the same level. Accordingly, the second work function liner 21 may overlap with the first impurity region and the second impurity region to be formed later.

By the third recess process, the upper buried portion 24 is formed. The upper buried portion 24 includes a second work function liner 21 and a second low resistivity electrode 23. The upper buried portion 24 may be recessed lower than the top surface of the active region 14.

The buried gate electrode 25 is formed through a first recess process, a second recess process, and a third recess process. The buried gate electrode 25 includes a lower buried portion 20 and an upper buried portion 24. The buried gate electrode 25 becomes a dual work function buried gate electrode due to the inclusion of the high work function first work function liner 17 and the low work function second work function liner 21.

Since the top surface of the buried gate electrode 25 is located at a lower level than the top surface of the active region 14, a recessed region R is formed. By forming the recessed region R on the buried gate electrode 25, the physical distance between the buried gate electrode 25 and an adjacent conductor (e.g., a contact plug) can be sufficiently ensured. As a result, the withstand voltage between the buried gate electrode 25 and the adjacent conductor can be improved.

As shown in fig. 5H, a capping layer 26 is formed on the buried gate electrode 25 to fill the recessed region R of the gate trench 15. The capping layer 26 comprises a dielectric material. Capping layer 26 may comprise silicon nitride. As a method for forming the capping layer 26, after a preliminary capping layer (not shown) is formed on the resultant structure including the buried gate electrode 25, a planarization process may be performed on the preliminary capping layer until the top surface of the active region 14 is exposed. Gate dielectric layer 16A on the top surface of active region 14 may be removed to form gate dielectric layer 16, either during or after the planarization process is performed on the preliminary capping layer.

After the formation of the capping layer 26, an impurity doping process is performed by implantation or another doping technique. As a result, the first impurity region 27 and the second impurity region 28 are formed in the active region 14. The capping layer 26 is used as a barrier when performing an impurity doping process. The first impurity region 27 and the second impurity region 28 become a source region and a drain region, respectively. The gate dielectric layer 16A on the top surface of the active region 14 may be removed after the impurity doping process.

The bottom surfaces of the first impurity region 27 and the second impurity region 28 may have a depth overlapping with the upper buried portion 24. Accordingly, the second work function liner 21 may overlap the first impurity region 27 and the second impurity region 28.

In another embodiment, the first impurity region 27 and the second impurity region 28 may be formed before the gate trench 15 is formed. For example, after forming an impurity region by doping impurities into the active region 14 using an ion implantation mask, the gate trench 15 may be formed. The impurity region may be divided into a first impurity region 27 and a second impurity region 28 by the gate trench 15.

Hereinafter, a method for manufacturing the semiconductor device according to the fifth modification of the first embodiment shown in fig. 4E will be described.

Fig. 6A to 6G are sectional views describing a method for manufacturing the semiconductor device 100 shown in fig. 4E. A method for preparing the remaining components except for the buried gate electrode will be described with reference to fig. 5A to 5H.

As shown in fig. 6A, a gate dielectric layer 16A may be formed on the surface of the gate trench 15 and the top surfaces of the active region 14 and the isolation layer 12.

A lower barrier layer 18A may be formed on the first work function liner layer 17A. The lower barrier layer 18A may be conformally formed on the surface of the first work function liner layer 17A. The lower barrier layer 18A and the first work function liner layer 17A may be different materials. The lower barrier layer 18A may be formed of a metal-containing material. The lower barrier layer 18A may comprise a metal nitride. For example, the lower barrier layer 18A may include titanium nitride.

A first low resistivity layer 19A may be formed on the lower barrier layer 18A. The first low resistivity layer 19A may fill the gate trench 15. The first low-resistivity layer 19A includes a low-resistivity metal material. The first low-resistivity layer 19A may be formed of a material that reacts to the first work function liner layer 17A and a second work function liner to be formed later. The first low-resistivity layer 19A may include tungsten. The first low-resistivity layer 19A may be formed by a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process.

As shown in fig. 6B, a first recess process is performed in such a manner that the first work function liner 17, the lower barrier 18, and the first low-resistivity electrode 19 remain in the gate trench 15. The first recess process may be performed by a dry etching process (e.g., an etch-back process). The first work function liner 17 is formed by an etch back process for the first work function liner layer 17A. The first low-resistivity electrode 19 is formed by a back-etching process of the first low-resistivity layer 19A. The lower barrier 18 is formed by an etch back process to the lower barrier layer 18A. In another embodiment, the first recess process may be performed in such a manner that after the planarization process is performed, an etch-back process is subsequently performed.

The lower buried portion 20 is formed by the first recess process described above. The lower buried portion 20 comprises a first work function liner 17, a lower barrier 18 and a first low resistivity electrode 19. The lower buried portion 20 may be recessed to be lower than the top surface of the active region 14.

As shown in fig. 6C, an intermediate barrier 29 may be formed. An intermediate barrier 29 may be formed on the top surface of the lower buried portion 20. For example, after forming the intermediate barrier layer 29A on the entire surface of the substrate 11 including the lower buried portion 20, the intermediate barrier layer 29A may be etched so that the intermediate barrier 29 is formed on the top surface of the lower buried portion 20. The intermediate barrier 29 may be formed of a metal nitride. The intermediate barrier 29 may be formed of titanium nitride. The intermediate barrier layer 29A may be formed such that the thickness of the intermediate barrier layer 29A on the top surface of the lower buried portion 20 is thicker than the thickness of the intermediate barrier layer 29A on the other surface.

As shown in fig. 6D, a preliminary second work function liner 21B may be formed. A method for forming the preliminary second work function liner 21B is shown in fig. 5D and 5E. The preliminary second work function liner 21B is formed by forming a second work function liner layer and performing a second recess process. The preliminary second work function liner 21B includes a low work function material. The preliminary second work function liner 21B may be formed of a non-metallic material. The preliminary second work function liner 21B may include polysilicon doped with N-type impurities. The preliminary second work function liner 21B may have a shape of a spacer.

As shown in fig. 6E, an upper barrier layer 22A and a second low resistivity layer 23A may be sequentially formed on the resultant structure including the preliminary second work function liner 21B and the intermediate barrier 29. The upper barrier layer 22A may be conformally formed. The second low-resistivity layer 23A may fill the remaining portion of the gate trench 15 on the lower buried portion 20. The second low-resistivity layer 23A may be formed of the same material as the first low-resistivity electrode 19. The second low-resistivity layer 23A includes a low-resistivity metal material. The second low resistivity layer 23A may be formed of a material that is reactive to the preliminary second work function liner 21B. The second low-resistivity layer 23A may include tungsten. The upper barrier layer 22A may be formed of a metal-containing material. The upper barrier layer 22A may include a metal nitride. For example, the upper barrier layer 22A may comprise titanium nitride. In another embodiment, upper barrier layer 22A may be formed of the same material as lower barrier 18.

As shown in fig. 6F, a third recess process is performed in such a manner that the second work function liner 21, the upper barrier 22, and the second low-resistivity electrode 23 remain in the gate trench 15. The third recess process may be performed by dry etching (e.g., an etch-back process). The second low-resistivity electrode 23 is formed by a back-etching process of the second low-resistivity layer 23A. Upper barrier 22 is formed by an etch back process to upper barrier layer 22A. The second work function liner 21 is formed by a back etching process of the preliminary second work function liner layer 21B. The third recess process may be performed in such a manner that after a planarization process is performed until the surface of the gate dielectric layer 16A on the top surface of the active region 14 is exposed, an etch-back process is subsequently performed. The top surfaces of the second low resistivity electrode 23, the upper barrier 22 and the second work function liner 21 may be located at the same level.

By the third recess process, the upper buried portion 24 is formed. The upper buried portion 24 comprises a second work function liner 21, an upper barrier 22 and a second low resistivity electrode 23.

The buried gate electrode 25 is formed through the first recess process to the third recess process. The buried gate electrode 25 includes a lower buried portion 20, an intermediate barrier 29, and an upper buried portion 24. The buried gate electrode 25 becomes a dual work function buried gate electrode due to the inclusion of the high work function first work function liner 17 and the low work function second work function liner 21.

As shown in fig. 6G, a capping layer 26 is formed on the buried gate electrode 25 to fill the upper portion of the gate trench 15. The capping layer 26 comprises a dielectric material. Capping layer 26 may comprise silicon nitride. As a method for forming the capping layer 26, after a preliminary capping layer (not shown) is formed on the resultant structure including the buried gate electrode 25, a planarization process may be performed on the preliminary capping layer until the top surface of the active region 14 is exposed. Gate dielectric layer 16A on the top surface of active region 14 may be removed to form gate dielectric layer 16, either during or after the planarization process is performed on the preliminary capping layer.

Fig. 7 is a sectional view illustrating a semiconductor device according to a second embodiment. Fig. 7 is a sectional view illustrating a semiconductor device according to a second embodiment taken along line a-a' in fig. 1.

Some components of the semiconductor device 200 according to the second embodiment may be the same as those of the semiconductor device 100 according to the first embodiment. For example, the remaining components other than the gate structure may be the same as those of the first embodiment.

Referring to fig. 7, the semiconductor device 200 according to the second embodiment may include a gate structure 200G, a first impurity region 217, and a second impurity region 218. A gate trench 205 may be formed across active region 204 and isolation layer 202. The gate structure 200G may be formed in the gate trench 205. The first impurity region 217 and the second impurity region 218 may be separated from each other by the gate trench 205.

Gate structure 200G may include a gate dielectric layer 206, a gate electrode 207, and a capping layer 216. The top surface of gate electrode 207 may be located at a lower level than the top surface of active region 204. The gate electrode 207 may fill a lower portion of the gate trench 205. A capping layer 216 may be disposed on the gate electrode 207 to fill an upper portion of the gate trench 205. A gate dielectric layer 206 may be formed along the bottom surface and sidewalls of the gate trench 205. A channel 240 may be formed between the first impurity region 217 and the second impurity region 218 along the gate electrode 207. The channel 240 has a longer channel length than conventional planar transistors. Accordingly, short channel effects can be prevented.

The gate electrode 207 may comprise a first work function liner 209, a single low resistivity electrode 220 and a second work function liner 213. Thus, unlike the first embodiment, the second embodiment has a single low resistivity electrode 220. The single low-resistivity electrode 220 has a structure formed of one low-resistivity layer, and the first embodiment and its modifications are applied to a dual low-resistivity electrode including a first low-resistivity electrode and a second low-resistivity electrode.

A first workfunction liner 209 may be placed between the single low resistivity electrode 220 and the gate dielectric layer 206. The top surface of the first work function liner 209 may be located at a lower level than the top surface of the single low resistivity electrode 220. The first work function liner 209 may overlap the channel 240.

A second workfunction liner 213 may be placed between the single low resistivity electrode 220 and the gate dielectric layer 206. The second work function liner 213 may have a shape of a spacer disposed on both sidewalls of the gate trench 205, respectively. The top surfaces of the second work function liner 213 and the single low resistivity electrode 220 may be located at the same level.

A capping layer 216 may be formed on the top surface of the single low resistivity electrode 220 and the second work function liner 213.

The first and second work function liners 209 and 213 may be conductive materials. The first and second work function liners 209 and 213 are formed of different work function materials. The first work function liner 209 may have a work function greater than the second work function liner 213. The first work function liner 209 may comprise a high work function material. The second work function liner 213 may include a low work function material. A high work function material is a material having a work function greater than the mid-gap work function of silicon. A low work function material is a material having a work function lower than the mid-gap work function of silicon. That is, the high work function material may have a work function greater than 4.5eV, and the low work function material may have a work function lower than 4.5 eV. The first work function liner 209 may comprise a metal-containing material. The second work function liner 213 may comprise a non-metallic material.

The first work function liner 209 may comprise a metal nitride and the second work function liner 213 may comprise a silicon-containing material. The first work function liner 209 may contain a first work function adjusting substance to have a high work function. The first work function adjusting substance may include aluminum (Al). Accordingly, the first work function liner 209 may include a metal nitride including aluminum. The work function of metal nitrides containing aluminum is greater than that of metal nitrides that do not contain aluminum. In the current embodiment, the first work function liner 209 may include aluminum-containing titanium nitride. The aluminum-containing titanium nitride may be referred to as titanium aluminum nitride (TiAlN) or aluminum-doped titanium nitride (Al-doped TiN). As a method for forming aluminum-doped titanium nitride (Al-doped TiN), after depositing titanium nitride (TiN), doping such as aluminum implantation may be performed. As a method for forming titanium aluminum nitride (TiAlN), an aluminum-containing material may be added in an in-situ aluminum-doped manner during a deposition process in which titanium nitride (TiN) is deposited. For example, when titanium nitride (TiN) is deposited by a Chemical Vapor Deposition (CVD) process, a titanium source material, a nitrogen-containing material, and an aluminum source material are simultaneously flowed. The first workfunction liner 209 may protect the gate dielectric layer 206 from the single low resistivity electrode 220.

The second work function liner 213 has a low work function. The second work function liner 213 may contain a second work function adjusting substance to have a low work function. The second work function adjusting substance may include an N-type dopant. Accordingly, the second work function liner 213 may include a silicon-containing material including N-type dopants. In the current embodiment, the second work function liner 213 may include polysilicon, for example, may include polysilicon doped with N-type dopants (hereinafter, referred to as N-type doped polysilicon). N-type doped polysilicon has a low work function. The N-type dopant may include phosphorus (P) or arsenic (As). The second work function liner 213 may overlap the first impurity region 217 and the second impurity region 218. For example, the second work function liner 213 may horizontally overlap the first impurity region 217 and the second impurity region 218. The second work function liner 213 may fill a gap 230 between the single low resistivity electrode 220 and the gate dielectric layer 206. A gap 230 may be placed between the single low resistivity electrode 220 and the gate dielectric layer 206 over the first work function liner 209.

The single low resistivity electrode 220 comprises a material having a lower specific resistivity than the first and second work function liners 209, 213. The single low-resistivity electrode 220 may be formed of a low-resistivity material. Accordingly, the resistivity of the gate electrode 207 is reduced by the single low-resistivity electrode 220. The single low-resistivity electrode 220 includes a low-resistivity metal-containing material. In order to reduce the resistivity of the gate electrode 207, the second work function liner 213 may be formed to a thin thickness. As a result, the resistivity of the gate electrode 207 can be significantly reduced by increasing the amount of the metal material.

In a second embodiment, a single low resistivity electrode 220 may be formed of a material that is non-reactive to the second work function liner 213. That is, the single low resistivity electrode 220 may be formed of a material that is non-reactive with the second work function liner 213.

As such, the single low-resistivity electrode 220 may be formed of a low-resistivity metal-containing material having a lower specific resistivity than the second work-function liner 213 and being non-reactive with the second work-function liner 213.

The single low resistivity electrode 220 may be formed of a low resistivity metal-containing material having a lower specific resistivity than the first work function liner 209 and being non-reactive with the first work function liner 209. Further, the single low-resistivity electrode 220 may be formed of a material that does not contain impurities (such as fluorine) that attack the gate dielectric layer 206.

The single low resistivity electrode 220 may be formed of titanium nitride. Since the single low resistivity electrode 220 is a material that is non-reactive to the second work function liner 213 and is a material that does not contain fluorine, the gate electrode 207 may not need a barrier, and thus is referred to as a non-blocking gate electrode.

Fig. 8A to 8D are sectional views illustrating modifications of the second embodiment. Some components of the semiconductor device 200 according to the modification of the second embodiment may be the same as those of the semiconductor device 200 according to the second embodiment. The remaining components except for the gate structures 2001G, 2002G, 2003G, and 2004G may be the same as those of the second embodiment.

Referring to fig. 8A, a gate structure 2001G of the semiconductor device 200 according to the first modification may include a gate dielectric layer 206, a gate electrode 207, and a capping layer 216. The gate electrode 207 may comprise a first work function liner 209, a single low resistivity electrode 220S and a second work function liner 213. The first work function liner 209 may comprise titanium aluminum nitride. The second work function liner 213 may comprise N-type doped polysilicon. The first work function liner 209 may overlap the channel 240. The second work function liner 213 may overlap the first impurity region 217 and the second impurity region 218.

A single low resistivity electrode 220S may include a lower portion 220L and an upper portion 220U. The sidewalls of the lower portion 220L may have a vertical profile and the sidewalls of the upper portion 220U may have an inclined profile (see reference numeral "S"). The sidewalls of the upper portion 220U may have a positive slope. For example, the top width TCD of the upper portion 220U may be less than the bottom width BCD of the upper portion 220U. The bottom width BCD of the upper portion 220U may be the same as the width of the lower portion 220L. In the lower portion 220L, the top width and the bottom width may be the same as each other.

In this way, since the upper portion 220U of the single low resistivity electrode 220S has a positive slope, the space in which the gap 230 of the second work function liner 213 is formed may be widened. Accordingly, a gap filling margin of the second work function liner 213 can be secured. That is, the gap 230 can be filled with the second work function liner 213 without a void.

Referring to fig. 8B, a gate structure 2002G of the semiconductor device 200 according to the second modification may include a gate dielectric layer 206, a gate electrode 207, and a capping layer 216. The gate electrode 207 may include a first work function liner 209, a single low resistivity electrode 220, a second work function liner 213, and a barrier 221. The first work function liner 209 may overlap the channel 240. The second work function liner 213 may overlap the first impurity region 217 and the second impurity region 218. A second variation may include barrier 221. The barrier 221 may contact the first and second work function liners 209 and 213. For example, the barrier 221 may be disposed between the first work function liner 209 and the single low resistivity electrode 220 and between the second work function liner 213 and the single low resistivity electrode 220.

The first work function liner 209 may comprise titanium aluminum nitride. The second work function liner 213 may comprise N-type doped polysilicon.

The single low resistivity electrode 220 may be formed of a material that is reactive to the second work function liner 213. The barrier 221 may be formed of a material capable of preventing a reaction between the second work function liner 213 and the single low-resistivity electrode 220. The single low-resistivity electrode 220 may comprise tungsten and the barrier 221 may comprise titanium nitride. A silicidation reaction between the second work function liner 213 and the single low resistivity electrode 220 may be prevented by the barrier 221.

Referring to fig. 8C, a gate structure 2003G of the semiconductor device according to the third modification may include a gate dielectric layer 206, a gate electrode 207, and a capping layer 216. The gate electrode 207 may include a first work function liner 209, a single low resistivity electrode 220, a second work function liner 213, a first barrier 222, and a second barrier 223. The first work function liner 209 may overlap the channel 240. The second work function liner 213 may overlap the first impurity region 217 and the second impurity region 218. A third variation may include a first barrier 222 and a second barrier 223. The first barrier 222 and the second barrier 223 may contact a single low resistivity electrode 220. The first barrier 222 may contact a bottom portion and lower sidewalls of the single low-resistivity electrode 220, and the second barrier 223 may contact upper sidewalls of the single low-resistivity electrode 220. A first barrier 222 may be disposed between the first work function liner 209 and the single low resistivity electrode 220. A second barrier 223 may be disposed between the second work function liner 213 and the single low resistivity electrode 220.

The second barrier 223 may be formed of a material capable of preventing a reaction between the second work function liner 213 and the single low resistivity electrode 220. The second barrier 223 may include titanium nitride. A silicidation reaction between the second work function liner 213 and the single low resistivity electrode 220 may be prevented by the second barrier 223.

To prevent erosion of the gate dielectric layer 206, a first barrier 222 is placed between the single low resistivity electrode 220 and the first work function liner 209. The first barrier 222 may be formed of the same material as the second barrier 223. The first barrier 222 may include titanium nitride.

Referring to fig. 8D, the gate structure 2004G of the semiconductor device 200 according to the fourth modification may include a gate dielectric layer 206, a gate electrode 207, and a capping layer 216. The gate electrode 207 may include a first work function liner 209, a single low resistivity electrode 220S, a second work function liner 213, a first barrier 222, and a second barrier 223. The first work function liner 209 may overlap the channel 240. The second work function liner 213 may overlap the first impurity region 217 and the second impurity region 218. A fourth variation may include a first barrier 222 and a second barrier 223. The first barrier 222 and the second barrier 223 may contact a single low resistivity electrode 220S. The first barrier 222 may contact a bottom portion and lower sidewalls of the single low-resistivity electrode 220S, and the second barrier 223 may contact upper sidewalls and a top surface of the single low-resistivity electrode 220S. A first barrier 222 may be disposed between the first work function liner 209 and the single low resistivity electrode 220S. The second barrier 223 may be disposed between the second work function liner 213 and the single low-resistivity electrode 220S and on a top surface of the single low-resistivity electrode 220S.

The first work function liner 209 may comprise titanium aluminum nitride. The second work function liner 213 may comprise N-type doped polysilicon. The single low resistivity electrode 220S may be formed of a material that is reactive to the second work function liner 213. The single low resistivity electrode 220S may comprise tungsten. A single low resistivity electrode 220S may include a lower portion 220L and an upper portion 220U. The sidewalls of the lower portion 220L may have a vertical profile and the sidewalls of the upper portion 220U may have an inclined profile.

The second barrier 223 may be formed of a material capable of preventing a reaction between the second work function liner 213 and the single low resistivity electrode 220S. The second barrier 223 may include titanium nitride. A silicidation reaction between the second work function liner 213 and the single low resistivity electrode 220S may be prevented by the second barrier 223. The second barrier 223 may be formed on a top surface of the upper portion 220U of the single low-resistivity electrode 220S. In another embodiment, the second barrier 223 may be disposed on sidewalls of the upper portion 220U of the single low resistivity electrode 220S.

To prevent erosion of the gate dielectric layer 206, a first barrier 222 is interposed between the single low resistivity electrode 220S and the first work function liner 209. The first barrier 222 may be formed of the same material as the second barrier 223. The first barrier 222 may include titanium nitride.

The above-described modification can be applied to a buried gate type fin channel transistor.

Fig. 9A to 9F are sectional views describing a method for manufacturing the semiconductor device shown in fig. 7. Fig. 9A to 9F are cross-sectional views illustrating process steps taken along line a-a' in fig. 1.

As shown in fig. 9A, an isolation layer 32 is formed in a substrate 31. Active region 34 is defined by isolation layer 32.

A gate trench 35 is formed in the substrate 31. The gate trench 35 may be formed in a straight line shape across the active region 34 and the isolation layer 32. The gate trench 35 may be formed shallower than the isolation trench 33.

A gate dielectric layer 36A may be formed on the surface of the gate trench 35 and on the top surfaces of the active region 34 and the isolation layer 32. Gate dielectric layer 36A may comprise a high-k material, an oxide, a nitride, an oxynitride, or combinations thereof.

A first work function liner 37A may be formed on the gate dielectric layer 36A. The first work function liner 37A may be conformally formed on the surface of the gate dielectric layer 36A. The first work function liner 37A may include a high work function material. The first work function liner 37A may include titanium aluminum nitride (TiAlN).

Next, a low resistivity layer 38A may be formed on the first work function liner layer 37A. Low resistivity layer 38A may fill gate trench 35. The low resistivity layer 38A includes a low resistivity metal material. To prevent erosion of the gate dielectric layer 36A, the low resistivity layer 38A may be formed of a material that does not contain impurities such as fluorine. Further, the low resistivity layer 38A may be formed of a material that is not reactive to a second work function liner layer to be formed later. The low resistivity layer 38A may be formed of titanium nitride. The low resistivity layer 38A may be chemically treatedA vapor deposition (CVD) process or an Atomic Layer Deposition (ALD) process. In another embodiment, in the case where the low-resistivity layer 38A is formed of tungsten, since tungsten is formed by using, for example, tungsten hexafluoride (WF)₆) And thus gate dielectric layer 36A may be attacked by fluorine. To prevent such erosion of gate dielectric layer 36A, a barrier layer may be formed in advance before low resistivity layer 38A is formed. The barrier layer may comprise titanium nitride.

As shown in fig. 9B, the first recess process is performed in such a manner that the preliminary first work function liner 37B and the single low-resistivity electrode 38 remain in the gate trench 35. The first recess process may be performed by a dry etching process (e.g., an etch-back process). The preliminary first work function liner 37B is formed by an etch-back process for the first work function liner layer 37A. A single low-resistivity electrode 38 is formed by a back-etching process of low-resistivity layer 38A. The first recess process may be performed in such a manner that after the planarization process is performed, an etch-back process is subsequently performed.

The preliminary first work function liner 37B and the single low resistivity electrode 38 are recessed lower than the top surface of the active region 34. The first recess process of the second embodiment has a different depth from the first recess process of the first embodiment. That is, the first recess process of the second embodiment may be performed shallower than the first recess process of the first embodiment.

As shown in fig. 9C, a second recess process may be performed. By the second recess process, the first work function liner 37 and the gap 39 may be formed. The second recess process may selectively recess the preliminary first work function liner 37B. For example, the second recess process may have a high selectivity to a single low resistivity electrode 38 and selectively etch only the preliminary first work function liner 37B.

By the second recess process, the first work function liner 37 is formed to be recessed lower than the top surface of the single low resistivity electrode 38. The recessed space of the first work function liner 37 remains as a gap 39.

As shown in fig. 9D, a second work function liner layer 40A may be formed on the resultant structure including the gap 39. The second work function liner layer 40A may fill the gap 39. The second work function liner layer 40A may be a different work function material than the first work function liner 37. The second work function liner 40A includes a low work function material. The second work function liner 40A may be formed of a non-metallic material. The second work function liner layer 40A may include polysilicon doped with N-type impurities.

As shown in fig. 9E, the second work function liner layer 40A may be etched. For example, the second work function liner layer 40A may be etched back. Accordingly, a second work function liner 40 may be formed. The second work function liner 40 may have a shape of a spacer. The top surfaces of the second work function liner 40 and the single low resistivity electrode 38 may be at the same level.

As shown in fig. 9F, a capping layer 41 may be formed to fill an upper portion of the gate trench 35. A capping layer 41 is formed on the single low resistivity electrode 38 and the second work function liner 40. The capping layer 41 comprises a dielectric material. The capping layer 41 may include silicon nitride. As a method of forming the capping layer 41, after a preliminary capping layer (not shown) is formed on the resultant structure including the low resistivity electrode 38 and the second work function liner 40, a planarization process may be performed on the preliminary capping layer until the top surface of the active region 34 is exposed. Gate dielectric layer 36A on the top surface of active region 34 may be removed to form gate dielectric layer 36 either during or after the planarization process is performed on the preliminary capping layer.

After the formation of the capping layer 41, an impurity doping process is performed by implantation or another doping technique. As a result, the first impurity region 42 and the second impurity region 43 are formed in the substrate 31. The first impurity region 42 and the second impurity region 43 become a source region and a drain region, respectively. The gate dielectric layer 36A on the top surface of the active region 34 may be removed after the impurity doping process.

The first and second impurity regions 42 and 43 may overlap the second work function liner 40.

In another embodiment, the first impurity region 42 and the second impurity region 43 may be formed before the gate trench 35 is formed. For example, after forming an impurity region by doping impurities into the active region 34 using an ion implantation mask, the gate trench 35 may be formed. The impurity region may be divided into a first impurity region 42 and a second impurity region 43 by the gate trench 35.

Fig. 10A to 10I are sectional views describing a method for manufacturing the semiconductor device shown in fig. 8D. A method for preparing the remaining components except for the gate electrode will be described with reference to fig. 9A to 9F.

As shown in fig. 10A, an isolation layer 32 is formed in a substrate 31. Active region 34 is defined by isolation layer 32. A gate trench 35 is formed in the substrate 31. A gate dielectric layer 36A may be formed on the surface of the gate trench 35 and on the top surfaces of the active region 34 and the isolation layer 32.

A first barrier layer 44A and a low resistivity layer 38A may be sequentially formed on the first work function liner layer 37A. The first barrier layer 44A may be conformally formed on the surface of the first work function liner layer 37A. Low resistivity layer 38A may fill gate trench 35. The low resistivity layer 38A includes a low resistivity metal material. The low-resistivity layer 38A may be formed of a material containing impurities such as fluorine. Further, the low resistivity layer 38A may be formed of a material that reacts to a second work function liner layer to be formed later. The low resistivity layer 38A may be formed of tungsten. The low resistivity layer 38A may be formed by a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process. The first barrier layer 44A may include titanium nitride.

As shown in fig. 10B, the first recess process is performed in such a manner that the preliminary first work function liner 37B, the preliminary first barrier 44B, and the preliminary single low-resistivity electrode 38 remain in the gate trench 35. The first recess process may be performed by a dry etching process (e.g., an etch-back process). The preliminary first work function liner 37B is formed by an etch-back process for the first work function liner layer 37A. The preliminary first barrier 44B is formed by an etch-back process for the first barrier layer 44A. A preliminary single low-resistivity electrode 38 is formed by a back-etching process of the low-resistivity layer 38A. The first recess process may be performed in such a manner that after the planarization process is performed, an etch-back process is subsequently performed.

The preliminary first work function liner 37B, the preliminary first barrier 44B, and the preliminary single low resistivity electrode 38 are recessed lower than the top surface of the active region 34. The top surfaces of preliminary first work function liner 37B, preliminary first barrier 44B, and preliminary single low resistivity electrode 38 may be located at the same level.

As shown in fig. 10C, a second recess process may be performed. Through the second recess process, the first work function liner 37, the first barrier 44, and the preliminary gap 39A may be formed. The second recess process may selectively recess the preliminary first work function liner 37B and the preliminary first barrier 44B. For example, the second recess process has high selectivity to the preliminary single low-resistivity electrode 38, and selectively etches only the preliminary first work function liner 37B and the preliminary first barrier 44B.

By the second recess process, the first work function liner 37 and the first barrier 44, which are recessed lower than the top surface of the preliminary single low resistivity electrode 38, are formed. The recessed space of the first work function liner 37 and the first barrier 44 remains as the preliminary gap 39A.

As shown in fig. 10D, a preliminary single low-resistivity electrode 38 is additionally recessed. Accordingly, a single low resistivity electrode 38S is formed. The upper sidewalls of the single low resistivity electrode 38S may have a sloped profile S. Further, a widened gap 39B may be formed.

As shown in fig. 10E, a second barrier layer 45A is formed. The second barrier layer 45A may be conformally formed. The gap 39B is not filled with the second barrier layer 45A. The second barrier layer 45A may include titanium nitride.

As shown in fig. 10F, a second dam 45 may be formed. The second barrier 45 may be formed by an etch back process for the second barrier layer 45. The second barrier 45 may be formed on the upper sidewalls and the top surface of the single low resistivity electrode 38S. The second barrier 45 may contact the first barrier 44. In another embodiment, the second barrier 45 may be formed only on the upper sidewalls of the single low-resistivity electrode 38S.

As shown in fig. 10G, a second work function liner layer 40A may be formed over the resulting structure including the gap 39B. The second work function liner 40A may fill the gap 39B. The second work function liner layer 40A may be a different work function material than the first work function liner 37. The second work function liner 40A includes a low work function material. The second work function liner 40A may be formed of a non-metallic material. The second work function liner layer 40A may include polysilicon doped with N-type impurities.

As shown in fig. 10H, the second work function liner layer 40A may be etched. For example, the second work function liner layer 40A may be etched back. Accordingly, a second work function liner 40 may be formed. The second work function liner 40 may have a shape of a spacer filling the gap 39B. The top surface of the second work function liner 40 may be located at a higher level than the single low resistivity electrode 38S. In another embodiment, the top surfaces of the second work function liner 40 and the single low resistivity electrode 38S may be located at the same level.

As shown in fig. 10I, a capping layer 41 may be formed to fill an upper portion of the gate trench 35. A capping layer 41 is formed over the second barrier 45 and the second work function liner 40. The capping layer 41 comprises a dielectric material. The capping layer 41 may include silicon nitride. As a method for forming the capping layer 41, after a preliminary capping layer (not shown) is formed on the resultant structure including the second barrier 45 and the second work function liner 40, a planarization process may be performed on the preliminary capping layer until the top surface of the active region 34 is exposed. Gate dielectric layer 36A on the top surface of active region 34 may be removed to form gate dielectric layer 36 either during or after the planarization process is performed on the preliminary capping layer.

The first and second impurity regions 42 and 43 may overlap the second work function liner 40.

Fig. 11 is a sectional view illustrating a semiconductor device according to a third embodiment.

Referring to fig. 11, the semiconductor device 300 according to the third embodiment may include a pillar type active region 304 and a gate structure 300G. The semiconductor device 300 is illustrated as a vertical channel transistor that is a non-planar transistor.

An isolation layer 302 may be formed in the substrate 301. The isolation layer 302 may fill the isolation trench 303. The pillar type active region 304 may be vertically formed in the substrate 301. The pillar type active region 304 may include a first impurity region 317. The second impurity region 318 may be located in the substrate 301. The channel region 305 may be vertically interposed between the first impurity region 317 and the second impurity region 318.

The gate structure 300G may include a gate dielectric layer 306, a gate electrode 307, and a capping layer 316. The gate electrode 307 may be located at a lower level than the top surface of the pillar type active region 304. The gate electrode 307 may overlap with a sidewall of the pillar-type active region 304. Accordingly, a vertical channel may be formed in the channel region 305 through the gate electrode 307. The gate electrode 307 may be referred to as a vertical gate electrode. A capping layer 316 may be disposed on the gate electrode 307. A gate dielectric layer 306 may be formed on the sidewalls of the pillar-type active region 304 and on a portion of the surface of the substrate 301.

The gate electrode 307 may include a first vertical portion 308 and a second vertical portion 312. The first vertical portion 308 may include a first work function liner 309, a first barrier 310, and a first low resistivity electrode 311. The second vertical portion 312 may include a second work function liner 313, a second barrier 314, and a second low resistivity electrode 315.

A first work function liner 309 may be disposed between the first low resistivity electrode 311 and the channel region 305. The first work function liner 309 may overlap the channel region 305.

The second work function liner 313 may be disposed between the first impurity region 317 and the second low resistivity electrode 315. The second work function liner 313 may overlap the first impurity region 317.

The cover layer 316 may be formed on the second vertical portion 312.

The second impurity region 318 does not overlap with the gate electrode 307.

The first and second work function liners 309, 313 may be conductive materials. The first and second work function liners 309, 313 are formed of different work function materials. The first work function liner 309 may have a work function greater than the second work function liner 313. The first work function liner 309 may include a high work function material. The second work function liner 313 may include a low work function material. A high work function material is a material having a work function greater than the mid-gap work function of silicon. A low work function material is a material having a work function lower than the mid-gap work function of silicon. That is, the high work function material may have a work function greater than 4.5eV, and the low work function material may have a work function lower than 4.5 eV. The first work function liner 309 may include a metal-containing material. The second work function liner 313 may include a non-metallic material.

The first work function liner 309 may comprise a metal nitride and the second work function liner 313 may comprise a silicon-containing material. The first work function liner 309 may comprise titanium aluminum nitride (TiAlN). The second work function liner 313 may comprise N-type doped polysilicon.

The first low-resistivity electrode 311 may be formed of a material having low resistivity and including impurities that attack the gate dielectric layer 306. Thus, the first barrier 310 is placed between the first low resistivity electrode 311 and the first work function liner 309. The first low-resistivity electrode 311 may comprise tungsten. The first low resistivity electrode 311 may be a material that reacts to the second work function liner 313.

The second low-resistivity electrode 315 may be formed of a material having low resistivity and reacting with the second work function liner 313. Thus, the second barrier 314 is interposed between the second low resistivity electrode 315 and the second work function liner 313.

According to the third embodiment, since the second work function liner 313 has a low work function, Gate Induced Drain Leakage (GIDL) in the first impurity region 317 may be suppressed. Since the channel dose of the channel region 305 is reduced by the first work function liner 309, junction leakage may be improved.

The semiconductor device 300 according to the third embodiment may be modified in various ways. For example, the gate structure may be modified similarly to the first embodiment and its modifications and the second embodiment and its modifications.

The semiconductor device according to the embodiment may be integrated in a transistor circuit. In addition, the semiconductor device according to the embodiment can be applied to an integrated circuit including a transistor for various purposes. For example, the semiconductor device according to the embodiment may be applied to an integrated circuit including an insulated gate fet (igfet), a High Electron Mobility Transistor (HEMT), a power transistor, a Thin Film Transistor (TFT), and the like.

The semiconductor device, the transistor, and the integrated circuit according to the embodiment may be embedded in an electronic device. The electronic device may include both memory and non-memory. The memory includes SRAM, DRAM, FLASH, MRAM, ReRAM, STTRAM, and FeRAM. The non-memory includes logic circuitry. The logic circuits may include sense amplifiers, decoders, input/output circuits, etc. for controlling the memory devices. Further, the logic circuit may include various Integrated Circuits (ICs) other than the memory. For example, logic circuitry includes a microprocessor, an application processor of a mobile device, and the like. In addition, the non-memory includes a logic gate such as a nand gate, a driver IC for the display device, a power semiconductor device such as a power management IC (pmic), and the like. The electronic devices may include computing systems, image sensors, cameras, mobile devices, display devices, sensors, medical instruments, optoelectronic devices, Radio Frequency Identification (RFID), solar cells, semiconductor devices for vehicles, semiconductor devices for rail vehicles, semiconductor devices for aircraft, and the like.

Fig. 12 is a sectional view illustrating a transistor circuit including a semiconductor device according to an embodiment.

Referring to fig. 12, the transistor circuit 400 includes a first transistor 420 and a second transistor 440. The first transistor 420 and the second transistor 440 are formed in the substrate 401 and are isolated from each other by the isolation layer 402.

The first transistor 420 includes a gate structure 400G, a first source region 417, and a first drain region 418. A gate structure 400G is formed in the gate trench 405. The gate trench 405 is of a type that crosses the isolation layer 402 and the active region 404. The isolation layer 402 may be formed by filling a dielectric material in the isolation trench 403.

Gate structure 400G may include a first gate dielectric layer 406, a buried gate electrode 407, and a capping layer 416. The buried gate electrode 407 includes a lower buried portion 408 and an upper buried portion 412. The lower buried portion 408 includes a first work function liner 409, a lower barrier 410, and a first low resistivity electrode 411. The upper buried portion 412 includes a second work function liner 413, an upper barrier 414 and a second low resistivity electrode 415. The first work function liner 409 may comprise titanium aluminum nitride (TiAlN) and the second work function liner 413 may comprise N-type doped polysilicon.

The second transistor 440 includes a planar gate electrode 432, a second source region 433, and a second drain region 434. A second gate dielectric 431 is formed under the planar gate electrode 432. The planar gate electrode 432 may comprise polysilicon, metal nitride, metal compound, or combinations thereof. The second gate dielectric layer 431 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a high-k material. The high-k material may include a hafnium-based material. In the second gate dielectric layer 431, an interface layer and a high-k material may be stacked. The interface layer may comprise silicon oxide, silicon nitride or silicon oxynitride.

As can be seen from the above description, in the transistor circuit 400, the first transistor 420 having the buried gate electrode 407 and the second transistor 440 having the planar gate electrode 432 are integrated in one substrate 401. After the first transistor 420 is formed, a second transistor 440 may be formed.

In the transistor circuit 400, both the first transistor 420 and the second transistor 440 may be NMOSFETs. In addition, both the first transistor 420 and the second transistor 440 may be PMOSFETs.

The transistor circuit 400 may be a CMOSFET. For example, any one of the first transistor 420 and the second transistor 440 may be an NMOS transistor, and the other transistor may be a PMOSFET. In the planar gate electrode 432 of the second transistor 440, a suitable work function material may be selected to adjust the threshold voltage. For example, in the case of a PMOSFET, for the planar gate electrode 432, a P-type work function material may be selected to have a work function suitable for the PMOSFET.

The first transistor 420 may be referred to as a buried gate type transistor, and the second transistor 440 may be referred to as a planar gate type transistor.

In the transistor circuit 400, the first transistor 420 may be a transistor of a memory cell, and the second transistor 440 may be a transistor of a peripheral circuit.

In this way, since the buried gate electrode 407 is formed to include the first work function liner 409 of a high work function and the second work function liner 413 of a low work function, the performance of the transistor circuit 400 can be improved.

Fig. 13 is a cross-sectional view illustrating a memory cell including a semiconductor device according to an embodiment.

Referring to fig. 13, a memory cell 500 includes a buried word line 506, a bit line 521, and a storage element 525.

The memory cell 500 will be described in detail below.

An isolation layer 502 is formed in the substrate 501. A plurality of active regions 503 are defined by the isolation layer 502. A gate trench 504 is formed across the active region 503. A gate dielectric layer 505 is formed on the surface of the gate trench 504.

A buried word line 506 is formed on the gate dielectric layer 505 to fill a lower portion of the gate trench 504. The buried word line 506 includes a lower buried portion 507 and an upper buried portion 511. The lower buried portion 507 includes a high work function liner 508, a lower barrier 509, and a first low resistivity electrode 510. The upper buried portion 511 comprises a low work function liner 512, an upper barrier 513 and a second low resistivity electrode 514. The high work function liner 508 may comprise titanium aluminum nitride (TiAlN). The low work function liner 512 may comprise N-type doped polysilicon. The lower barrier 509 and the upper barrier 513 may include titanium nitride. First low-resistivity electrode 510 and second low-resistivity electrode 514 may comprise tungsten. The buried word line 506 has the same configuration as the gate electrode 107 according to the fourth modification of the first embodiment shown in fig. 4D. In other embodiments, the buried word line 506 may have the same configuration as the first embodiment and its modifications and the second embodiment and its modifications.

A capping layer 515 is formed on the buried word line 506 to fill an upper portion of the gate trench 504. First and second impurity regions 516 and 517 are formed in the substrate 501 on both sides of the buried word line 506. The buried word line 506, the first impurity region 516, and the second impurity region 517 may constitute a cell transistor.

A bit line structure electrically coupled to the first impurity regions 516 may be formed. The bitline structure includes bitline 521 and bitline hard mask layer 522. The bit line structure may further include a first contact plug 520 between the bit line 521 and the first impurity region 516. Spacers 523 are formed on the sidewalls of the bitline structures. A first interlayer dielectric layer 519A and a second interlayer dielectric layer 519B are formed over the substrate 501. A first contact plug 520 may be formed in the first contact hole 518. The first contact hole 518 may be formed in the first interlayer dielectric layer 519A. First contact plug 520 is electrically coupled to first impurity region 516. The line widths of the first contact plug 520 and the bit line 521 may be the same. Accordingly, there is a gap between the first contact plug 520 and the sidewall of the first contact hole 518, and a portion of the spacer 523 extends to fill the gap. The top surface of the first impurity region 516 may be recessed, thereby increasing a contact area between the first contact plug 520 and the first impurity region 516. The bit lines 521 may have a straight line shape extending in a direction crossing a direction in which the buried word lines 506 extend. The bit line 521 may include at least one selected from polysilicon, metal silicide, metal nitride, and metal. The bitline hard mask layer 522 may comprise silicon oxide or silicon nitride. The first contact plug 520 may include at least one selected from polysilicon, metal silicide, metal nitride, and metal.

The spacers 523 comprise a dielectric material. Spacers 523 may comprise silicon oxide, silicon nitride, or a combination of silicon oxide and silicon nitride. The spacer 523 may have a multi-spacer structure. For example, the spacer 523 may be a NON structure of silicon nitride/silicon oxide/silicon nitride. The spacer 523 may be an air gap embedded multi-spacer structure.

The memory element 525 may be formed over the second impurity region 517. The second contact plug 524 may be formed between the memory element 525 and the second impurity region 517. A second contact hole 524A may be formed through the first and second interlayer dielectric layers 519A and 519B, and a second contact plug 524 may be formed in the second contact hole 524A. Second contact plug 524 may be electrically coupled to second impurity region 517. The second contact plug 524 may include at least any one selected from polysilicon, metal silicide, and metal nitride. For example, the second contact plug 524 may include a plug structure in which polysilicon, metal silicide, and metal are stacked.

Each of the first interlayer dielectric layer 519A and the second interlayer dielectric layer 519B may be a single-layer structure or a multi-layer structure. Each of the first interlayer dielectric layer 519A and the second interlayer dielectric layer 519B may include at least any one selected from silicon oxide, silicon nitride, and silicon oxynitride. The second interlayer dielectric layer 519B serves to isolate adjacent second contact plugs 524. In another embodiment, a contact spacer (not shown) surrounding a sidewall of the second contact plug 524 may be additionally formed. The contact spacer may be an air gap embedded multi-spacer structure.

In another embodiment, a third contact plug (not shown) may be additionally formed on the second contact plug 524. The third contact plug may have a type overlapping with the bit line structure and the second contact plug 524. The third contact plug may include a metal material.

A memory element 525 may be formed on the second contact plug 524 to be electrically coupled to the second contact plug 524. The memory element 525 may be implemented in various types.

The storage element 525 may be a capacitor. Accordingly, the memory element 525 may include a storage node contacting the second contact plug 524. The storage node may be cylindrical or columnar. A capacitor dielectric layer may be formed on a surface of the storage node. The capacitor dielectric layer may include at least any one selected from zirconia, alumina, and hafnia. For example, the capacitor dielectric layer may be an ZAZ structure in which a first zirconia, an alumina, and a second zirconia are stacked. The plate node is formed on the capacitor dielectric layer. The storage nodes and the panel nodes may include a metal-containing material.

In another embodiment, the memory element 525 may comprise a variable resistor. The variable resistor may include a phase change material. The phase change material may include at least one selected from among tellurium (Te) and selenium (Se) as chalcogen elements. In another embodiment, the variable resistor may include a transition metal oxide. In yet another embodiment, the variable resistor may be a Magnetic Tunnel Junction (MTJ).

As described above, the memory cell 500 may include a buried word line 506 having a high work function liner 508 and a low work function liner 512. In case that the memory cell 500 is applied to a DRAM, a refresh characteristic of the DRAM may be improved.

Fig. 14 is a diagram illustrating an electronic device including a semiconductor device according to an embodiment.

Referring to fig. 14, an electronic apparatus 600 may include a plurality of semiconductor devices 601, 602, 603, 604, and 605. For example, the electronic apparatus 600 may include at least one of the semiconductor devices 100, 200, and 300, the transistor circuit 400, and the memory cell 500 according to the above-described embodiments and variations thereof.

At least one semiconductor device among the semiconductor devices included in the electronic apparatus 600 includes a buried gate electrode formed in the gate trench. The buried gate electrode may include a high work function liner and a low work function liner. The low work function liner overlaps the source and drain regions and, correspondingly, improves Gate Induced Drain Leakage (GIDL). Accordingly, the electronic apparatus 600 can achieve a high operation speed corresponding to the size reduction.

As is apparent from the above description, according to an embodiment, gate-induced drain leakage may be reduced since a low work function liner including N-type doped polysilicon is formed between a gate electrode and source/drain regions.

Furthermore, according to embodiments, since the high work function liner including titanium aluminum nitride overlaps the channel, the channel dose may be reduced and junction leakage may be reduced.

Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

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