阅读说明：本技术 用于低偏移开关电容器积分器的开关方案 (Switching scheme for low offset switched capacitor integrators ) 是由 I·C·M·桑切斯-卡斯特罗 A·J·吉里贝里 C·P·赫里尔 于 2020-03-06 设计创作，主要内容包括：本公开涉及用于低偏移开关电容器积分器的开关方案。描述一种开关电容器积分器,其通过使用基本上将所有电荷注入传送到输出的开关方案来减轻了与连接到求和节点的开关的电荷注入失配所造成的偏移,从而防止了净偏移的积分。(The present disclosure relates to switching schemes for low offset switched capacitor integrators. A switched capacitor integrator is described that mitigates offsets caused by charge injection mismatch with switches connected to a summing node by using a switching scheme that transfers substantially all charge injection to the output, thereby preventing net offset integration.)

1. A switched capacitor integrator circuit, comprising: an amplifier; at least one input capacitor configured to receive and deliver at least one input signal to an input of the amplifier; and at least one capacitor coupled to the amplifier in a feedback configuration, the switched capacitor integrator circuit comprising:

at least two switches coupled to each plate of the at least one input capacitor, wherein at least one of the at least four switches comprises a compound switch comprising a parallel combination of:

a first transistor having a first width; and

a second transistor having a second width greater than the first width,

wherein the control circuit is configured to control operation of the first and second transistors of the at least one compound switch such that when the first transistor is closed, the second transistor is open and then the first transistor is open.

2. The switched capacitor integrator circuit of claim 1, wherein the width of the second transistor is W, and the first transistor has a scaled width (W/s), where s is a scaling factor.

3. The switched capacitor integrator circuit of claim 1, wherein the scaling factor is in a range from 5 to 20.

4. The switched capacitor integrator circuit of claim 1, wherein the at least one compound switch further comprises:

at least one third transistor, wherein the at least one third transistor has a third width, wherein the at least one third transistor is in parallel with the first and second transistors, and wherein the at least one third transistor is configured to open when the first transistor is closed.

5. The switched capacitor integrator circuit of claim 1, wherein the control circuit is configured to control operation of the first transistor using a first clock signal and to control operation of the second transistor using a second clock signal, wherein the first clock signal is different from the second clock signal.

6. The switched capacitor integrator circuit of claim 5, wherein the first clock signal has a first active time and the second clock signal has a second active time, and wherein the second active time is shorter than the first active time.

7. The switched capacitor integrator circuit of claim 1, wherein the integrator circuit is a differential integrator circuit having at least one compound switch symmetrically in each differential input branch.

8. The switched capacitor integrator circuit of claim 1, wherein the compound switch is configured to be coupled between the input of the amplifier and the at least one input capacitor.

9. The switched capacitor integrator circuit of claim 1, wherein the compound switch is configured to be coupled between an input configured to receive at least one input signal and the at least one input capacitor.

10. The switched capacitor integrator circuit of claim 1, wherein the at least one compound switch is configured to be coupled between an input independent voltage and the at least one input capacitor.

11. The switched capacitor integrator circuit of claim 1, in combination with a sigma-delta analog-to-digital converter circuit.

12. A method of operating a switched capacitor integrator circuit, the switched capacitor integrator circuit comprising an amplifier; at least one input capacitor configured to receive and deliver at least one input signal to an input of the amplifier; at least one capacitor coupled to the amplifier in a feedback configuration; and at least two switches coupled to each plate of the at least one input capacitor, wherein at least one of the at least four switches comprises a compound switch, the method comprising:

controlling operation of a compound switch having a parallel combination of:

a first transistor having a first width; and

a second transistor having a second width greater than the first width,

the method comprises the following steps:

the second transistor is closed when the first transistor is open, and then the first transistor is closed.

13. The method of claim 12, wherein controlling operation of at least one compound switch comprises:

applying a first clock signal to the first transistor; and

applying a second clock signal to the second transistor, wherein the first clock signal is different from the second clock signal.

14. The method of claim 13, wherein applying the first clock signal to the first transistor comprises: applying the first clock signal for a first active time, an

Wherein applying the second clock signal to the second transistor comprises: applying the second clock signal for a second active time, wherein the second active time is shorter than the first active time.

15. The method of claim 12, wherein the second transistor is closed when the first transistor is open and then the first transistor is closed during the sampling phase, the method further comprising: the first and second transistors are turned on to start the integration phase.

16. The method of claim 12, wherein controlling operation of at least one compound switch comprises:

the at least one compound switch is coupled between the input of the amplifier and the at least one input capacitor.

17. The method of claim 12, wherein controlling operation of at least one compound switch comprises:

the at least one compound switch is coupled between an input configured to receive at least one input signal and the at least one input capacitor.

18. The method of claim 12, wherein controlling operation of at least one compound switch comprises:

the at least one compound switch is coupled between an input independent voltage and the at least one input capacitor.

19. A switched capacitor integrator circuit comprising an amplifier, an input capacitor configured to receive an input signal, and a capacitor coupled to the amplifier in a feedback configuration, the switched capacitor integrator circuit comprising:

at least one compound switch coupled to a plate of the input capacitor, wherein the compound switch comprises a parallel combination of:

a first transistor having a first width; and

a second transistor having a second width greater than the first width,

wherein the at least one compound switch is configured to be coupled between the input of the amplifier and the input capacitor.

20. The switched capacitor integrator circuit of claim 19, wherein the width of the second transistor is W and the first transistor has a scaled width (W/s), where s is a scaling factor.

Technical Field

This document relates generally, but not by way of limitation, to integrated circuits, and more particularly to switched capacitor circuits.

Background

Switched capacitor circuits typically include switches and capacitors, as well as amplifiers, in arrangements configured to implement a particular input-to-output transfer function. For example, switched capacitor circuits may be used to implement gain stages, filters, D/a converters, and many other types of circuits. The switches of the switched capacitor circuit are selectively turned on and off by a clock signal to implement a pass function.

Switched capacitor circuits have found widespread use due to advances in Complementary Metal Oxide Semiconductor (CMOS) technology. CMOS technology is commonly used to implement switched capacitor circuits due to the availability of Field Effect Transistor (FET) switches and operational amplifiers (op amps) with low input bias currents. One common switched capacitor circuit is a switched capacitor integrator. Such CMOS switched capacitor integrator circuits typically include switches, capacitors, and operational amplifiers.

Disclosure of Invention

More particularly, the present disclosure relates to a switched capacitor integrator that mitigates offset caused by charge injection mismatch with switches connected to a summing node by using a switching scheme that transfers substantially all charge injection to the output, thereby preventing net offset integration.

In some aspects, the present disclosure relates to a switched capacitor integrator circuit, comprising: an amplifier; at least one input capacitor configured to receive and deliver at least one input signal to an input of the amplifier; and at least one capacitor coupled to the amplifier in a feedback configuration, the switched capacitor integrator circuit comprising: at least two switches coupled to each plate of the at least one input capacitor, wherein at least one of the at least four switches comprises a compound switch comprising a parallel combination of: a first transistor having a first width; and a second transistor having a second width greater than the first width, wherein the control circuit is configured to control operation of the first and second transistors of the at least one compound switch such that when the first transistor is closed, the second transistor is open and then the first transistor is open.

In some aspects, the present disclosure relates to a method of operating a switched capacitor integrator circuit, the switched capacitor integrator circuit comprising an amplifier; at least one input capacitor configured to receive and deliver at least one input signal to an input of the amplifier; at least one capacitor coupled to the amplifier in a feedback configuration; and at least two switches coupled to each plate of the at least one input capacitor, wherein at least one of the at least four switches comprises a compound switch, the method comprising: controlling operation of a compound switch having a parallel combination of: a first transistor having a first width; and a second transistor having a second width greater than the first width, comprising: the second transistor is closed when the first transistor is open, and then the first transistor is closed.

In some aspects, the present disclosure relates to a switched capacitor integrator circuit comprising an amplifier, an input capacitor configured to receive an input signal, and a capacitor coupled to the amplifier in a feedback configuration, the switched capacitor integrator circuit comprising: at least one compound switch coupled to a plate of the input capacitor, wherein the compound switch comprises a parallel combination of: a first transistor having a first width; and a second transistor having a second width greater than the first width, wherein the at least one compound switch is configured to be coupled between the input of the amplifier and the input capacitor.

This summary is intended to provide an overview of the subject matter of the present patent application. And are not intended to provide an exclusive or exhaustive explanation of the invention. Including the detailed description to provide more information about the present patent application.

Drawings

In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different instances of similar components. The drawings illustrate generally, by way of example, and not by way of limitation, various embodiments discussed in this document.

Fig. 1 is a schematic diagram of an example of a Switched Capacitor (SC) integrator.

Fig. 2 is a schematic diagram of an equivalent circuit of a portion of the relevant SC network of the SC integrator of fig. 1.

Fig. 3 is a schematic diagram of an equivalent circuit of a portion of an SC integrator using various techniques of the present disclosure.

Fig. 4 is an example of a generic compound switch that may be used to implement the parallel switching technique of the present disclosure.

Fig. 5 is a schematic diagram of another example of a switched capacitor integrator that can implement the parallel switching technique of the present disclosure.

Detailed Description

An analog integrator is a widely used signal processing module. Switched Capacitor (SC) implementations of integrators are very popular due to advantages in accuracy and versatility, especially for Field Effect Transistor (FET) technology. Integrators are typically sensitive to drift because over time they naturally integrate, leading to inaccurate results and possibly saturating the device.

For a FETSC integrator, the effects of most offset sources can be effectively eliminated by state of the art techniques. However, in the prior art, potential offsets caused by charge injection mismatches of the switches connected to the FETSC integrator summing nodes can be mitigated by balancing the set-up time or averaging its effects over time rather than essentially eliminating it as is preferable in many cases.

A fundamental problem that cannot be satisfactorily solved in the prior art is the trade-off between the magnitude of the offset contribution associated with the charge injection mismatch and the settling time impact of the respective switch. The present disclosure presents a technique that substantially mitigates this offsetting contribution without requiring transaction settlement time.

The present disclosure is directed, inter alia, to a switched capacitor integrator that mitigates the effects of charge injection mismatch with switches connected to a summing node by using a switching scheme that delivers substantially all charge injection to an output, thereby preventing integration of a net offset.

Fig. 1 is a schematic diagram of an example of a switched capacitor integrator. The example shown in fig. 1 is a fully differential implementation of an SC integrator.

As in any SC circuit, the operation of an SC integrator is based on the use of switches to apply a voltage into a capacitor. SC circuits are particularly attractive for embodiments in FETs and related technologies because FET technology allows for the competitive implementation of both switches and capacitors. Accordingly, the present disclosure is primarily directed to such techniques.

The fully differential SC integrator circuit 10 of fig. 1 may be formed of an amplifier (amp)12 in negative feedback configuration by connection at output node V_op、V_onAnd a summing node V_sp、V_snSome feedback capacitors C in between_op、C_onAnd from differential input V_i＝V_ip-V_inTransferring charge to V_sp、V_snThe SC of (1) is input to the network. Feedback capacitor C_op、C_onMaintaining integrator differential output V_o＝V_op-V_onThe state of (1).

A set of switches (e.g. transistors) to input the capacitor C_ip、C_inIs connected to the summing node V_sp、V_sn. These switches are labeled RHS switches 14. Another set of switches, e.g. transistors, will C_ip、C_inIs connected to the input terminal V_ip，V_in. These switches are labeled LHS switches 16.

As in any SC circuit, operation is controlled by at least two clock phases that are non-overlapping to avoid unwanted charge loss from associated capacitors. These clock phases are labeled p1, p2 in fig. 1, and further distinguish between the RHS phases (labeled p1r, p2r) and the LHS phases (labeled p1l, p2 l). A complete clock cycle includes all these phases and defines a period T_CLKThe period sets the operating frequency f of the SC integrator_CLK＝1/T_CLK(sampling frequency).

The RHS phases p1r, p2r drive the RHS switch 14, while the LHS phases p1l, p2l drive the LHS switch 16.

In a given phase (p 2 in this case), by adding C_ip、C_inIs connected to a corresponding V_ip，V_inAnd mixing C_ip、C_inIs connected to a Common Mode (CM) summing node voltage V_SCMAt C_ip、C_inMiddle pair V_ip，V_inSampling is performed. Thus, differential charge Q_iSample to C_ip、C_inFrom the following formula (assuming C_ip＝C_in＝C_i) The following are given:

Q_i＝C_i·V_iequation (1)

In the next stage (in this case p1), C is added_ip、C_inIs connected to a Common Mode (CM) input voltage V_ICMAnd mixing C_ip_、C_inIs connected to the summing node V_sp、V_snForcing Q_iInto a feedback capacitor C_op、C_on. This results in a differential step av in the integrator output_oIs expressed as (assume C)_op＝C_on＝C_oAnd applying equation 1):

thus, the SC integrator exhibits discrete-time operation, where the output V, corresponding to the instant n_o(n) becomes available at the end of the corresponding clock cycle (in this case, at the end of p1) and it uses the input V sampled at the previous stage_i(n-1/2) to modify the previously retained output V_o(n-1)：

The ideal gain of the SC integrator is determined by the ratio C of the input capacitance and the feedback capacitance according to equation 2_i/C_oAnd (4) setting.

If the switch is implemented by a FET transistor, charge Q is injected into the terminals of the switch each time its state transitions. This non-ideal effect, known as charge injection, is well known and is considered a significant disadvantage of FET technology.

This charge Q is mainly formed by 2 components: electric charge Q trapped in the channel_chAnd clock feed-through charge Q due to gate-source coupling_clk. Thus, Q can be quantified (where W is the width of the transistor, L is the effective length of the transistor, C_oxIs the gate oxide capacitance per unit area, C_ovIs the gate-source overlap capacitance per unit width, V_GSIs the gate-source voltage, V_THIs the threshold voltage, V_HIs a clock high voltage level, V_LIs clock low voltage level):

Q＝Q_ch+Q_clk＝W·L·C_ox·(V_GS-V_TH)+W·C_ov·(V_H-V_L) Equation (4)

In fig. 1, the relative timing of p1r, p2r is shown, and the non-overlapping nature of these clock signals is shown. The LHS phases p1l, p2l are typically versions of the respective RHS phases plr, p2r, with the sampling edge delayed to avoid sampling the input related charge injection (see equation 4) of the LHS switch to the input capacitor C by floating the LHS switch at either the p1l or p2l transition_ip、C_inIn (1). This technique, called bottom sampling, can prevent LHS charge injection from causing non-linearity and is widely used in SC circuits. RHS switch terminal holding voltage V_SCM(ii) a Thus, their associated charge injection is substantially independent of the input and therefore only causes a shift.

The sampling edge for a given phase is the edge on which the corresponding switch is open; by convention, the falling edge is assumed in this disclosure as a sampling point. Since the sampling edges of plr, p2r precede the sampling edges associated with the corresponding LHS phases p1l, p2l, the RHS samples in each phase can be considered as valid samples for the integrator.

FETSC integrator offset source

In well-designed fully differential integrators, the misalignment is mainly caused by the mismatch of nominally identical components.

For a FETSC fully differential integrator, in effect, the offset contribution of the correlation is:

the amplifier (amp) mismatch induced mismatch of the transistors is mainly present in its input stage.

LHS switch charge injection mismatch (which also causes non-linearity).

RHS switch charge injection mismatch.

At a voltage V due to errors present in the summing nodeOffset Δ V of form integral_OSProportional to integrator gain, Δ V_OS(V)∝(C_i/C_o)·V. This is particularly the case for amplifier 12 detuning.

With charge Q due to errors present in the summing nodeDeviation Δ V of form integral_OS(e.g., RHS switch charge injection mismatch) and feedback capacitance C_oIn inverse ratio, Δ V_os(Q)∝Q/C_o。

Separately injected into summing node V_sp、V_snCharge Q of_p、Q_nWill be Δ V_OS(Q_p，Q_n)∝(Q_p-Q_n)/C_o(ii) a Thus, the resulting offset and absolute charge mismatch Δ Q ═ Q_p-Q_nProportional to the relative mismatch, Δ Q/Q ═ Q (Q)_p-Q_n)/[(Q_p+Q_n)/2]Is in direct proportion. As a result, increased Q_p、Q_nThe nominal value Q of (a) will not be an effective way to minimize its effect (since the amplitude depends on the relative mismatch); conversely, it would be more efficient to reduce Q (this is typically the case assuming that the absolute mismatch Δ Q is scaled to Q).

The effect of amplifier detuning in the integrator output can be effectively mitigated by techniques such as chopping. As described above, the offset caused by the mismatch of charge injection of the LHS switch can be effectively eliminated by bottom sampling.

The effect of the charge injection mismatch of the RHS switch on the compensation can be minimized by any combination of the following methods:

adding a feedback capacitor C_oOf (possibly scaling the input capacitor C)_iTo maintain the same gain).

Overdrive V by reducing the voltage, as shown in equation 4_GS-V_THAnd/or gate area W · L (which is generally more practical) to reduce the magnitude of charge injection.

By averaging T over successive chopping half-cycles with an average value of opposite polarity_RHS/2＝2/f_RHSAt a certain frequency f_RHSChopping is performed on the RHS switch to eliminate the offset caused by the RHS switch charge injection mismatch.

Increase of C_oMeaning that the set-up time for a given power is increased.

Decrease V_GS-V_THIt also affects the settling time because of the on-resistance R of the switch_ON(given approximately by equation 5, where μ is the mobility of the charge carriers) will increase proportionally.

Similarly, reducing W.L (once L reaches its technical minimum, or equivalently at the expense of reducing W/L) will be offset by the settling time for a given power.

Chopping of RHS switch can be performed by working at f_RHSAnd a chopper and noise reducer around the RHS switch. This represents a non-negligible overhead of the clock phase generation and switch drive circuitry of the SC integrator.

Since the switches of the chopper and reducer are in series with the RHS switch, to restore the original settling time for a given power, the W.L of these switches can be sized to obtain an equivalent resistance R comparable to the original RHS switch_ON. Thus, the absolute charge injection mismatch of the RHS switch may increase (for a given settling time), but by one period T_RHSAveraging may mitigate its potential impact on integrator detuning.

Chopper and switch of chopperCancellation occurs due to mismatch in their charge injection. Thus, to obtain an improvement in the net offset, the chopping frequency f_RHSMust be less than the sampling frequency f_CLKTo reduce the equivalent induction offset by the ratio f due to time averaging_CLK/f_RHS> 1, thereby making it acceptable.

In this scheme, the chopping offset component Δ V caused by RHS switch charge injection mismatch_OSAt a frequency f_RHSThe square wave form of (c) appears in the SC integrator output.

f_RHS＜f_CLKIndicating the fact that the component will not be cancelled in every integration cycle (since this requires f_RHS＝f_CLK). The corresponding square wave will therefore be processed by the circuitry after the integrator, possibly causing distortion. This technique relies on some post-processing that filters or mitigates the effects of created offset tones, which is generally not an attractive function. To avoid this, the technique to eliminate RHS switch charge injection mismatch offset must be at the sampling frequency f_CLKThe operation is carried out.

Thus, based on the foregoing, techniques known in the art for mitigating the offset of the charge injection mismatch caused by the RHS switch involve a direct tradeoff between offset and settling time (for a given power and technique) and/or presence of tones. Solutions to these shortcomings are desired.

Conclusion

The present disclosure describes a solution for mitigating offsets caused by RHS switch charge injection mismatch, which can be dynamic (and also offset drift can be cancelled), at a sampling frequency f_CLKOperates (avoids the presence of potentially bad tones) and can break the trade-off between previously established offsets and establishment times.

The effect of charge injection mismatch on the detuning of a typical SC integrator will be analyzed in detail below. Without loss of generality, and to simplify the analysis, only the mismatches associated with the pair of RHS switches 14 driven by p1r are considered. Furthermore, only the mismatched charge injection Δ Q is considered in the analysis (since normal charge injection has no net effect in the integrated output), all mismatch cases are arbitrarily assigned to a single switch, and therefore, it is assumed that the complementary one does not contribute to the charge injection. This is shown in fig. 2.

Fig. 2 is a schematic diagram of an equivalent circuit of a relevant part of an SC (single-ended) network of the SC integrator of fig. 1. In particular, fig. 2 depicts a typical SC integrator RHS switching for a portion of the SC integrator circuit of fig. 1.

The charge injection by the switch sw1 is described next for the relevant transition of the clock signal. The relevant events in chronological order are:

p1r goes low (sample): charge Δ Q₁Injection C_o(resulting in integrator output V_oOccurrence of step DeltaV₁＝ΔQ₁/C_o) Then charge Δ Q is added₂Injection C_iAnd storing.

P2r goes high (reset C)_iRHS plate): previously stored in C_iElectric charge of₂Is dumped to AC ground V_SCMAnd is therefore permanently lost.

P1r goes high (start of next integration phase): electric charge Δ Q₃Injection C_o(resulting in integrator output V_oOccurrence of step DeltaV₃＝ΔQ₃/C_o) And charge DeltaQ₄Injection C_iHowever, since the amplifier is reconnected by the closing of sw1, Δ Q is provided by the amplifier₄(result in V_oOccurrence of step DeltaV₄＝ΔQ₄/C_o)。

Thus, in each cycle, the integrator outputs V_oOf_oIs caused by the charge injection mismatch of the RHS switch driven by p1 r:

the charge injection of the FET switch (given by equation 4) is divided between its 2 terminals (arbitrarily designated as drain and source). The division is not necessarily symmetrical and depends on many factors, such as the relative impedances of the terminals and the transitions in the gate signalThe slope of the migration. Modeling this using a division factor of 0 ≦ d ≦ 1, injecting charge of the FET switch into Q_TAt its terminal Q_d、Q_sThe method comprises the following steps:

Q_T＝Q_d+Q_s，Q_d＝(1-d)·Q_T，Q_s＝d·Q_Tequation (7)

In addition, for a given terminal voltage, the charge injection Q of the FET switch during the falling and rising transitions of its gate signal_TAre identical in amplitude.

In the case of fig. 2, these facts imply:

ΔQ₁+ΔQ₂＝-(ΔQ₃+ΔQ₄) Equation (8)

Therefore, according to equation 7, if Δ Q is given₂Integrating instead of dumping, Δ V_o0. That is, if all the charges injected when the switch sw1 is opened and closed are integrated, the integrator output V_oThe net effect of (c) is zero and the charge injection mismatch associated with sw1 does not cause a shift.

For connection to Common Mode (CM) summing node voltage V_SCMAnd a RHS switch sw2 driven by p2r can perform a similar analysis. The conclusion is the same, but not all the associated charge injections are integrated to cancel out V_oBut instead all charge injection of switch sw2 is dumped into V_SCMAnd similarly, at V_oNor cause an offset. The results obtained are therefore applicable to any RHS switch.

In relation to the offset caused by the charge injection mismatch of the RHS switch in the SC integrator, the following principles are extracted from the above description:

I. the induced misalignment depends on the absolute charge injection mismatch.

If all charge injections of the RHS switch have been integrated, the net effect of the integrator output is zero.

In view of these two principles, the following solutions are proposed to mitigate the offset caused by the charge injection mismatch of the RHS switch without affecting the setup time: adding one and conventionalThe RHS master switch is sized to connect smaller switches in parallel and drive the switches to open only after the master switch is opened to integrate all charge injection of the RHS master switch. As a result, the residual misalignment depends on the absolute charge injection mismatch of the smaller switches, which will be smaller than the mismatch caused by a conventionally sized main RHS switch (according to equation 4). By appropriately determining the relative impedance of the two switches (by the aspect ratio W/L) and the delay T between the opening edges of their drive signals_DLYThe possible impact of this technique on the equivalent setup time can be mitigated.

Fig. 3 is a schematic diagram of an equivalent circuit of a portion of an SC integrator using various techniques of the present disclosure. In particular and in accordance with the present disclosure, fig. 3 depicts an SC integrator RHS parallel switching scheme that uses a smaller switch in parallel with a conventionally sized primary RHS switch and drives it in such a way: the main RHS switch is only turned on after it is turned on to integrate all charge injection of the main RHS switch. The two switches (e.g., transistors) together form what is referred to herein as a "compound switch" that includes a first transistor (switch sw1s) having a first width (W/s) and a second transistor (W) having a second width (W) greater than the first width_f) Is connected in parallel with the second transistor (switch sw1 f). As described below, the compound switch may be formed from more than two transistors.

The RHS switch sw1 of fig. 2 has been replaced with a parallel combination of switches sw1s of reduced width by a factor s (e.g., W/s) and driven by the original phase p1r, while switch sw1f is driven by the new phase p1rf, as shown in fig. 3. In some example configurations, the scaling factor is in the range of 5 to 20, including 5 and 20. Also, this parallel combination is referred to as a compound switch in this disclosure.

The timing of the switches is controlled by a control circuit 20. The control circuit is configured to control operation of the first sw1s switch and the second sw1f switch (e.g., transistors) of the compound switch such that when the first switch is closed, the second switch is open and then the first switch is open.

In some example configurations, the control circuit is configured to control operation of the first switch using a first clock signal and to control operation of the second switch using a second clock signal, wherein the first clock signal is different from the second clock signal. In some examples, the first clock signal (e.g., p1r) has a first active time and the second clock signal (e.g., p1rf) has a second active time, wherein the second active time is shorter than the first active time.

The switch sw1s may be referred to as a slow switch because its impedance is also increased by the same factor s (according to equation 5) compared to the conventional RHS switch sw1 of fig. 2 because its width W/s is reduced by the scaling factor s. Accordingly, its charge injection is smaller than that of switch sw1 by a scaling factor s (according to equation 4). This is illustrated in FIG. 3 by using the lower case letters Δ q_iThe associated charges are labeled for illustration. The sw1s switch is driven by the original p1r phase, thus determining the sampling event in the integrator operation.

The switch sw1f is referred to as a fast switch because its impedance is small compared to the impedance associated with the slow switch sw1s because of its width W_fLarger (W)_f> W/s). It is driven by a new phase p1rf, generated by p1r, but with a time delay T at the opening edge_DLY(as shown in the qualitative timing diagram of fig. 3).

Next, charge injection of the equivalent switch formed by sw1s and sw1f is described for the relevant transitions of the clock signal. The relevant events in chronological order are:

p1rf becomes low: electric charge Δ Q₁Injection C_o(resulting in integrator output V_oStep Δ V₁＝ΔQ₁/C_o) Electric charge Δ Q₂Injection of C by closure of sw1s_o(resulting in integrator output V_oStep Δ V₂＝ΔQ₂/C_o)。

P1r goes low (sample): electric charge Δ q₁Is injected into C_o(resulting in integrator output V_oOccurrence of a step Δ v₁＝Δq₁/C_o) Electric charge Δ q₂Is injected into C_iAnd is stored.

P2r goes high (reset C)_iRHS plate): previously stored in C_iElectric charge Δ q in (1)₂Is dumped to AC groundV_SCMAnd is therefore permanently lost.

P1r and pr1f go high (start of next integration phase): to C_oInjected charge Δ Q₃(resulting in integrator output V_oOccurrence of step DeltaV₃＝ΔQ₃/C_o) To C_iInjected charge Δ Q₄However, Δ Q since the amplifier is reconnected by the closure of sw1f and sw1s₄Supplied by an amplifier (resulting in V)_oOccurrence of step DeltaV₄＝ΔQ₄/C_o) (ii) a Electric charge Δ q₃Is injected into C_oMiddle (leading to V)_oOccurrence of a step Δ v₃＝Δq₃/C_o) Electric charge Δ q₄Is injected into C_iBut since the amplifier is reconnected by the closure of sw1f and sw1s, the amplifier provides a charge Δ q₄(result in V_oOccurrence of a step Δ v₄＝Δq₄/C_o)。

Thus, in each cycle, the integrator output V is caused by charge injection mismatch of the equivalent RHS switch_oThe following offset Δ V 'occurs'_o：

Applying equation 8 to sw1f eliminates the net effect of correlated charge injection. Therefore, equation 9 reduces to:

assuming without loss of generality that sw1s has the same division factor d for charge injection as sw1 in fig. 2, the ratio of the induced offsets for the two approaches becomes (according to equations 10, 8 and 6):

since the only difference between the two switches is the scaling of the aforementioned widths (if width of sw1 is W, width of sw1s is W/s), it follows from equations 4 and 11:

thus, compared to the conventional approach (shown in fig. 2), which is proportional to the ratio of the widths (or in general, the gate areas) of the RHS switches performing the sampling in each case (sw1s in fig. 3 and sw1 in fig. 2 for the conventional switching approach), SC integrators including RHS switches implemented by the new approach (as shown in fig. 3 and referred to as parallel switching techniques) can reduce the offset Δ V 'caused by RHS switch charge injection mismatch'_o。

Again, a similar analysis may be performed by applying the parallel switching technique to the RHS switch sw2 in fig. 3. The conclusion is the same, but not all relevant charge injection components of sw2 are integrated to cancel them at V_oCan be dumped to V_SCMIn (1). The results obtained are therefore applicable to any RHS switch in the SC integrator.

For convenience, these results were obtained assuming systematic mismatch in charge injection. For more relevant random mismatch cases, the principle can be extended directly and the corresponding analysis can be reduced

Given the induced offset (assuming the reality of a normal distribution of random mismatch of charge injection).

Fast switches (sw 1f in FIG. 3) are only in a small fraction of the p1r phase (delayed by a time T)_DLYIndication) is closed. Its function is to allow most of the input charge to be transferred before the input is turned on, and the slow switch (sw1s in FIG. 3) during the remainder of the p1r phase (T) before the sample is turned on_DLY) During which the fine setup is completed.

Therefore, to obtain an equivalent settling time comparable to that achievable by the method shown in fig. 2, the on-resistance of sw1f must be less than the on-resistance of sw 1. Likewise, width W of sw1f_fMay be greater than the width W associated with sw1_f(W_f＞W)。

Since the amount of offset due to charge injection mismatch is independent of sw1f (eq. 10), W can be adjusted_fSize (and time delay T)_DLY) To provide the required settling time without affecting the final offset. Thus, by sampling at the frequency f_CLKThe parallel switching technique of the present disclosure of operation effectively addresses the tradeoff between offset and settling time (and thus potential undesired tones) caused by charge injection mismatch.

An open edge of sw1f (phase p1rf in FIG. 3 goes low) would result in a transition at T_DLYThe perturbation that must be addressed by sw1s during the period and the fine establishment of input signal charge transfer. Thus, the opening of sw1f should occur for a sufficient time before valid sampling (the open edge of sw1s) and/or the gate area of sw1f should be small enough to limit the size of the corresponding perturbation.

The size of the two parameters may be adjusted to achieve the target stable performance while maintaining the gate area of sw1 within the desired minimum range (or equivalently, actively adjusting the size of the scaling factor s as needed) to simultaneously achieve the desired residual offset.

In fact, implementing a corresponding RHS switch opportunity by the described parallel switching technique (shown in fig. 3) results in an increase in power, area and complexity compared to other approaches (shown in fig. 2), which are negligible in practice and controlled by the generation and routing of the additional clock signal p1rf (p1rf is p1r with sampling edges advanced by a given time interval).

Fig. 4 is an example of a generic compound switch that may be used to implement the parallel switching technique of the present disclosure. By considering P fast switches in parallel with slow switch sw1s, a more gradual parallel switching technique operation can be achieved.

In FIG. 4, an array of fast switches sw1f < P:1> may be driven by a dedicated clock signal P1rf < P:1> through control circuit 30. The array of fast samples sw1f < P:1> are turned on sequentially during sampling, thus providing the same operation as the parallel switching technique described above, but with greater flexibility to manage fast switching disturbances.

Essence of natureAbove, given fast switch sw1f<i>Is closer to the sampling edge of the slow switch sw1s (i.e., the associated delay T)_{DLY_i}Smaller), which corresponds to a smaller gate area (in effect, width W)_i) It may be advantageously sized to cause less charge injection and therefore less settling disturbance. This is possible because sw1f<i>Closer to the sampling edge, the less contribution to the remaining coarse settling since the charge transfer will be more complete, so sw1f<i>The smaller the required resistance, W_iThe smaller.

As a result, by the pair sw1f<P:1>Gate region (essentially width W)_P，...，W₁) And sample edge delay T_{DLY_P，}...，T_{DLY_P}With appropriate resizing, the best stable behavior can be obtained for a given residual offset level defining the scaling factor s.

The width W may be determined following any advantageous scaling law_iAnd a time interval T_{DLY_i}Is naturally chosen to be the following relationship: w_P＜…＜W₁And T_{DLY_P}＜…＜T_{DLY_1}(and, in other words, the smaller the gate area of a given slow switch, the closer it is to the sampling instant of opening). In practice, one or two additional switching levels (P.ltoreq.3) are sufficient to obtain the required improvement compared to the method shown in FIG. 2.

For example, the slow switch sw1s (e.g., first transistor) may have a width of W/s, the first fast switch sw1f (1) (e.g., second transistor) may have a width of W/s1, the second fast switch sw1f (2) (e.g., third transistor) may have a width of W/s2, if the second transistor is turned on after the third transistor, W/s < W/s1 < W/s2(s > s 1> s2), and the second and third transistors are turned on before the first transistor.

Parallel switching techniques have been proposed in the context of typical SC fully differential integrators. However, this technique will be applicable to any SC integrator topology by replacing the corresponding RHS switch with the method shown in fig. 3 (or a generalization thereof, as shown in fig. 4).

The technology is directAny SC integrator that does not imply modifications to the RHS switch structure and operation described as an example in this disclosure. For example, the integrator may be differentially sampled for opposite inputs, rather than for the input common mode V_ICMSampling (as described previously and shown in fig. 1). In this case, a parallel switching technique would be applicable.

More importantly, this technique is directly applicable even in cases where the operation of the RHS switch architecture and/or SC integrator deviates from the architecture described as an example in this disclosure. For example, the integrator may integrate in two stages instead of only one stage (as described previously and shown in fig. 1) by doubling the input branches (and thus, the complementary RHS switches). In this case, the parallel switching technique will be equally applied to all RHS switches, based on the same descriptive principles, and it is possible to obtain the same improvements.

The parallel switching technique is also directly applicable to single-ended implementations because it does not rely on the differential nature and/or operation of its components as a principle of operation.

The application of parallel switching techniques can be extended to other switches connected to the SC integrator summing node whose charge injection can ultimately be delivered to the output, for example:

the RHS switch of the SC branch is connected to the reference voltage instead of the input voltage. For example, a digital-to-analog converter (DAC) branches in the integrator of a discrete-time sigma-delta modulator that handles feedback.

The RHS switch of the SC branch is connected to the calibration voltage instead of the input voltage to adjust the offset, gain error or other measure of the integrator.

The switching of the input chopper of the integrating amplifier may be used to mitigate its detuning and/or low frequency noise.

In general, the parallel switching technique proposed in this disclosure is advantageously applicable to any switch (with minor differences) connected to the summing node of an SC integrator, especially if the switch is operated periodically.

The present disclosure focuses on the important case of Integrated Circuits (ICs). However, these principles are equally applicable to discrete circuit implementations of SC integrators.

In a non-limiting specific example of one implementation, the switched capacitor integrator of the present disclosure may be used in a sigma-delta analog-to-digital converter. A non-limiting example of a sigma-delta analog-to-digital Converter using a switched capacitor integrator is described in commonly assigned U.S. patent No. 9,124,290 to Sherry et al, entitled "Method and Apparatus for separating the Reference Current from the Input Signal in sigma-delta Converter," the entire contents of which are incorporated herein by Reference.

Fig. 5 is a schematic diagram of another example of a switched capacitor integrator implementing the parallel switching technique of the present disclosure. The fully-differential SC integrator circuit 40 in fig. 5 may be formed by an amplifier (amplifier) 42 connected at the output node V_op、V_onAnd node V_sp、V_snSome feedback capacitors C in between_op、C_onAnd from differential input V_i＝V_ip-V_inTo V_sp、V_snThe SC input network that delivers charge operates in a negative feedback configuration. Feedback capacitor C_op、C_onMaintaining integrator differential output V_o＝V_op-V_onThe state of (1).

A set of switches (e.g. transistors) to input the capacitor C_ip、C_inIs connected to the summing node V_sp、V_sn. These switches are labeled RHS switches 42. Another set of switches, e.g. transistors, will C_ip、C_inIs connected to the input terminal V_ip，V_in. These switches are labeled LHS switches 44.

As can be seen in the example configuration shown in FIG. 5, all RHS switches (e.g., connecting input capacitor C)_ip、C_inAnd a summing node V_sp、V_snRHS switch) has been replaced by the topology presented in fig. 3, which has at least one fast switch and one slow switch in parallel, so that the differential integrator circuit 40 comprises at least one compound switch in each differential input branch. That is, each RHS switch of FIG. 1 has been completed by a compound switchInstead, the compound switch includes a small slow switch sw1s having a first width (W/s) and a second width (W) greater than the first width_f) As shown in the enlarged portion 46, of the larger fast switch sw1 f. In some example configurations, the scaling factor s is in the range of 5 to 20, including 5 and 20.

As shown in fig. 5, switch sw1s is driven by phase p1r and switch sw1f is driven by phase p1 rf. The timing of the switches is controlled by a control circuit 48. The control circuit is configured to control operation of first and second switches (e.g., transistors) of the compound switch such that when the first switch swls is closed, the second switch swlf is open, and then the first switch swls is open.

Additionally or alternatively, in some example configurations, the parallel switching technique may be applied to one or more LHS switches, e.g., 16 in fig. 1.

In some example configurations, a compound switch may be coupled between an input independent voltage and an input capacitor (e.g., replacing the RHS switch driven by p2r in fig. 1), as shown in fig. 5.

Note

Each non-limiting aspect or example described herein can exist independently or can be combined in various permutations or combinations with one or more other examples.

The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". Such examples may include elements in addition to those shown or described. However, the inventors also contemplate examples providing only those elements shown or described. Moreover, the inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), with respect to particular examples (or one or more aspects thereof), or other examples (or one or more aspects thereof) shown or described herein.

If usage between this document and any document incorporated by reference is inconsistent, then usage in this document controls.

In this document, the terms "a" or "an" are used in patent documents to include one or more, independent of "at least one" or "one or more" of any other circumstance or usage. In this document, unless otherwise specified, the term "or" is used to indicate a non-exclusive, e.g., "a or B" includes "a but not B", "B but not a" and "a and B". In this document, the terms "including" and "in which" are used as the plain equivalents of the respective terms "comprising" and "wherein". Also, in the following claims, the terms "comprises" and "comprising" are open-ended, i.e., a system, apparatus, article, composition, formulation, or process that includes an element in addition to the elements listed thereafter in a claim is considered to be within the scope of that claim. Furthermore, in the appended claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

The method examples described herein may be at least partially machine or computer implemented. Some examples may include a computer-readable or machine-readable medium encoded with instructions operable to configure an electronic device to perform a method as described in the above examples. Implementations of such methods may include code, e.g., microcode, assembly language code, a high-level language code, and the like. Such code may include computer readable instructions for performing various methods. The code may form part of a computer program product. Further, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, e.g., during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, Random Access Memories (RAMs), Read Only Memories (ROMs), and the like.

The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, for example, by one of ordinary skill in the art upon reviewing the above description. The abstract is provided to comply with 37c.f.r. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. This document is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing detailed description, various features may be grouped together to simplify the present disclosure. This should not be construed as an intention that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments may be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.