阅读说明：本技术 存储器系统和操作存储器系统的方法 (Memory system and method of operating memory system ) 是由 阿密特·伯曼 阿里尔·道布恰克 于 2019-09-29 设计创作，主要内容包括：公开了一种存储器系统和操作存储器系统的方法。存储器控制器被配置为：对数据的多个第一帧执行第一纠错码(ECC)编码；生成分别与数据的所述多个第一帧对应的多个增量校验子单元；通过对所述多个增量校验子单元执行第二ECC编码生成增量校验子码字,其中,增量校验子码字包括一个或多个冗余数据单元；对数据的至少一个第二帧执行第三ECC编码,使得数据的编码的至少一个第二帧是位的第一向量；确定位的第二向量,使得将位的第二向量与位的第一向量相加形成位的组合向量,其中,位的组合向量是具有增量校验子的ECC码字,增量校验子的值基于所述一个或多个冗余数据单元中的至少一个预先固定。(A memory system and a method of operating a memory system are disclosed. The memory controller is configured to: performing a first Error Correction Code (ECC) encoding on a plurality of first frames of data; generating a plurality of delta-check subunits corresponding respectively to the plurality of first frames of data; generating a delta check sub-codeword by performing a second ECC encoding on the plurality of delta check sub-units, wherein the delta check sub-codeword includes one or more redundant data units; performing a third ECC encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits; determining a second vector of bits such that adding the second vector of bits to the first vector of bits forms a combined vector of bits, wherein the combined vector of bits is an ECC codeword with an incremental syndrome whose value is fixed in advance based on at least one of the one or more redundant data units.)

1. A memory system, comprising:

a memory controller; and

a memory device for storing a plurality of data signals,

wherein the memory controller is configured to,

a first error correction code encoding is performed on a plurality of first frames of data,

generating a plurality of delta-check subunits corresponding respectively to the plurality of first frames of data,

generating a delta-syndrome codeword by performing a second error correction code encoding on the plurality of delta-syndrome units, wherein the delta-syndrome codeword comprises one or more redundant data units,

performing a third error correction code encoding on at least one second frame of data, such that the encoded at least one second frame of data is a first vector of bits,

a second vector of bits is determined such that,

adding the second vector of bits to the first vector of bits to produce a combined vector of bits, and

a value of an incremental syndrome unit generated based on the combined vector of bits is fixed in advance based on at least one of the one or more redundant data units, an

A combined vector of bits is generated.

2. The memory system of claim 1, wherein the memory controller is further configured to,

generating a Hamming product code codeword by performing extended Hamming code encoding on a column of bits among the encoded bits of the first frame of data, an

The hamming product code codeword is stored in a memory device.

3. The memory system of claim 2, wherein the memory controller is further configured to: such that the first error correction code encoding and the third error correction code encoding are bose-chaudhuri-hocquenghem encodings.

4. The memory system of claim 3, wherein the memory controller is further configured to: such that the second error correction code encoding is reed-solomon encoding.

5. The memory system according to claim 1, wherein the memory unit is a single memory unit,

wherein the memory controller is further configured to: so that the user can easily and conveniently select the required position,

the memory controller receives a plurality of information bits from an external device,

the memory controller arranges the plurality of information bits into a two-dimensional array of bits comprising a plurality of rows and a plurality of columns, an

The memory controller performs extended hamming code encoding on the plurality of columns of the array of bits to generate a plurality of columns of extended hamming code encoding of bits, wherein each frame of data among the plurality of first frames of data and the at least one second frame of data is a row of bits among the plurality of columns of extended hamming code encoding of bits such that a combined vector of the encoded plurality of first frames of data and bits is each a frame of hamming product code words, and

wherein the memory controller is further configured to: the hamming product code codeword is stored in a memory device.

6. The memory system of claim 5, wherein the memory controller is further configured to: such that the first error correction code encoding and the third error correction code encoding are bose-chaudhuri-hocquenghem encodings.

7. The memory system of claim 6, wherein the memory controller is further configured to: such that the second error correction code encoding is reed-solomon encoding.

8. A memory system, comprising:

a memory controller; and

a memory device for storing a plurality of data signals,

wherein the memory controller is configured to,

a plurality of frames of data are read from the memory device,

correcting errors in one or more frames of data among the plurality of frames of data by performing a first error correction code decoding on the plurality of frames of data,

identifying a plurality of correct frames and at least one erroneous frame among the plurality of frames of data after decoding of the first error correction code,

generating a plurality of delta-check subunits corresponding respectively to the plurality of correct frames,

generating a delta-syndrome error-correcting code word comprising information bits and redundancy bits based on the plurality of delta-syndrome units such that

The redundant bits of the delta-syndrome error correction code word are bits of at least one of the generated delta-syndrome units, and

the information bits of the delta-syndrome error-correcting code word are bits of one or more delta-syndrome units other than the at least one delta-syndrome unit among the plurality of generated delta-syndrome units, and

recovering a delta syndrome unit corresponding to the at least one erroneous frame by performing a second error correction code decoding on the delta syndrome error correction code codeword.

9. The memory system of claim 8, wherein the memory controller is further configured to: reading the plurality of frames of data from the memory device is performed by reading a hamming product code word from the memory device, wherein the hamming product code word comprises the plurality of frames of data.

10. The memory system of claim 8, wherein the memory controller is further configured to: performing Bose-Chaudhuri-Hocquenghem decoding on the at least one erroneous frame using a recovered delta check subunit, wherein the recovered delta check subunit is data that increases an error correction capability of redundant data included in the at least one erroneous frame.

11. The memory system of claim 8, wherein the memory controller is further configured to: such that the first error correction code decoding is a bose-chaudhuri-hocquenghem decoding.

12. The memory system of claim 11, wherein the memory controller is further configured to: such that the second error correction code decoding is reed-solomon decoding.

13. The memory system of claim 12, wherein the memory controller is further configured to: performing Bose-Chaudhuri-Hocquenghem decoding on the at least one erroneous frame using a recovered delta-check subunit, wherein the recovered delta-check subunit is data that increases an error correction capability of Bose-Chaudhuri-Hocquenghem redundancy data included in the at least one erroneous frame.

14. A method of operating a memory system including a memory controller and a memory device, the method comprising:

performing a first error correction code encoding on a plurality of first frames of data;

generating a plurality of delta-check subunits corresponding respectively to the plurality of first frames of data;

generating a delta-syndrome codeword by performing a second error correction code encoding on the plurality of delta-syndrome units, wherein the delta-syndrome codeword comprises one or more redundant data units;

performing a third error correction code encoding on at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits;

a second vector of bits is determined such that,

adding the second vector of bits to the first vector of bits to produce a combined vector of bits, and

a value of an incremental syndrome unit generated based on the combined vector of bits is fixed in advance based on at least one of the one or more redundant data units, an

A combined vector of bits is generated.

15. The method of claim 14, further comprising:

generating a Hamming product code codeword by performing extended Hamming code encoding on a column of bits among the encoded bits of the first frame of data, an

The hamming product code codeword is stored in a memory device.

16. The method of claim 15, wherein the first error correction code encoding and the third error correction code encoding are bose-chaudhuri-hocquenghem encodings.

17. The method of claim 16, wherein the second error correction code encoding is reed-solomon encoding.

18. The method of claim 14, further comprising:

receiving a plurality of information bits from an external device;

arranging the plurality of information bits into a two-dimensional array of bits comprising a plurality of rows and a plurality of columns;

performing extended hamming code encoding on the plurality of columns of the array of bits, thereby generating extended hamming code encoded columns of bits;

each frame of data among the plurality of first frames of data and the at least one second frame of data is a row of bits among a plurality of columns of an extended hamming code encoding of bits such that the combined vectors of the encoded plurality of first frames of data and bits are each a frame of hamming product code words; and

the hamming product code codeword is stored in a memory device.

19. The method of claim 18, wherein the first error correction code encoding and the third error correction code encoding are bose-chaudhuri-hocquenghem encodings.

20. The method of claim 19, wherein the second error correction code encoding is reed-solomon encoding.

Technical Field

The present disclosure relates to the field of data storage, and more particularly, to a method and apparatus for storing data using an Error Correction Code (ECC).

Background

When data is stored in the memory device and the stored data is read from the memory device, errors may occur. Various error correction codes may be used to detect and correct such errors. The error correction codes may include Reed-Solomon (RS) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, Low Density Parity Check (LDPC) codes, Hamming Product Codes (HPC), and the like.

As the quality of data (e.g., bit error rate) increases, the performance of error correction codes may increase. However, for some error correction codes, there is a point at which the rate at which the performance of the error correction code increases drops or flattens. This phenomenon is called error floor (error floor).

Disclosure of Invention

According to at least some example embodiments of the inventive concepts, a memory system includes a memory controller and a memory device. According to at least some example embodiments of the inventive concepts, a memory controller is configured to: performing a first Error Correction Code (ECC) encoding on a plurality of first frames of data; generating a plurality of delta-check subunits corresponding respectively to the plurality of first frames of data; generating a delta check sub-codeword by performing a second ECC encoding on the plurality of delta check sub-units, wherein the delta check sub-codeword includes the one or more redundant data units; performing a third Error Correction Code (ECC) encoding on the at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits; determining a second vector of bits such that adding the second vector of bits to the first vector of bits produces a combined vector of bits, and a value of an incremental check subunit generated based on the combined vector of bits is fixed in advance based on at least one of the one or more redundant data units; and generating a combined vector of bits.

According to at least some example embodiments of the inventive concepts, a memory system includes a memory controller and a memory device. According to at least some example embodiments of the inventive concepts, a memory controller is configured to: reading a plurality of frames of data from a memory device; correcting errors in one or more frames of data among the plurality of frames of data by performing a first Error Correction Code (ECC) decoding on the plurality of frames of data; identifying a plurality of correct frames and at least one erroneous frame among the plurality of frames of data after a first ECC decoding; generating a plurality of incremental check subunits corresponding to the plurality of correct frames respectively; generating a delta-syndrome ECC codeword including information bits and redundancy bits based on the plurality of delta-syndrome units, such that the redundancy bits of the delta-syndrome ECC codeword are bits of at least one delta-syndrome unit among the generated plurality of delta-syndrome units, and the information bits of the delta-syndrome ECC codeword are bits of one or more delta-syndrome units other than the at least one delta-syndrome unit among the generated plurality of delta-syndrome units; and recovering a delta check subunit corresponding to the at least one erroneous frame by performing a second ECC decoding on the delta check sub-ECC codeword.

According to at least some example embodiments of the inventive concepts, a method of operating a memory system including a memory controller and a memory device includes: performing a first Error Correction Code (ECC) encoding on a plurality of first frames of data; generating a plurality of delta-check subunits corresponding respectively to the plurality of first frames of data; generating a delta check sub-codeword by performing a second ECC encoding on the plurality of delta check sub-units, wherein the delta check sub-codeword includes one or more redundant data units; performing a third Error Correction Code (ECC) encoding on the at least one second frame of data such that the encoded at least one second frame of data is a first vector of bits; determining a second vector of bits such that adding the second vector of bits to the first vector of bits produces a combined vector of bits, and a value of an incremental check subunit generated based on the combined vector of bits is fixed in advance based on at least one of the one or more redundant data units; and generating a combined vector of bits.

Drawings

The above and other features and advantages of the exemplary embodiments of the inventive concept will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings. The drawings are intended to depict example embodiments of the inventive concept and should not be interpreted as limiting the intended scope of the claims. The drawings are not to be considered as drawn to scale unless explicitly indicated.

Fig. 1 is a diagram illustrating a memory system according to at least one example embodiment of the inventive concepts.

Fig. 2 illustrates an example of a product code codeword, according to at least some example embodiments of the inventive concepts.

Fig. 3A-3F illustrate operations for performing a projected bose-chaudhuri-hocquenghem (projected BCH) encoding algorithm, according to at least some example embodiments of the inventive concepts.

Fig. 4 is a block diagram illustrating a computer system including a memory system according to an example embodiment of the inventive concepts.

Fig. 5 is a block diagram illustrating a memory card according to at least one example embodiment of the inventive concepts.

Fig. 6 is a block diagram illustrating an example network system including a memory system according to at least one example embodiment of the inventive concepts.

Detailed Description

Embodiments are described in terms of functional blocks, units, and/or modules and are illustrated in the accompanying drawings as is conventional in the art of inventive concepts. Those skilled in the art will appreciate that the blocks, units, and/or modules are physically implemented via electronic (or optical) circuitry (such as logic circuitry, discrete components, microprocessors, hardwired circuitry, memory elements, wired connections, and so on), wherein the electronic (or optical) circuitry may be formed using semiconductor-based or other manufacturing techniques. Where the blocks, units, and/or modules are implemented by a microprocessor or the like, they may be programmed using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and/or software. Alternatively, each block, unit and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Furthermore, each block, unit and/or module of an embodiment may be physically separated into two or more interacting and discrete blocks, units and/or modules without departing from the scope of the inventive concept. Furthermore, the blocks, units and/or modules of an embodiment may be physically combined into more complex blocks, units and/or modules without departing from the scope of the inventive concept.

I. Overview

According to at least some example embodiments, as discussed in more detail below, using a projected BCH encoding operation during the process of ECC encoding a Hamming Product Code (HPC) codeword may result in an improvement in the error floor associated with the process of performing ECC decoding on the HPC codeword. For example, as discussed in more detail below, by generating a delta syndrome (delta syndrome) for a frame of the HPC codeword, performing ECC encoding on the generated delta syndrome itself, and storing the redundant data resulting from encoding the delta syndrome, the missing delta syndrome may be recovered during the process of decoding the HPC codeword. For example, as discussed in more detail below, when decoding the HPC codeword, the recovered delta syndrome may be used during the decoding operation to improve the error correction capability of the ECC code used to encode the HPC codeword. Thus, the error floor associated with ECC decoding operations may be improved.

Furthermore, in accordance with at least some example embodiments of the inventive concepts, as discussed in more detail below, the selected frame of the HPC codeword may be encoded in such a way that the delta syndrome corresponding to the selected frame has a desired or pre-fixed value. Therefore, by selecting the value of the redundant data generated by encoding the delta syndrome of the other frame as a predetermined value, the redundant data is substantially embedded in the delta syndrome generated for the selected frame. Thus, the need to separately store the above-described redundant data is reduced or, alternatively, eliminated. Thus, the memory requirements associated with encoding HPC codewords using the projection BCH may be advantageously reduced.

An example memory system 900 for performing the above-described encoding and/or decoding operations is discussed in more detail below in section II of this disclosure. An example Hamming Product Code (HPC) encoding operation is discussed in more detail below in section III of the present disclosure. An example projected bose-chaudhuri-hocquenghem (BCH) encoding operation is discussed in more detail below in section IV of this disclosure. An example method for generating a BCH codeword with a pre-fixed incremental syndrome value is discussed in more detail below in section V of the present disclosure. Example decoding operations are discussed in more detail below in section VI of this disclosure. An implementation example corresponding to the memory system 900 is discussed in more detail below in section VII of the present disclosure.

A memory system 900 according to at least some example embodiments of the inventive concepts will now be discussed in section II of the present disclosure below.

II. Example memory System

Fig. 1 is a diagram illustrating a memory system 900 according to at least one example embodiment of the inventive concepts. Referring to fig. 1, a memory system 900 includes a memory controller 1000 and a nonvolatile memory device 2000.

The non-volatile memory device 2000 may be, but is not limited to: flash memory devices, NAND flash memory devices, phase change ram (pram), ferroelectric ram (fram), magnetic ram (mram), and the like. According to at least one example embodiment of the inventive concepts, the non-volatile memory device 2000 may include a plurality of NAND flash memory devices. The nonvolatile memory device 2000 may have a planar structure or a three-dimensional (3D) memory cell structure having stacked memory cells.

Memory device 2000 may include memory cell array 2100, X-decoder 121, voltage generator 125, I/O buffer 124, page buffer 123, and control logic 126, where each of memory cell array 2100, X-decoder 121, voltage generator 125, I/O buffer 124, page buffer 123, and control logic 126 may be implemented as one or more circuits. The memory device may also include input/output (I/O) pads (pads, also known as pads or pads) 127.

The memory cell array 2100 includes a plurality of word lines and a plurality of bit lines. Each memory cell in memory cell array 2100 can be implemented as a non-volatile memory cell. For example, each memory cell in memory cell array 2100 can have a floating gate or charge storage layer (such as a charge trapping layer).

The memory cell array 2100 may include a plurality of blocks and a plurality of pages. One block includes a plurality of pages. A page may be a unit of a program operation and a read operation, and a block may be a unit of an erase operation. For example, the memory cell array 2100 includes a first block 2120 and a second block 2130. As shown in fig. 1, the first block 2120 includes pages 1 to N, and the second block 2130 includes pages 1 to N, where N is a positive integer greater than 1.

Control logic 126 controls the overall operation of memory device 2000. When receiving a command CMD from the memory controller 1000, the control logic 126 interprets the command CMD and controls the memory device 2000 to perform an operation (e.g., a program operation, a read retry operation, or an erase operation) according to the interpreted command CMD.

According to at least one example embodiment, control logic 126 may include a hardware-implemented processor configured to execute commands based on the command CMD. According to at least one example embodiment of the inventive concepts, the control logic 126 may include a memory unit for storing instructions in addition to the processor, wherein the steps, when executed by the processor included in the control logic 126, cause the processor to perform certain operations. According to at least one example embodiment of the inventive concepts, any of the operations described herein as being performed by memory device 2000 may be performed by control logic 126 (e.g., by a processor included in control logic 126 that drives firmware stored in a memory unit included in control logic 126), or under the control of control logic 126. Alternatively, control logic 126 may be circuitry (e.g., an Application Specific Integrated Circuit (ASIC)) that is physically programmed in accordance with hardware to perform or control any of the operations described herein as being performed by memory device 2000.

The X-decoder 121 is controlled by the control logic 126 and drives at least one word line of a plurality of word lines in the memory cell array 2100 according to a row address.

The voltage generator 125 is controlled by the control logic 126 to generate one or more voltages required for a write operation, a read operation, or an erase operation, and to supply the generated voltages to one or more rows selected by the X-decoder 121.

The register 128 is controlled by the control logic 126, and the register 128 is a space storing information input from the memory controller 1000, and may include a plurality of latches. For example, the register 128 may group read voltage (and/or reference voltage) information and store the information in the form of a table.

The page buffer 123 is controlled by the control logic 126 and operates as a sense amplifier or a write driver according to an operation mode (e.g., a read operation or a write operation).

The I/O pad 127 and the I/O buffer 124 may serve as an I/O path for data exchanged between an external device (e.g., the memory controller 1000 or a host) and the memory device 2000. The I/O pads 127 are connected to the memory controller 1000 through a memory system bus. Data and/or commands may be output from memory device 2000 to memory controller 1000 via I/O pads 127 and a memory system bus, or received from memory controller 1000 at memory device 2000.

According to at least some example embodiments of the inventive concepts, the memory device 2000 operates in response to commands and/or control signals generated by the memory controller 1000. Accordingly, operations described in this disclosure as being performed, executed, or controlled by memory device 2000 may additionally or alternatively be referred to as operations performed, executed, or controlled by memory controller 1000.

The memory controller 1000 may include a microprocessor 111, a Read Only Memory (ROM)113, a Random Access Memory (RAM)112, an encoder 1100, a decoder 1200, a memory interface 116, and a controller bus 118. The elements 111 to 116 of the memory controller 1000 may be electrically connected to each other through a controller bus 118.

The microprocessor 111 controls the overall operation of the memory system 900 including the memory controller 1000. The microprocessor 111 is a circuit that controls other elements by generating control signals. When power is supplied to the memory system 900, the microprocessor 111 drives firmware (e.g., stored in the ROM 113) for operating the memory system 900 on the RAM 112, thereby controlling the overall operation of the memory system 900. According to at least one example embodiment of the inventive concepts, the microprocessor 111 may also issue commands or output control signals to control the operation of other elements of the memory controller 1000, including, for example, some or all of the ROM 113, RAM 112, encoder 1100, decoder 1200, memory interface 116, and control bus 118. According to at least one example embodiment of the inventive concepts, any of the operations described herein as being performed by the memory controller 1000 may be performed by the microprocessor 111 (e.g., by a microprocessor driving the above-mentioned firmware), or under the control of the microprocessor 111.

Although the driver firmware code of the memory system 900 is stored in the ROM 113, one or more example embodiments of the inventive concepts are not limited thereto. The firmware code may also be stored in a portion of the memory system 900 other than the ROM 113. Thus, the control or intervention of the microprocessor 111 may include not only direct control of the microprocessor 111 but also intervention of firmware as software driven by the microprocessor 111.

Alternatively, the microprocessor 111 may be circuitry (e.g., (ASIC)) that is physically programmed in accordance with hardware to perform or control any of the operations described herein as being performed by the memory controller 1000.

The RAM 112, which is a memory used as a buffer, may store initial commands, data, and various variables input from the host or the microprocessor 111, or store data output from the memory device 2000. According to at least some example embodiments of the inventive concepts, the RAM 112 may store data input to the memory device 2000, various parameters and variables, and data output from the memory device 2000, various parameters and variables.

The memory interface 116 may serve as an interface between the memory controller 1000 and the memory device 2000. The memory interface 116 is connected to the I/O pad 127 of the memory device 2000 via a memory system bus and can exchange data with the I/O pad 127 via the memory system bus. Further, memory interface 116 may create commands applicable to memory device 2000 and provide the created commands to I/O pads 127 of memory device 2000. Memory interface 116 provides one or more commands to be executed by memory device 2000 and one or more addresses ADD for memory device 2000.

According to at least one example embodiment of the inventive concepts, decoder 1200 may be an Error Correction Code (ECC) decoder and encoder 1100 may be an ECC encoder. According to at least one example embodiment of the inventive concepts, the decoder 1200 and the encoder 1100 perform error bit correction. The encoder 1100 may generate data to which one or more parity bits and/or redundancy bits are added by performing error correction coding on the data before the data is provided to the memory device 2000. One or more parity bits and/or redundancy bits may be stored in the memory device 2000.

The decoder 1200 may perform error correction decoding on the output data, determine whether the error correction decoding is successful based on a result of the error correction decoding, and output an instruction signal based on a result of the determination. The read data may be sent to the decoder 1200, and the decoder 1200 may use one or more parity bits and/or redundant bits to correct the erroneous bits of the data. When the number of erroneous bits exceeds the limit of erroneous bits that can be corrected, the decoder 1200 cannot correct the erroneous bits, resulting in failure of error correction.

Each of the encoder 1100 and the decoder 1200 may include an error correction circuit, system, or device. The encoder 1100 and decoder 1200 may perform error correction using, for example, one or more of a Low Density Parity Check (LDPC) code, a bose-chaudhuri-hocquenghem (BCH) code, a turbo code, a reed-solomon (RS) code, a convolutional code, a Recursive Systematic Code (RSC), and a coded modulation such as Trellis Coded Modulation (TCM) or Block Coded Modulation (BCM). Further, as discussed in more detail below, the encoder 1100 and decoder 1200 may perform error correction using Hamming Product Code (HPC).

Example encoding operations in accordance with at least some example embodiments of the inventive concepts will now be discussed in section III of the present disclosure below.

III, example encoding operations

In general,the product code (or iterative code) is a serial concatenated code. The concept of product codes is relatively simple and relatively efficient, by using two or more short block codes (block codes) to construct very long block codes. For example, the product code P may be defined asWherein, C¹And C²Respectively, a first system linear block code and a second system linear block code, a first code C¹Having a parameter (n)₁，k₁，₁) Second code C²Having a parameter (n)₂，k₂，₂)，n_i、k_iAnd_irespectively representing the codeword length, the number of information bits and the minimum hamming distance. One type of product code is the Hamming Product Code (HPC). For example, when the first code C¹And a second code C²In both extended hamming codes, the product code P is the HPC. Encoding the data using HPC produces HPC codewords. FIG. 2 illustrates an example of an HPC codeword 200. The process of encoding data using HPC will now be discussed below with reference to Algorithm 1 and HPC codeword 200.

The operation of algorithm 1 is shown below using pseudo code. According to at least some example embodiments of the inventive concepts, each operation of algorithm 1 may be performed by memory controller 1000 (e.g., using microprocessor 111) or under the control of memory controller 1000.

Algorithm 1 will be discussed for the following case: first code C¹And a second code C²Are all extended Hamming codes, k₁＝183，k₂＝183，n₁＝192，n₂192. Thus, the parameter of the product code P generated is n ═ n₁×n₂、 k＝k₁×k₂、＝₁×₂The code rate R is defined by R ═ R₁×R₂Wherein R is_iIs the ith code CⁱThe code rate of (2). Furthermore, in this disclosure, "redundant" data,The "redundant" bits, etc. may also be referred to as "parity" data, "parity" bits, etc. Furthermore, in this disclosure, "redundant" data, "redundant" bits or "parity" data, "parity" bits, etc. may be generally referred to as "overhead" (e.g., of an ECC code similar to a BCH code or an RS code).

Referring to algorithm 1, in operation (a1), memory controller 1000 receives information bits 210 (e.g., from an external device) and arranges information bits 210 into k₁Row and k₂And (4) columns. Thus, as illustrated by HPC codeword 200 in FIG. 2, memory controller 1000 arranges information bits 210 into 183 columns and 183 rows. In this disclosure, a row of data (e.g., a row of HPC codeword 200) may also be referred to as a "frame".

In operation (a2), the memory controller 1000 uses the second code C²To k is paired₁The rows are encoded. For example, referring to HPC codeword 200 in FIG. 2, memory controller 1000 uses second code C ²183 rows of information bits 210 are encoded to generate 183 corresponding rows of redundant data shown in fig. 2 as redundant rows 230. In the example shown in fig. 2, 183 redundant rows 230 each include 9 redundant bits. For example, because, as described above, the second code C²Is an extended hamming code, the 9 redundant bits may include 8 extended hamming code parity bits and one additional parity bit, as a total of 8+1 to 9 redundant bits. Thus, each row of HPC codeword 200 includes n₂(i.e., 183+9 ═ 192 ═ n₂) A bit. Thus, HPC codeword 200 comprises n₂And (4) columns.

In operation (a3), the memory controller 1000 uses the first code C¹To n₂The columns are encoded. For example, referring to HPC codeword 200 in FIG. 2, memory controller 1000 uses first code C ¹183 columns of information bits 210 are encoded, resulting in 183 redundant columns 220. In the example shown in fig. 2, 183 redundant columns 220 each include 9 bits. In addition, the memory controller 1000 uses the first code C¹Bits of 9 columns included in the 183 redundant rows 230 are encoded, thereby generating a check-on-check block 240 of 9 × 9 bits.

Albeit at the topAlgorithm 1 is described with reference to an example case in which a row of information bits 210 is first encoded (e.g., in operation (a 2)), after which columns of the encoded row are encoded (e.g., in operation (A3)), but operation (A3) may be performed before operation (a2) (i.e., operation (A3) may include using code C, according to at least some example embodiments of the inventive concepts¹To k is paired₂The column is encoded, and operation (A2) may include using code C after operation (A3)²To n₁The rows are encoded).

According to at least some example embodiments of the inventive concepts, memory controller 1000 stores HPC codeword 200 on memory device 2000 after operations (A1) through (A3). For example, memory controller 1000 may send HPC codeword 200 and one or more write commands to memory device 2000, and memory device 2000 may respond to the one or more write commands by writing HPC codeword 200 to memory cell array 2100 (e.g., writing HPC codeword 200 to a memory page of memory cell array 2100).

As described above, the parameter of the generated product code P is n ═ n₁×n₂、k＝k₁×k₂、＝₁×₂The code rate R is defined by R ═ R₁×R₂Wherein R is_iIs the ith code CⁱThe code rate of (2). Thus, by combining short codes having a small minimum hamming distance, a relatively long block code having a relatively large minimum hamming distance can be constructed. Given the process used to construct product code P, HPC codeword 200 is the last (n)₂-k₂) Column is the first code C¹The code word of (1). Using a matrix generator, the last (n) of HPC codeword 200 may be shown₁-k₁) A line is a second code C²The code word of (1). Thus, all rows of HPC codeword 200 are second code C²And all columns of HPC codeword 200 are first code C¹The code word of (1).

Operation of algorithm 1 (a2) may be performed using projected BCH encoding, which will now be discussed in more detail in section IV of the present disclosure below, in accordance with at least some example embodiments of the inventive concepts.

IV, projection BCH coding

According to at least some example embodiments of the inventive concepts, the first and second images may be combined, for example, according to algorithm 2 discussed below,projection (projector)The BCH encoding algorithm is applied to, for example, the rows of HPC codewords 200. For example, in accordance with at least some example embodiments of the inventive concepts, in addition to the extended hamming code encoding discussed above with reference to operation (a2) of algorithm 1,projection (projector)The BCH encoding algorithm is applied, or alternatively,projection (projector)The BCH encoding algorithm replaces the extended hamming code encoding discussed above with reference to operation (a2) of algorithm 1. For example, according to at least some example embodiments of the inventive concepts, the operation of algorithm 1 (a2) includes: k for data corresponding to HPC codeword 200₁For performing algorithm 2 discussed belowProjection (projector)BCH coding operations (i.e., not for k)₁Row performs extended hamming code encoding); and generates and stores parity bits for each row of HPC codeword 200. The parity bits may be generated according to a known method.

Further, in accordance with at least some example embodiments of the inventive concepts, with respect to operation (a3) of algorithm 1, extended hamming code encoding, discussed above with reference to algorithm 1, is performed on columns of the codeword (e.g., HPC codeword 200), but the projected BCH encoding, discussed below with respect to algorithm 2, is not applied to the columns of the codeword (e.g., HPC codeword 200).

Thus, according to at least some example embodiments of the inventive concept, in algorithm 1: the projected BCH encoding according to algorithm 2 is performed on the rows of information bits of the codeword by memory controller 1000, and then the extended hamming code encoding is performed on the columns of bits from among the rows of projected BCH encoded information bits by memory controller 1000, thereby generating a two-dimensional HPC codeword.

Furthermore, according to at least some other example embodiments of the inventive concept, in algorithm 1: extended hamming code encoding is performed on columns of information bits of the codeword by memory controller 1000, and then projected BCH encoding according to algorithm 2 is performed on rows of bits from among the extended hamming code encoded columns of information bits by memory controller 1000, thereby generating a two-dimensional HPC codeword.

Projection BCH coding algorithm, as discussed in more detail below with reference to Algorithm 2Including performing BCH encoding on rows of data among the information bits 210, thereby generating BCH redundant data for each row. In addition, the projected BCH encoding algorithm includes generating an incremental syndrome (ds) for improving the error correction capability of the BCH redundant data. Each incremental syndrome may correspond to one of a plurality of stages (stages) i. The total number of erroneous bits per row that can be corrected appropriately with the help of the corresponding incremental syndrome of stage i is denoted t_i(or ti). In addition, as discussed in more detail below with reference to algorithm 2, the same level of incremental syndromes are concatenated and encoded using an RS code, thereby generating RS redundancy data. The error correction capability of the RS code varies with the level variation of the encoded delta syndrome. The total number of error rows of incremental parity sub-data of a stage that can be properly corrected using the above-mentioned RS redundancy data for stage i is denoted as F_i(or Fi).

Thus, the parameters of the projection BCH coding algorithm can be represented by vectors F and t. For the sake of simplicity, as shown in fig. 3A to 3F, algorithm 2 will be explained below with reference to only 8 frames of data of codeword 300 (i.e., first frame 31 to eighth frame 38). Further, algorithm 2 will be explained below with reference to examples of vector F ═ F0F 1F 2 ═ 831 ] and vector t ═ t0 t1 t2 ═ 679.

Although algorithm 2 is explained below with reference to 8 frames of information bits included in codeword 300 for simplicity, algorithm 2 may be performed for more than 8 frames of data. For example, memory controller 1000 may execute algorithm 2 for 192 frames of bits included in HPC codeword 200 shown in FIG. 2.

The operation of algorithm 2 is shown below using pseudo code. According to at least some example embodiments of the inventive concepts, each operation of algorithm 2 may be performed by memory controller 1000 (e.g., using microprocessor 111) or under the control of memory controller 1000.

Algorithm 2

According to at least some example embodiments of the inventive concepts, Algorithm 2Has three parts: part 0, part 1 and part 2. Referring to part 0, in operation (B1), the memory controller 1000 encodes F0-F1 frames with an error correction capability of t0 bits. For example, F0-F1-8-3-5. Accordingly, as shown in fig. 3A, the information bits (INFO)310 of the first to fifth frames 31 to 35 (e.g., the first F0-F1 ═ 5 frames) are encoded using a BCH code capable of correcting t0 bits, thereby generating BCH redundant data 315. Accordingly, as shown in item (b) of fig. 3A, m is generated for each of the first to fifth frames 31 to 35_BCH× t0 bits of BCH redundant data, where m_BCHIndicates the number of bits in a Galois field (Galois field) corresponding to the BCH code. In the examples shown in fig. 3A to 3F, m_BCH8. Thus, for each of the first frame 31 to the fifth frame 35, the memory controller 1000 generates m_BCH× t 0-8 × 6-48 bit BCH redundancy data in this disclosure, the value m_BCHSometimes also referred to simply as m.

Then, referring to part 1 of algorithm 2, in operation (B2), memory controller 1000 generates a delta syndrome for the F0-F1 frames. For example, as shown in item (C) of fig. 3B, for each of the first F0-F1 ═ 5 frames (i.e., the first frame 31 through the fifth frame 35), the memory controller 1000 generates a level 1 delta syndrome 317A, a first level 2 delta syndrome 317B, and a second level 2 delta syndrome 317C. In this disclosure, the incremental syndrome may also be referred to as "DS" or "DS". In accordance with at least some example embodiments of the inventive concepts, as shown in fig. 3B, stage 1ds 317A may include F0-F1 ═ 5 separate delta check subunits, and may be used during BCH decoding operations to increase the error correction capability of the BCH redundancy data 315 from t0 bits to t1 bits. According to at least some example embodiments of the inventive concepts, as shown in fig. 3B, first stage 2ds 317B and second stage 2ds 317C may each include F0-F1 ═ 5 individual ds cells, and may be used with stage 1ds 317A during BCH decoding operations to increase the error correction capability of BCH redundancy data 315 to t2 bits. ds 317A to ds 317C may be generated according to known methods for generating ds.

In operation (B3), the memory controller 1000 generates F1 cells of reed-solomon (RS) code overhead (i.e., F1 cells of RS redundancy data) for t1-t0 columns of ds. For example, according to at least some example embodiments of the inventive concepts, as shown in item (d) of fig. 3B, memory controller 1000 may cascade individual cells of stage 1ds 317A (i.e., the first [ t1-t0 ═ 7-6 ═ 1] column ds in ds 317A-ds 317C) and encode the cascaded cells of stage 1ds 317A using RS codes. As a result of the encoding, the memory controller 1000 generates an RS overhead 320. As shown in item (d) in fig. 3B, the RS overhead 320 includes F1 ═ 3 elements of RS overhead (first to third RS overhead elements 320A, 320B, and 320C). According to at least some example embodiments of the inventive concepts, each of the first to third RS overhead cells 320A to 320C may have the same size (e.g., the same number of bits) as an individual ds cell included in ds 317A to ds 317C. In this disclosure, the term "RS overhead unit" is considered synonymous with "RS redundant data unit" and may also be referred to as "RS redundant data unit". According to at least some example embodiments of the inventive concepts, each block labeled "ds" in fig. 3B-3F represents a separate ds cell. According to at least some example embodiments of the inventive concepts, the single incremental syndrome may include one or more ds cells. For example, according to at least some example embodiments of the inventive concepts, the combined first stage 2ds 317B and second stage 2ds 317C may be considered a plurality of stage 2 delta syndromes that each include 5 ds cells.

In operation (B4), for an F1-F2 frame, the memory controller 1000 encodes the frame using a code having an error correction capability of t1 bits and sets the result of the encoding to vector X (where vector X may be referred to as vector X). For example, memory controller 1000 may encode F1-F2-3-1-2 frames using a BCH code with error correction capability of t 1-7 bits. According to at least some example embodiments of the inventive concepts, the F1-F2 frame encoded in operation (B4) may be the next F1-F2 (e.g., 2) frame after the F0-F1 (e.g., 5) frame that has been encoded in operation (B1). For example, in the example shown in fig. 3A to 3F, in operation (B4), the memory controller 1000 encodes the information bits 310 of the sixth and seventh frames 36 and 37, generating an intermediate BCH redundancy number as shown in item (e) of fig. 3CAccordingly, 332. As shown in item (e) of FIG. 3C, the intermediate BCH redundancy data 332 includes m for each of the sixth frame 36 and the seventh frame 37_BCH× t 1-8 × 7-56 bits the memory controller 1000 may then set the information bits 310 and the intermediate redundancy data 332 of each of the sixth and seventh frames 36, 36 to a vector x (i.e., a vector corresponding to the sixth and seventh frames 36, 37, respectively.) for example, the sixth frame 36 of item (e) shown in fig. 3C may correspond to a vector x₆The seventh frame 37 of item (e) shown in FIG. 3C may correspond to vector x₇。

In operation (B5), the memory controller 1000 computes a plurality of Y vectors (where vector Y may be referred to as vector Y) for the F1-F2 frames. According to at least some example embodiments of the inventive concept, as will be discussed in more detail in section V of the present disclosure below, the y-vector y calculated in operation (B5) for the r-th (r being a positive integer) frame_rIs when the corresponding x-vector x set for the r-th frame in operation (B4)_rWhen added, produces a combined vector v of the r-th frame_rSuch that the vector v is combined for the r frame_rA vector is generated in which the value of ds for one or more cells matches an expected (e.g., pre-fixed) value. Specifically, as will be discussed in more detail below with reference to fig. 3C and 3D, in operation (B5), memory controller 1000 determines a frame 6 y vector and a frame 7 y vector (vector y)₆334A and vector y₇334B) So that at frame 6 the y vector y₆334A and frame 7 y vector y₇334B respectively correspond to the x-vector x of the 6 th frame₆And frame 7 x vector x₇(i.e., the data for frame 36 and frame 37 of item (e) of FIG. 3C) for a sixth frame 36 (i.e., the combined vector v)₆) The resulting sum of values for stage 1ds units is for the seventh frame 37 (i.e., the combined vector v₇) The generated value of the stage 1ds cell will be equal to the value of the first RS overhead cell 320A and the value of the second RS overhead cell 320B, respectively, generated in operation (B3).

Referring again to operation (B5), as shown in item (f) of fig. 3C, the memory controller 1000 may generate a 6 th frame y vector y corresponding to the sixth frame 36 using the first RS overhead unit 320A₆334A, using the second RS overhead unit 320B to generate the seventh frame 37 pairCorresponding frame 7 y vector y₇334B. Then, in operation (B6), as shown in item (g) in fig. 3C, the memory controller 1000 will store the y vectors corresponding to the sixth frame 36 and the seventh frame 37 (i.e., the 6 th frame y vector y)₆334A and frame 7 y vector y₇334B) And x vectors (x generated in operation (B4) of algorithm 2) corresponding to the sixth frame 36 and the seventh frame 37₆And x₇(i.e., the information bits 310 and the intermediate BCH redundancy data 332 corresponding to the sixth and seventh frames 36, 37)) to generate a combined vector v corresponding to the sixth and seventh frames 36, 37, respectively₆And a combined vector v₇. Combined vector v₆Includes information bits 310 corresponding to the sixth frame 36 and final BCH redundancy data 333, and combines the vector v₇Including information bits 310 corresponding to the seventh frame 37 and final BCH redundancy data 333. As shown in item (f) of FIG. 3C, the final BCH redundancy data 333 may include first final BCH redundancy data 336A corresponding to the sixth frame 36 and second final BCH redundancy data 336B corresponding to the seventh frame 37. At this point, as discussed above, if the stage 1ds unit is based on the sixth frame 36 and the seventh frame 37 (i.e., the combined vector v₆And a combined vector v₇) Generated, then the value of the stage 1ds unit will be equal to the value of the first RS overhead unit 320A and the value of the second RS overhead unit 320B, respectively.

Then, referring to part 2 of algorithm 2, in operation (B7), memory controller 1000 generates a delta syndrome for the F1-F2 frames. For example, as shown in item (h) of fig. 3D, for each of the F1-F2-2 frames (i.e., the next 2 frames (sixth frame 36 through seventh frame 37) after the F0-F1-5 frame for which the delta syndrome was generated in operation (B2)), memory controller 1000 generates first RS overhead unit 320A and second RS overhead unit 320B as level 1 delta syndromes, generates first level 2 delta syndrome 337A, and generates second level 2 delta syndrome 337B. According to at least some example embodiments of the inventive concepts, as shown in fig. 3D, the first stage 2ds 337A and the second stage 2ds 337B may each include F1-F2 ═ 2 individual ds cells, and may be used during a BCH decoding operation to increase the error correction capability of the final BCH redundancy data 333 of the sixth frame 36 and the seventh frame 37 from t1 bits to t2 bits. ds 337A-ds 337B may be generated according to known methods for generating ds.

In operation (B8), the memory controller 1000 generates F2 cells of reed-solomon (RS) code overhead (i.e., F2 cells of RS redundancy data) for t2-t1 columns of ds. For example, as shown in item (i) of fig. 3D, the memory controller 1000 may generate the first stage 2ds 347A including the first stage 2ds unit of each of the first frame 31 to the seventh frame 37. Further, as also shown in item (i) of fig. 3D, the memory controller 1000 may generate the second level 2ds 347B including the second level 2ds unit of each of the first frame 31 to the seventh frame 37. Further, according to at least some example embodiments of the inventive concepts, as shown in item (i) of fig. 3D, the memory controller 1000 may encode the lower [ t2-t1 ═ 9-7 ═ 2] column of ds that has not been encoded using an RS code. For example, memory controller 1000 may concatenate seven individual units of first stage 2ds 347A and encode the concatenated units of first stage 2ds 347A using RS codes, thereby generating F2 ═ 1 fourth RS overhead units 350A. Furthermore, memory controller 1000 may concatenate seven individual units of second stage 2ds 347B and encode the concatenated units of second stage 2ds 347B using RS codes, thereby generating F2 ═ 1 fifth RS overhead units 350B. According to at least some example embodiments of the inventive concepts, each of the fourth to fifth RS overhead units 350A to 350B may have the same size (e.g., the same number of bits) as an individual ds unit included in ds 347A to ds 347B.

In operation (B9), for an F2 frame, the memory controller 1000 encodes the frame using a code having an error correction capability of t2 bits, and sets the result of the encoding to a vector x. For example, memory controller 1000 may encode the F2 ═ 1 frame using a BCH code with error correction capability of t2 ═ 9 bits. According to at least some example embodiments of the inventive concepts, the F2 frame encoded in operation (B9) may be a next F2 (e.g., 1) frame, among F0 ═ 8 frames (i.e., all of the first to eighth frames 31 to 38), which has not been encoded. For example, in the example shown in fig. 3A to 3F, as shown in item (j) of fig. 3E, in operation (B9), memory controller 1000 encodes the current iteration of algorithm 2 that has not yet been encoded according toThe information bits 310 of the unique frame (e.g., eighth frame 38) are encoded to generate intermediate BCH redundancy data 362. As shown in item (j) of FIG. 3E, for the eighth frame 38, the intermediate BCH redundancy data 362 includes m_BCH× t 2-8 × 9-72 bits the memory controller 1000 may then set the information bits 310 and the intermediate redundancy data 362 of the eighth frame 38 to the x-vector x₈。

In operation (B10), the memory controller 1000 calculates a y vector and sets the vector yvec as vector y for each of the F2 frames. According to at least some example embodiments of the inventive concepts, as will be discussed in more detail in section V of the present disclosure below, the y-vector y calculated for the r-th frame in operation (B10)_rIs when the corresponding x-vector x set for the r-th frame in operation (B9)_rWhen added, generates a combined vector v_rSuch that for vector v_rA vector of values of one or more cells of the generated ds that match expected (e.g., pre-fixed) values.

In particular, as will be discussed in more detail below with reference to fig. 3E, in operation (B10), memory controller 1000 determines a third y-vector y₈364 in vector y₈364 and x vector x₈(i.e., the data of the eighth frame 38 of item (j) of FIG. 3E) is added, followed by a comparison of the eighth frame 38 (i.e., the combined vector v)₈) The generated value of the stage 1ds cell, the first stage 2ds cell, and the second stage 2ds cell will be equal to the value of the third RS overhead cell 320C generated in operation (B3), the value of the fourth RS overhead cell 350A generated in operation (B8), and the value of the fifth RS overhead cell 350B, respectively.

Referring again to operation (B10), as shown in item (k) of fig. 3E, the memory controller 1000 may generate a third y-vector y corresponding to the eighth frame 38 using the third, fourth, and fifth RS overhead elements 320C, 350A, and 350B₈364. Then, in operation (B11), as shown in item (l) in fig. 3E, the memory controller 1000 will determine the y-vector corresponding to the eighth frame 38 (i.e., the third y-vector y)₈364) And an x-vector corresponding to the eighth frame 38 (x-vector x generated in operation (B9) of algorithm 2)₈(i.e., corresponding to the eighth frame 38)Information bits 310 and intermediate BCH redundancy data 362)) to generate a combined vector v corresponding to the eighth frame 38₈. Combined vector v₈Including information bits 310 corresponding to the eighth frame 38 and final BCH redundancy data 363. At this time, as discussed above, if the stage 1ds units, the first stage 2ds units, and the second stage 2ds units are based on the eighth frame 38 (i.e., the combined vector v)₈) Generated, then the value of the stage 1ds cell, the value of the first stage 2ds cell, and the value of the second stage 2ds cell will be equal to the values of the third through fifth RS overhead cells 320C, 350A, and 350B, respectively.

FIG. 3F shows an example codeword 300 resulting from performing a projected BCH encoding algorithm according to at least some example embodiments of the inventive concepts using Algorithm 2 on the information bits of the first through eighth frames 31 through 38. As shown in fig. 3F, according to at least some example embodiments of the inventive concepts, the amount of information bits in a frame may decrease as the amount of redundant data (e.g., BCH redundant data 313 corresponding to the first through fifth frames 31 through 35, final BCH redundant data 333 corresponding to the sixth and seventh frames 36 and 37, and final BCH redundant data 363 corresponding to the eighth frame 38) in the frame increases.

Next, an example method for generating a BCH codeword with a desired or optionally pre-fixed incremental syndrome value is discussed below in section V of the present disclosure.

V, example method for generating BCH codewords with pre-fixed incremental syndrome values

The problem to be solved can be viewed as determining how to create the BCH codeword such that the incremental syndrome value of the BCH codeword is guaranteed to have a desired or optionally pre-fixed (i.e., predetermined) value.

Example solutions to the above-mentioned problem will now be discussed below with reference to expressions 1 to 7. In the following expressions 1 to 7, the symbol a_{[B x C]}Or A_{B x C}Representing a matrix (or vector) a having a size B × C.

One solution to the above-mentioned problem of determining how to create a BCH codeword such that its incremental syndrome value has a desired or optionally pre-fixed value may be defined with reference to the following constraints:

let v be [ u, p ]]Is an n-bit vector, where u is a data bit and p is a parity bit (e.g., having m)_BCH×t₁The size of the bit); and is

The following expression 1 is satisfied.

Referring to expression 1, the value Δ s represents an incremental syndrome constraint. For example, in accordance with at least some example embodiments of the inventive concept, the delta syndrome constraint Δ s may be associated with a desired or optionally predetermined delta syndrome value as described above. For example, in accordance with at least some example embodiments of the inventive concept, the delta syndrome constraint Δ s itself may be the desired or optionally predetermined delta syndrome value described above.

According to at least some example embodiments of the inventive concept, the above-mentioned solution may be implemented by decomposing the problem into two parts:

1. the information part x should satisfy the following expression 2.

2. Constraining part

The following expression 3 should be satisfied.

Can be obtained by pairing a compound having m according to the following expression 4_BCH×t₁The data u of the parity bits is encoded to realize satisfaction of expression 2.

Satisfying expression 3 may be achieved by an algebraic solution. For example, according to at least some example embodiments of the inventive concept,is a full rank. Therefore, expression 5 can be determined as shown below.

Accordingly, the following expression 6 can be derived.

As a result, the y value corresponding to the incremental syndrome constraint Δ s can be determined according to the following expression 7.

Referring to expression 7 above, according to at least some example embodiments of the inventive concepts, the memory controller 1000 may store a matrix U for each error correction capability t. According to at least some example embodiments of the inventive concepts, the matrix U is a predetermined matrix. For example, the matrix U may be determined and stored in the memory controller 1000 before the operations of algorithm 1 and/or algorithm 2 are performed. According to at least some example embodiments of the inventive concepts, the matrix U is determined (e.g., offline) by a manufacturer or user of the memory controller 1000 and/or the memory system 900, and the matrix U is stored (e.g., in the ROM 113 and/or the RAM 112) by the memory controller 1000 before the memory controller 1000 performs ECC decoding operations. According to at least some example embodiments of the inventive concept, the matrix U discussed in this disclosure may be determined according to known methods. For example, according to at least one example embodiment of the inventive concept, the matrix U discussed in this disclosure may be determined using the method described in U.S. patent application publication No. 2019/0007062.

Thus, according to at least some example embodiments of the inventive concepts, memory controller 1000 may determine the y vector discussed above with reference to algorithm 2 based on the delta syndrome constraint Δ s and an appropriate U matrix that may be stored in memory controller 1000. For example, a discussion of applying the method for generating a BCH codeword having a pre-fixed delta syndrome value according to at least some example embodiments to operations (B4) to (B6) and operations (B9) to (B11) of algorithm 2 will now be provided below.

As noted in the discussion of algorithm 2 above, as shown in item (e) of fig. 3C, in operation (B4), an x-vector x is generated by encoding the sixth frame 36 and the seventh frame 37 using BCH codes with error correction capability of t1 ═ 7 bits₆And x₇。

By applying the above expression 2 to the operation (B4), it can be seen that

And is(wherein, x₆And x₇Is a row vector of length n, H_t1Is of size m.t₁× n).

As indicated in the discussion of algorithm 2 above, as shown in fig. 3B-3D, in operation (B5), memory controller 1000 determines frame 6 y vector y₆334A and frame 7 y vector y₇334B, so that the y vector y of the 6 th frame₆334A and frame 7 y vector y₇334B respectively correspond to the x-vector x of the 6 th frame₆And frame 7 x vector x₇Adding them to generate the 6 th frame combined vector v₆And 7 th frame combined vector v₇And combining the vector v for the 6 th frame₆The value of the generated stage 1ds unit will be equal to the value of the first RS overhead unit 320A, combining vector v for frame 7₇The value of the generated stage 1ds unit will be equal to the value of the second RS overhead unit 320B. Further, in operation (B6),memory controller 1000 decodes a frame 6 x vector x by dividing the frame₆And y vector y₆Are added together to generate a 6 th frame combination vector v₆And memory controller 1000 by encoding the 7 th frame x vector x₇And y vector y₇Are added together to generate a 7 th frame combination vector v₇。

By applying expression 7 above to the operation (B5), the memory controller 1000 can determine the 6 th frame y vector y by the following expression 8₆And frame 7 y vector y₇To perform operation (B5):

y₆＝Δs₆·U_t1

y₇＝Δs₇·U_t1. (expression 8)

In accordance with at least some example embodiments of the inventive concept, in expression 8, the frame 6 delta syndrome constraint Δ s₆Defined by the value of the first RS overhead element 320A predetermined in operation (B3); 7 th frame delta syndrome constraint Δ s₇Defined by the value of the second RS overhead element 320B, which is also predetermined in operation (B3); matrix U_t1May be stored in memory controller 1000 and have a size m (t)₁-t₀)×m·t₁(i.e., m.DELTA.t × m.t)₁) The pre-computed matrix of (a).

Thus, the memory controller 1000 can determine the 6 th frame combination vector v by the following expression 9₆And 7 th frame combined vector v₇To perform operation (B6):

v₆＝[0 y₆]+x₆

v₇＝[0 y₇]+x₇(expression 9)

Wherein the frame 6 y vector y is shown, for example, in items (f) and (g) of FIG. 3C₆And frame 7 y vector y₇All can use n-m.t₁And zero padding.

As noted in the discussion of algorithm 2 above, as shown in item (j) of fig. 3E, in operation (B9), the eighth frame 38 is encoded by using a BCH code with error correction capability of t2 ═ 9 bitsThe code generates a frame 8 x vector x₈。

When the above expression 2 is applied to the operation (B9), it can be seen that

(wherein, x₈Is a row vector of length n, H_t2Is of size m.t₂× n).

As indicated in the discussion of algorithm 2 above, as shown in fig. 3D-3E, in operation (B10), memory controller 1000 determines the 8 th frame y vector y₈364, such that vector y will be₈364 with eighth frame x vector x₈The addition yields a combined vector v8 for frame 8 and₈the generated value of the stage 1ds cell, the first stage 2ds cell, and the second stage 2ds cell will be equal to the value of the third RS overhead cell 320C generated in operation (B3), the value of the fourth RS overhead cell 350A generated in operation (B8), and the value of the fifth RS overhead cell 350B, respectively.

Further, in operation (B11), memory controller 1000 reads the 8 th frame x vector x₈And y vector y₈Are added together to generate an 8 th frame combination vector v₈。

By applying expression 7 above to the operation (B10), the 8 th frame y vector y₈May be determined according to the following expression 10:

y₈＝Δs₈·U_t2. (expression 10)

In accordance with at least some example embodiments of the inventive concept, in expression 10, the 8 th frame delta syndrome constraint Δ s₈Defined by the value of the third RS overhead element 320C generated in operation (B3), the value of the fourth RS overhead element 350A generated in operation (B8), and the value of the fifth RS overhead element 350B; matrix U_t2May be stored in memory controller 1000 and have m (t)₂-t₀)×m·t₂(i.e., m.DELTA.t × m.t)₂) Is calculated in advance.

Thus, memory controller 1000 may be implemented by following the expressionEquation 11 determines the 8 th frame combined vector v₈To perform an operation (B11)

v₈＝[0 y₈]+x₈(expression 11)

Wherein the 8 th frame y vector y is shown, for example, in items (k) and (l) of FIG. 3E₈Can use n-m.t₂And zero padding.

Example decoding operations according to at least some example embodiments of the inventive concepts are discussed below in section VI of the present disclosure.

VI, example decoding operation

According to at least some example embodiments of the inventive concepts, at some point after extended HPC encoding and projected BCH encoding have been performed on HPC codeword 200 (i.e., in the manner discussed above with reference to algorithms 1 and 2) and memory controller 1000 has stored HPC codeword 200 in memory device 2000, memory controller 1000 may read stored HPC codeword 200 from memory device 2000. For example, a memory controller may send one or more read commands to the memory device 2000. Memory device 2000 may then respond to one or more read commands by reading bits of HPC codeword 200 from the memory cells (e.g., a memory page) of memory cell array 2100 that store HPC codeword 200 and sending the read bits of HPC codeword 200 to memory controller 1000. Furthermore, in accordance with at least some example embodiments of the inventive concepts, memory controller 1000 may decode received HPC codewords 200 by performing an inner code decode operation followed by an outer code decode operation (e.g., using decoder 1200).

For example, the inner code decode operation may include sequentially decoding the rows and columns of HPC codeword 200 (e.g., by performing extended Hamming decoding on the rows and columns of HPC codeword 200) in order to reduce decoding complexity. Furthermore, improved performance may be achieved by performing Maximum Likelihood Decoding (MLD) of the component codes (e.g., soft decoding). For example, according to at least some example embodiments, decoder 1200 may be capable of performing soft input/soft output (SISO) decoding (e.g., as part of an inner code decoding operation) that may be used to obtain improved performance when decoding rows and columns of HPC codeword 200. For example, according to at least some example embodiments, the decoder 1200 may be or include a SISO decoder. With respect to CTCs (convolutional Turbo codes), using a SISO decoder (e.g., decoder 1200) for decoding the rows and columns of HPC codeword 200, memory controller 1000 may iterate the sequential decoding of the rows and columns of HPC codeword 200, thereby reducing the Bit Error Rate (BER) after each iteration.

For example, memory controller 1000 may use decoder 1200 to perform SISO decoding on rows and then perform SISO decoding on columns, or vice versa. In each such iteration, the soft data may be moved from row/column to column/row, and after multiple iterations, the algorithm may converge (with high probability) to a codeword that satisfies both the row and column conditions for the extended hamming code.

Memory controller 1000 may then perform outer code decoding using decoder 1200 after the inner code decoding described above is complete in order to correct errors, if any, still present in HPC codeword 200. The outer code decoding operation may be used to improve the error floor of the overall decoding operation and also verify that HPC codeword 200 is error free. Error floor may be caused when the decoder 1200 finds a codeword that satisfies both the row condition and the column condition for the extended hamming code but the remaining error pattern has too many errors to be corrected by the outer code. However, according to at least some example embodiments of the inventive concepts, by performing projection BCH encoding on the rows of HPC codewords 200 according to algorithm 2 discussed above, the effectiveness of the outer code decoding operations performed by memory controller 1000 may be improved, and thus the impact of the error floor associated with the outer code decoding operations may be reduced. An example outer code decoding operation in accordance with at least some example embodiments of the inventive concepts is illustrated below by algorithm 3. The operation of algorithm 3 is shown below using pseudo code. According to at least some example embodiments of the inventive concepts, each operation of algorithm 3 may be performed by memory controller 1000 (e.g., using microprocessor 111) or under the control of memory controller 1000.

Algorithm 3

For simplicity, algorithm 3 is described below with reference to codeword 300. Algorithm 3 will be described below with reference to the case where codeword 300 of fig. 3F has been encoded according to algorithm 1 and algorithm 2 (i.e., in the case where operation a2 of algorithm 1 is completed using algorithm 2).

Although algorithm 3 is explained below with reference to 8 frames of bits included in codeword 300 for simplicity, algorithm 3 may be performed for more than 8 frames of data. For example, memory controller 1000 may execute algorithm 3 for 192 frames of bits included in HPC codeword 200 shown in FIG. 2.

In operation (C1), after the memory controller 1000 completes the above-described inner code decoding operation on the rows and columns of the codeword 300, the memory controller 1000 performs a BCH decoding operation on the frames (i.e., the first frame 31 to the eighth frame 38) of the codeword 300.

In operation (C2), the memory controller 1000 determines which of the first through eighth frames 31 through 38 has been correctly decoded (referred to as "correct frames" in the present disclosure) and which of the first through eighth frames 31 through 38 includes errors (referred to as "error frames" in the present disclosure) according to a known BCH decoding method.

In operation (C3), for each correct frame of first frame 31 through eighth frame 38, memory controller 1000 generates a level 1 delta syndrome through a level N delta syndrome corresponding to the correct frame. According to at least some example embodiments of the inventive concepts, N represents a maximum level at which the incremental syndrome is generated. In the example of codeword 300 discussed above with reference to fig. 3A-3F, there are two levels of delta syndromes (e.g., level 1 delta syndrome 317A shown in item (c) in fig. 3B and first level 2 delta syndrome 347A and second level 2 delta syndrome 347B shown in item (i) in fig. 3D), so N is 2.

Operation (C3) also includes generating the embedded RS redundancy data as an incremental syndrome. In particular, as discussed above with reference to fig. 3A-3F and section V of the present disclosure, for the combined vector V₆And a combined vector v₇(which correspond to the sixth frame 36 and the seventh frame 37 of the codeword 300 respectively),for combined vector v₆The value of the generated stage 1ds unit will be equal to the value of the first RS overhead unit 320A, and for the combined vector v₇The value of the generated stage 1ds unit will be equal to the value of the second RS overhead unit 320B. Thus, in operation (C3), RS redundancy data is embedded in the stage 1ds cells generated for the sixth and seventh frames 36 and 37.

Further, as also discussed above with reference to fig. 3A-3F and section V of the present disclosure, shown in fig. 3D-3E, for the combined vector V₈(which corresponds to the eighth frame 38 of the codeword 300) for the combined vector v₈The generated value of the stage 1ds cell, the first stage 2ds cell, and the second stage 2ds cell will be equal to the value of the third RS overhead cell 320C generated in operation (B3) of algorithm 2, the value of the fourth RS overhead cell 350A generated in operation (B8) of algorithm 2, and the value of the fifth RS overhead cell 350B, respectively. Accordingly, in operation (C3), RS redundancy data is embedded in the stage 1ds cells and the stage 2ds cells generated for the eighth frame 38.

In operation (C4), the memory controller 1000 recovers the delta syndrome of the erroneous frame using RS redundancy embedded in the delta syndrome of the correct frame among the first frame 31 to the eighth frame 38. For example, if the first frame 31 is an error frame, the memory controller 1000 may not reliably generate the level 1 delta syndrome to the level N delta syndrome using data of the first frame 31 including an error. However, if the sixth frame 36 through the eighth frame 38 are correct frames, the memory controller 1000 may generate an RS delta-check sub-codeword using the RS overhead cells 320 (shown in item (d) of fig. 3B) and the stage 1ds cells of the other correct frames such that the RS delta-check sub-codeword includes the bits of the RS overhead cells 320 as redundancy bits and includes the bits of the stage 1ds cells of the other correct frames as information bits. Furthermore, as long as the total number of erroneous frames in first frame 31 through eighth frame 38 does not exceed stage 1 error row limit F1 (which is 3 for codeword 300 as discussed in section IV of this disclosure), memory controller 1000 may perform an RS decoding operation on the above-described RS delta-syndrome codeword, thereby recovering the stage 1ds cells corresponding to first frame 31.

In operation (C5), the memory controller 1000 performs BCH decoding again with the additional error correction capability Δ t provided by the at least one recovered delta syndrome corresponding to the erroneous frame, using the recovered delta syndrome, for the erroneous frame corresponding to the at least one recovered delta syndrome recovered in operation (C4). For example, since the BCH decoding operation performed in operation (C1) has an error correction capability of t0 ═ 6 (less than 7), the BCH decoding operation performed for the first frame 31 in operation (C1) will be unsuccessful if the first frame 31 includes 7 error bits. However, with the help of the level 1 delta syndrome of the first frame 31 recovered in operation (C4), the BCH decoding operation performed by the memory controller 1000 in operation (C5) will have an error correction capability of t1 ═ 7, which will be sufficient to correct the 7 erroneous bits in the first frame 31.

Then, in operation (C6), if the memory controller 1000 determines that the end condition has been satisfied, the memory device may end the outer code decoding operation. Example end conditions include, but are not limited to: the memory controller 1000 determines that all error frames have been corrected; and the memory device determines that the total number of erroneous frames exceeds the erroneous-row limit Fi for the current stage i of the outer-code decoding operation.

Further, in operation (C6), if the memory controller 1000 determines that the end condition is not satisfied, the memory controller 1000 returns to operation (C2) to determine the number of erroneous frames among the first to eighth frames. If the BCH decoding operation with improved error correction capability performed in operation (C5) is successful for correcting one or more erroneous frames, the total number of erroneous frames determined in the subsequent iteration of operation (C2) will be reduced compared to the previous iteration of operation (C2).

When operations (C2) through (C6) are performed iteratively, more erroneous frames may be corrected during each iteration. Furthermore, as more erroneous frames are corrected, more delta syndromes may be generated by memory controller 1000, and thus, the chances of being able to recover higher level delta syndromes increase. When the higher-level delta syndrome is recovered, the number of error bits that can be corrected by the BCH decoding operation performed in operation (C5) increases, so erroneous frames that have too many error bits to be corrected during the early iteration of operation (C5) can be corrected by later iterations of operation (C5). According to at least some example embodiments of the inventive concepts, the ith iteration of operations (C2) through (C6) corresponds to an ith outer code decoding operation.

An example implementation of the memory system 900 will now be discussed in section VII of the present disclosure below.

VII, examples of implementation

Fig. 4 is a block diagram illustrating a computer system 3000 including a memory system according to at least one example embodiment of the inventive concepts. The computer system 3000, such as a mobile device, a desktop computer, and a server, may employ the memory system 3400 according to at least one example embodiment of the inventive concepts.

Computer system 3000 may include a Central Processing Unit (CPU)3100, a RAM 3200, a user interface 3300, and a memory system 3400 electrically connected to bus 3500. The host as described above may include the central processor 3100, RAM 3200, and user interface 3300 in the computer system 3000. The central processor 3100 may control the entire computer system 3000 and may perform computations corresponding to user commands entered via the user interface 3300. The RAM 3200 can be used as a data memory of the central processor 3100, and the central processor 3100 can write/read data to/from the memory system 3400.

As in the above-described example embodiments of the inventive concepts, the memory system 3400 may include the memory controller 3410 and the memory device 3420.

According to at least one example embodiment of the inventive concepts, the memory controller 3410 may be implemented by the memory controller 1000 discussed above with reference to fig. 1-2, and the memory device 3420 may be implemented by the memory device 2000 discussed above with reference to fig. 1-2.

Fig. 5 is a block diagram illustrating a memory card 4000 according to at least one example embodiment of the inventive concepts. The memory system 900 according to at least some example embodiments of the inventive concepts discussed above with reference to fig. 1-3F may be a memory card 4000. For example, the memory card 4000 may include an embedded multimedia card (eMMC) or a Secure Digital (SD) card. As shown in fig. 5, the memory card 4000 may include a memory controller 4100, a nonvolatile memory 4200, and a port region 4300. According to at least one example embodiment of the inventive concepts, the memory controller 4100 illustrated in fig. 5 may be implemented by the memory controller 1000 discussed above with reference to fig. 1 through 3F, and the non-volatile memory 4200 illustrated in fig. 5 may be implemented by the memory device 2000 discussed above with reference to fig. 1 through 3F.

Memory controller 4100 may communicate with an external host via port region 4300 according to a preset protocol. The protocol may be an eMMC protocol, an SD protocol, a SATA protocol, a SAS protocol, or a USB protocol.

Fig. 6 is a block diagram illustrating an example network system 5000 including a memory system according to at least one example embodiment of the inventive concepts. As shown in fig. 6, the network system 5000 may include a server system 5100 and a plurality of terminals 5300, 5400, and 5500 connected via a network 5200. The server system 5100 may include a server 5110 and an SSD 5120, wherein the server 5110 is configured to process requests received from a plurality of terminals 5300, 5400, and 5500 connected to the network 5200, and the SSD 5120 is configured to store data corresponding to the requests received from the terminals 5300, 5400, and 5500. Here, the SSD 5120 may be a memory system according to at least one example embodiment of the inventive concepts.

According to at least one example embodiment of the inventive concepts, SSD 5120 may be implemented by memory system 900 discussed above with reference to fig. 1-3F.

Meanwhile, the memory system according to the example embodiment of the inventive concepts may be mounted via any of various packages. For example, a memory system according to at least one example embodiment of the inventive concepts may be mounted via any of a variety of packages including: package on package (PoP), Ball Grid Array (BGA), Chip Scale Package (CSP), leaded plastic chip carrier (PLCC), plastic dual in-line package (PDIP), waffle-die package, die in wafer form, Chip On Board (COB), ceramic dual in-line package (CERDIP), plastic Metric Quad Flat Package (MQFP), Thin Quad Flat Package (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP), Thin Quad Flat Package (TQFP), System In Package (SIP), Multi Chip Package (MCP), wafer level fabricated package (WFP), wafer level processed stacked package (WSP), and the like.

Having thus described the example embodiments of the inventive concept, it will be apparent that the example embodiments of the inventive concept may be varied in many ways. Such variations are not to be regarded as a departure from the intended spirit and scope of the example embodiments of the inventive concept, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.