阅读说明：本技术 显示面板、显示面板的驱动方法及显示装置 (Display panel, driving method of display panel and display device ) 是由 卢慧玲 朱杰 张露 胡思明 于 2020-05-28 设计创作，主要内容包括：本发明公开了一种显示面板、显示面板的驱动方法及显示装置,显示面板包括多条第一数据线、多条第二数据线以及多条第三数据线,第一数据线连接一列包含第一颜色子像素及第二颜色子像素的子像素,第二数据线连接一列仅包含第三颜色子像素的子像素,第三数据线连接一列包含第一颜色子像素及第二颜色子像素的子像素；显示面板还包括多个多路复用器,第一数据线与多路复用器的第一输出端电连接,第二数据线与多路复用器的第二输出端电连接,多路复用器的输入端连接一数据连接线,第三数据线连接一数据连接线；在同一行周期内,第三数据线的数据信号输入时间与第一数据线的数据信号输入时间重叠。本发明能够改善隔列亮的问题。(The invention discloses a display panel, a driving method of the display panel and a display device, wherein the display panel comprises a plurality of first data lines, a plurality of second data lines and a plurality of third data lines, the first data lines are connected with a row of sub-pixels comprising first color sub-pixels and second color sub-pixels, the second data lines are connected with a row of sub-pixels only comprising third color sub-pixels, and the third data lines are connected with a row of sub-pixels comprising the first color sub-pixels and the second color sub-pixels; the display panel also comprises a plurality of multiplexers, a first data line is electrically connected with a first output end of each multiplexer, a second data line is electrically connected with a second output end of each multiplexer, an input end of each multiplexer is connected with a data connecting line, and a third data line is connected with a data connecting line; in the same line period, the data signal input time of the third data line overlaps the data signal input time of the first data line. The invention can improve the problem of alternate brightness.)

1. A display panel is characterized by comprising a plurality of first data lines, a plurality of second data lines and a plurality of third data lines, wherein the first data lines are connected with a row of sub-pixels comprising first color sub-pixels and second color sub-pixels, the second data lines are connected with a row of sub-pixels only comprising third color sub-pixels, and the third data lines are connected with a row of sub-pixels comprising the first color sub-pixels and the second color sub-pixels;

the display panel further comprises a plurality of multiplexers, the first data line is electrically connected with a first output end of each multiplexer, the second data line is electrically connected with a second output end of each multiplexer, an input end of each multiplexer is connected with a data connecting line, and the third data line is connected with a data connecting line; in the same line period, a data signal input time of the third data line overlaps a data signal input time of the first data line.

2. The display panel according to claim 1, wherein the multiplexer comprises a first transistor connected between the first output terminal and an input terminal of the multiplexer, and a second transistor connected between the second output terminal and an input terminal of the multiplexer, a control terminal of the second transistor is electrically connected to a first clock signal line, a control terminal of the first transistor is electrically connected to a second clock signal line, and a clock pulse on the second clock signal line at least partially overlaps with a scan pulse of a subpixel scanned in the row period.

3. The display panel according to claim 2, wherein the clock pulse on the second clock signal line completely overlaps with the scan pulse of the sub-pixel scanned in the line period in the same line period.

4. The display panel according to claim 2, wherein an impedance element having the same impedance as that of the first transistor is connected in series to the data connection line connected to the third data line.

5. The display panel according to claim 2, wherein a third transistor is connected in series to the data connection line connected to the third data line, and a control terminal of the third transistor is electrically connected to the second clock signal line.

6. The display panel according to claim 5, wherein the third transistor is formed in the same process as the first transistor.

7. The display panel according to claim 2, wherein the clock pulse on the first clock signal line is separated from the clock pulse on the second clock signal line by a predetermined time in the same line period.

8. A driving method of a display panel is characterized in that the display panel comprises a plurality of first data lines, a plurality of second data lines and a plurality of third data lines, wherein the first data lines are connected with a row of sub-pixels comprising a first color sub-pixel and a second color sub-pixel, the second data lines are connected with a row of sub-pixels only comprising a third color sub-pixel, and the third data lines are connected with a row of sub-pixels comprising the first color sub-pixel and the second color sub-pixel; the display panel further comprises a plurality of multiplexers, the first data line is electrically connected with a first output end of each multiplexer, the second data line is electrically connected with a second output end of each multiplexer, an input end of each multiplexer is connected with a data connecting line, and the third data line is connected with a data connecting line;

the method comprises the following steps:

in the same line period, a data connection line connected with the multiplexer inputs data signals to the first data line and the second data line in a preset sequence through the multiplexer; the data connection line connected with the third data line inputs a data signal to the third data line, and the data signal input time of the third data line overlaps with the data signal input time of the first data line.

9. The method of claim 8, wherein the multiplexer comprises a first transistor connected between the first output terminal and an input terminal of the multiplexer, and a second transistor connected between the second output terminal and an input terminal of the multiplexer, a control terminal of the second transistor being electrically connected to a first clock signal line, a control terminal of the first transistor being electrically connected to a second clock signal line; the third data line inputs a data signal through a third transistor, and a control end of the third transistor is electrically connected with the second clock signal line;

in the same line period, a data connection line connected with the multiplexer inputs data signals to the first data line and the second data line in a preset sequence through the multiplexer; the data connection line connected to the third data line inputs a data signal to the third data line, and the data signal input time of the third data line overlaps the data signal input time of the first data line includes:

in a first stage, the first clock signal line controls the second transistor to be conducted, and a data signal is input into the second data line;

in a second stage, the second clock signal line controls the first transistor and the third transistor to be turned on simultaneously, and the first data line and the third data line input data signals simultaneously.

10. A display device characterized by comprising the display panel according to any one of claims 1 to 7.

Technical Field

Embodiments of the present invention relate to display technologies, and in particular, to a display panel, a driving method of the display panel, and a display device.

Background

With the development of display technology, the application of display panels is more and more extensive, and the corresponding requirements for the technical indexes of the display panels are higher and higher.

However, the conventional display panel has a problem of bright columns during display, and the display effect of the display panel is seriously affected.

Disclosure of Invention

The invention provides a display panel, a driving method of the display panel and a display device, which aim to solve the problem of alternate brightness.

In a first aspect, an embodiment of the present invention provides a display panel, where the display panel includes a plurality of first data lines, a plurality of second data lines, and a plurality of third data lines, where the first data lines are connected to a row of sub-pixels including a first color sub-pixel and a second color sub-pixel, the second data lines are connected to a row of sub-pixels including only a third color sub-pixel, and the third data lines are connected to a row of sub-pixels including the first color sub-pixel and the second color sub-pixel; the display panel further comprises a plurality of multiplexers, the first data line is electrically connected with a first output end of each multiplexer, the second data line is electrically connected with a second output end of each multiplexer, an input end of each multiplexer is connected with a data connecting line, and the third data line is connected with a data connecting line; in the same line period, a data signal input time of the third data line overlaps a data signal input time of the first data line.

Optionally, the multiplexer includes a first transistor connected between the first output terminal and the input terminal of the multiplexer, and a second transistor connected between the second output terminal and the input terminal of the multiplexer, a control terminal of the second transistor is electrically connected to a first clock signal line, a control terminal of the first transistor is electrically connected to a second clock signal line, and in a same row period, a clock pulse on the second clock signal line at least partially overlaps with a scan pulse of a subpixel scanned in the row period.

Optionally, in the same row period, the clock pulse on the second clock signal line completely overlaps with the scan pulse of the sub-pixel scanned in the row period.

Optionally, an impedance element is connected in series to the data connection line connected to the third data line, and an impedance of the impedance element is the same as an impedance of the first transistor.

Optionally, a third transistor is connected in series to the data connection line connected to the third data line, and a control terminal of the third transistor is electrically connected to the second clock signal line.

Optionally, the third transistor and the first transistor are formed in the same process.

Optionally, in the same line period, the clock pulse on the first clock signal line and the clock pulse on the second clock signal line are separated by a preset time.

In a second aspect, an embodiment of the present invention further provides a driving method of a display panel, where the display panel includes a plurality of first data lines, a plurality of second data lines, and a plurality of third data lines, the first data lines are connected to a row of sub-pixels including a first color sub-pixel and a second color sub-pixel, the second data lines are connected to a row of sub-pixels including only a third color sub-pixel, and the third data lines are connected to a row of sub-pixels including the first color sub-pixel and the second color sub-pixel; the display panel further comprises a plurality of multiplexers, the first data line is electrically connected with a first output end of each multiplexer, the second data line is electrically connected with a second output end of each multiplexer, an input end of each multiplexer is connected with a data connecting line, and the third data line is connected with a data connecting line;

the method comprises the following steps:

in the same line period, a data connection line connected with the multiplexer inputs data signals to the first data line and the second data line in a preset sequence through the multiplexer; the data connection line connected with the third data line inputs a data signal to the third data line, and the data signal input time of the third data line overlaps with the data signal input time of the first data line.

Optionally, the multiplexer includes a first transistor connected between the first output terminal and the input terminal of the multiplexer, and a second transistor connected between the second output terminal and the input terminal of the multiplexer, a control terminal of the second transistor is electrically connected to the first clock signal line, and a control terminal of the first transistor is electrically connected to the second clock signal line; the third data line inputs a data signal through a third transistor, and a control end of the third transistor is electrically connected with the second clock signal line;

in the same line period, a data connection line connected with the multiplexer inputs data signals to the first data line and the second data line in a preset sequence through the multiplexer; the data connection line connected to the third data line inputs a data signal to the third data line, and the data signal input time of the third data line overlaps the data signal input time of the first data line includes:

in a first stage, the first clock signal line controls the second transistor to be conducted, and a data signal is input into the second data line;

in a second stage, the second clock signal line controls the first transistor and the third transistor to be turned on simultaneously, and the first data line and the third data line input data signals simultaneously.

In a third aspect, an embodiment of the present invention further provides a display device, including the display panel according to the first aspect.

According to the technical scheme of the embodiment of the invention, the adopted display panel comprises a plurality of first data lines, a plurality of second data lines and a plurality of third data lines, wherein the first data lines are connected with a row of sub-pixels comprising first color sub-pixels and second color sub-pixels, the second data lines are connected with a row of sub-pixels only comprising third color sub-pixels, and the third data lines are connected with a row of sub-pixels comprising the first color sub-pixels and the second color sub-pixels; the display panel also comprises a plurality of multiplexers, a first data line is electrically connected with a first output end of each multiplexer, a second data line is electrically connected with a second output end of each multiplexer, an input end of each multiplexer is connected with a data connecting line, and a third data line is connected with a data connecting line; in the same line period, the data signal input time of the third data line overlaps the data signal input time of the first data line. The third sub-pixels positioned in the odd-numbered columns and the third sub-pixels positioned in the even-numbered columns are both connected with the second data lines, and the second data lines are both electrically connected with the second output ends of the corresponding multiplexers, so that the charging modes of the sub-pixels (third sub-pixels) connected with the second data lines are consistent, and the problem of alternate-column brightness of the columns where the third sub-pixels are positioned is solved. In the same row period, the data signal input time of the third data line is overlapped with the data signal input time of the first data line, namely the charging mode of the sub-pixels connected with the third data line is the same as the charging mode of the sub-pixels connected with the first data line, so that the charging mode of the first sub-pixels positioned in odd columns is the same as that of the first sub-pixels positioned in even columns, the problem of alternately bright columns cannot occur, and the problem of alternately bright columns cannot occur in the second sub-pixels similarly, so that the display effect is greatly improved.

Drawings

FIG. 1 is a schematic diagram of a conventional display panel structure;

FIG. 2 is a timing diagram illustrating a conventional driving method of a display panel;

fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention;

FIG. 4 is a timing diagram of a display panel according to an embodiment of the present invention;

FIG. 5 is a timing diagram of another display panel according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of another display panel according to an embodiment of the present invention;

fig. 8 is a flowchart of a driving method of a display panel according to an embodiment of the invention;

fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

As mentioned in the background art, the prior art display panel has the problem of brightness isolation, and the inventors have found through careful study that the reason for this technical problem is:

fig. 1 is a schematic structural diagram of a conventional display panel, and fig. 2 is a timing diagram of a conventional display panel, referring to fig. 1 and fig. 2, the conventional display panel includes a display area AA and a non-display area NAA, a plurality of criss-cross scan lines 101 'and data lines 102' are disposed in the display area AA, the scan lines 101 'and the data lines 102' define a plurality of pixel regions, and sub-pixels 103 'are disposed in the pixel regions, wherein the number of the sub-pixels 103' is three, namely, the red sub-pixel R, the green sub-pixel G and the blue sub-pixel B, each sub-pixel has disposed therein a pixel circuit, such as a pixel circuit with threshold compensation, typically a 7T1C pixel circuit, a plurality of multiplexers 104 ' are further provided in the non-display area NAA, the input terminals of the multiplexers 104 ' are electrically connected to the data connection lines 105 ', for outputting the data signal on the data connection line 105 'to the corresponding data line 102'; the multiplexer includes a first transistor T1 ' and a second transistor T2 ', a control terminal of the first transistor T1 ' is electrically connected to the first clock signal line Demux1 ', a first terminal is electrically connected to an input terminal of the multiplexer, and a second terminal is connected to a data line 102 '; a control end of the second transistor T2 ' is electrically connected to the second clock signal line Demux2 ', a first end is electrically connected to the input end of the multiplexer, and a second end is connected to a data line 102 '; the pixel arrangement of the display panel is as shown in fig. 1, and the specific working process is as follows:

in a row period, the first clock signal line Demux1 'provides a turn-on pulse to the first transistor T1' in a time period T1, the first transistor is turned on, but the Scan pulse Scan 'does not arrive on the Scan line 101', that is, the data signal is charged onto the data line first, and is charged into the corresponding sub-pixel after the Scan pulse arrives (time period T3), which is commonly referred to as a line charging mode; the second clock signal line Demux2 'supplies a turn-on pulse to the second transistor T2' for a time period T2, the second transistor is turned on, and in a case of a high frequency, the turn-on pulse of the second transistor T2 'at least partially overlaps with the Scan pulse Scan' to compress a row period, that is, in a time period T4, the turn-on pulse of the second transistor overlaps with the Scan pulse, and in a time period T4, since the Scan pulse has come, a data signal may be directly charged in the corresponding sub-pixel, that is, in a direct charging mode, and in a time period T2 except for the time period T4, the data signal is still in a line charging mode, that is, a column of sub-pixels connected to the first transistor is in a line charging mode, and a column of sub-pixels connected to the second transistor is in a mixed mode of line charging and direct charging is higher in charging efficiency than the line charging, resulting in that a column of sub-pixels connected to the first transistor is lower than a column of sub-pixels connected to the second transistor, taking the column where the green sub-pixels are located as an example, the green sub-pixels located in the odd-numbered columns are connected with the first transistor, and the charging efficiency is low in a line charging mode, while the green sub-pixels located in the even-numbered columns are connected with the second transistor, and the charging efficiency is high in a mixed mode of direct charging and line charging, so that the problem that the display panel is bright (vertical stripes) at every other column is caused, and the display effect is seriously influenced.

In order to solve the technical problems, the invention provides the following solutions:

fig. 3 is a schematic structural diagram of a display panel according to an embodiment of the present invention, referring to fig. 3, the display panel includes a plurality of first data lines 1021, a plurality of second data lines 1022 and a plurality of third data lines 1023, the first data lines 1021 connect a row of sub-pixels including a first color sub-pixel and a second color sub-pixel, the second data lines 1022 connect a row of sub-pixels including only a third color sub-pixel, and the third data lines 1023 connect a row of sub-pixels including a first color sub-pixel and a second color sub-pixel; the display panel further includes a plurality of multiplexers 104, the first data line 1021 is electrically connected to a first output terminal of the multiplexer 104, the second data line 1022 is electrically connected to a second output terminal of the multiplexer 104, an input terminal of the multiplexer 104 is connected to a data connection line 105 (the first data connection line 1051), and the third data line 1023 is connected to a data connection line (the second data connection line 1052); in the same line period, the data signal input time of the third data line 1023 overlaps the data signal input time of the first data line 1021.

Specifically, the display panel may be an OLED (organic light-Emitting Diode) display panel, and includes a display area AA and a non-display area NAA, wherein a plurality of scanning lines 101, data lines 102 and sub-pixels 103 are disposed in the display area AA, a plurality of multiplexers and data connection lines 105 are disposed in the non-display area NAA, and the data connection lines 105 are used for receiving data signals of a driving chip or a source driver. In this embodiment, the data line 102 includes a first data line 1021, a second data line 1022, and a third data line 1023, the scan line 101 and the data line 102 are interlaced to form a plurality of pixel regions, and sub-pixels are disposed in the pixel regions, the sub-pixels of this embodiment have three kinds, that is, a first color sub-pixel R, a second color sub-pixel B, and a third color sub-pixel G, which are configured to emit red blue light and green light, respectively, and in other embodiments, can also emit light of other colors, respectively; the sub-pixels are arranged in an array, wherein the sub-pixels in the 3n +1 th row are alternately arranged on the row by the first color sub-pixels and the second color sub-pixels, the sub-pixels in the 3n +2 th row only comprise the third color sub-pixels, the sub-pixels in the 3n +3 th row are alternately arranged on the row by the second color sub-pixels and the first color sub-pixels, and n is an integer greater than or equal to 0; and the sub-pixel of the 3n +1 column is connected with a first data line 1021, the sub-pixel of the 3n +2 column is connected with a second data line 1022, the sub-pixel of the 3n +3 column is connected with a third data line 1023, the third sub-pixel of the odd column and the third sub-pixel of the even column are both connected with the second data line 1022, and the second data line 1022 is electrically connected with the second output end of the corresponding multiplexer, so that the charging modes of the sub-pixels (third sub-pixels) connected with the second data line 1022 are ensured to be consistent, and the problem of alternate lighting of the column where the third sub-pixel is located can be avoided. In the same row period, the data signal input time of the third data line overlaps with the data signal input time of the first data line, that is, the charging mode of the sub-pixels connected with the third data line is the same as the charging mode of the sub-pixels connected with the first data line, so that the charging mode of the first sub-pixels positioned in odd columns is the same as that of the first sub-pixels positioned in even columns, and the problem of alternately bright columns cannot occur.

In the technical solution of this embodiment, the display panel includes a plurality of first data lines, a plurality of second data lines, and a plurality of third data lines, the first data lines are connected to a row of sub-pixels including a first color sub-pixel and a second color sub-pixel, the second data lines are connected to a row of sub-pixels including only a third color sub-pixel, and the third data lines are connected to a row of sub-pixels including a first color sub-pixel and a second color sub-pixel; the display panel also comprises a plurality of multiplexers, a first data line is electrically connected with a first output end of each multiplexer, a second data line is electrically connected with a second output end of each multiplexer, an input end of each multiplexer is connected with a data connecting line, and a third data line is connected with a data connecting line; in the same line period, the data signal input time of the third data line overlaps the data signal input time of the first data line. The third sub-pixels positioned in the odd-numbered columns and the third sub-pixels positioned in the even-numbered columns are both connected with the second data lines, and the second data lines are both electrically connected with the second output ends of the corresponding multiplexers, so that the charging modes of the sub-pixels (third sub-pixels) connected with the second data lines are consistent, and the problem of alternate-column brightness of the columns where the third sub-pixels are positioned is solved. In the same row period, the data signal input time of the third data line is overlapped with the data signal input time of the first data line, namely the charging mode of the sub-pixels connected with the third data line is the same as the charging mode of the sub-pixels connected with the first data line, so that the charging mode of the first sub-pixels positioned in odd columns is the same as that of the first sub-pixels positioned in even columns, the problem of alternately bright columns cannot occur, and the problem of alternately bright columns cannot occur in the second sub-pixels similarly, so that the display effect is greatly improved.

Alternatively, fig. 4 is a timing diagram of a display panel according to an embodiment of the present invention, and with reference to fig. 3 and 4, the multiplexer 104 includes a first transistor T1 connected between the first output terminal and the input terminal of the multiplexer 104, and a second transistor T2 connected between the second output terminal and the input terminal of the multiplexer 104, a control terminal of the second transistor T2 is electrically connected to the first clock signal line Demux1, a control terminal of the first transistor T1 is electrically connected to the second clock signal line Demux2, and during a same row period, a clock pulse on the second clock signal line Demux2 at least partially overlaps a scan pulse of a sub-pixel scanned during the row period.

Specifically, in the time period T1, the first clock signal line Demux1 controls the second transistor T2 to be turned on, so that the Data signal Data1 on the first Data connection line 1051 is written into the second Data line 1022 first; in a second time period T2, the second clock signal line Demux2 controls the first transistor T1 to be turned on, so that the Data signal Data1 on the first Data connection line 1051 is written into the first Data line 1021 first or directly into the corresponding sub-pixel (i.e. the sub-pixel connected to the first Data line and turned on in the current row period) in the time period T4, the Data signal Data1 on the first Data connection line 1051 is written into the corresponding sub-pixel directly, and at this time (time period T2), the Data signal Data2 on the third Data line 1023 is written into the third Data line 1023 first or directly into the corresponding sub-pixel; it should be noted that the Data signal Data1 on the first Data link 1051 in the t1 time period and the t2 time period may be the same or different; in a time period t3, the Scan pulse Scan controls the corresponding sub-pixel to write data, at this time, the data signals on the first data line 1021, the second data line 1022 and the third data line 1023 are written into the corresponding sub-pixel, that is, the data signals are written into the sub-pixels scanned in the line period and connected to the first data line 1021, the second data line 1022 and the third data line 1023, respectively, and in a time period t4, the clock pulse on the second clock signal line Demux2 overlaps with the Scan pulse Scan of the corresponding sub-pixel, so that the line period is shorter, and the method is more suitable for scenes such as high refresh frequency of the display panel.

Alternatively, fig. 5 is a timing diagram of another display panel according to an embodiment of the present invention, referring to fig. 5, in the same row period, a clock pulse on the second clock signal line Demux2 completely overlaps with a scan pulse of a sub-pixel scanned in the row period.

By the arrangement, on one hand, the line period can be compressed to a greater extent, and the refresh rate of the display panel is improved; on the other hand, the first data line 1021 is connected with the sub-pixels with two colors, namely, the first color sub-pixel and the second color sub-pixel, when the two color sub-pixels display a picture (for example, display a monochrome picture), the difference of data signals is large (for example, the difference of data voltages is large), the sub-pixels connected with the first data line 1021 are all in a direct charging mode, the charging efficiency is high, and uneven display caused by the residual data signals on the first data line 1021 in the previous line period can be effectively avoided.

Alternatively, fig. 6 is a schematic structural diagram of another display panel according to an embodiment of the present invention, and referring to fig. 6, an impedance element 201 is connected in series to a data connection line (a second data connection line 1052) connected to the third data line 1023, and an impedance of the impedance element 201 is the same as an impedance of the first transistor T1.

When the first data link line 1051 writes a data signal to the first data line 1021 through the multiplexer 104, because the first transistor T1 has a certain impedance, parameters such as the phase or the size of the data signal written on the first data line 1021 and the data signal input on the first data link line 1051 are not completely consistent, and if there is no impedance on the second data link line 1052, the phase and the size of the data signal on the third data line 1023 are consistent with those of the data signal on the second data link line 1052, so that the size or the phase of the data signal on the first data line 1021 and the data signal on the third data line 1023 are different, and there is a possibility that the first color sub-pixel and the second color sub-pixel have a problem of alternately bright. By setting the impedance of the impedance element 201 to be the same as the impedance of the first transistor T1, parameters such as the magnitude and phase of the data signal on the first data line 1021 and the third data line 1023 are the same, thereby further preventing the first color sub-pixel and the second color sub-pixel from being lighted in alternate rows. The impedance element 201 may be, for example, a resistor, and the impedance value of the first transistor T1 may be obtained by testing the transistors in the display panel test area.

Optionally, referring to fig. 7, a third transistor T3 is connected in series to a data connection line (a second data connection line 1052) connected to the third data line 1023, and a control terminal of the third transistor T3 is electrically connected to the second clock signal line Demux 2.

Specifically, the display panel needs to manufacture a large number of transistors in the manufacturing process, the manufacturing process is mature, and the process conditions are controllable, so that parameters such as impedance of the transistors can be set as required, the third transistor T3 is controlled by using the second clock signal line Demux2, and since the control end of the first transistor T1 is also electrically connected to the second clock signal line Demux2, the first transistor T1 and the second transistor T2 are turned on and off at the same time, that is, the data signal input time of the third data line 1023 is overlapped with the data signal input time of the first data line 1021, and further, the problem of alternate brightness of the first color sub-pixel and the second color sub-pixel is avoided.

Optionally, the third transistor is formed in the same process as the first transistor.

Specifically, the third transistor and the first transistor may be thin film transistors, and the formation process includes, for example, depositing an active layer, doping the active layer, forming a gate insulating layer, a gate layer, an interlayer insulating layer, a source drain electrode layer, and the like, where the manufacturing conditions (such as temperature and doping concentration) of the third transistor and the first transistor are completely the same, and the sizes of the first transistor and the second transistor are also the same, so as to ensure that the impedances of the first transistor and the third transistor are the same, and further avoid the problem that the first color sub-pixel and the second color sub-pixel appear alternately bright.

Optionally, with continued reference to fig. 4 and 5, the clock pulse on the first clock signal line Demux1 is separated from the clock pulse on the second clock signal line Demux2 by a preset time t5 during the same line period.

If the clock pulse on the first clock signal line Demux1 overlaps the clock pulse on the second clock signal line Demux2, the data signal written into the first data line and the data signal written into the second data line may be interfered with each other, and a display error may be caused, and the rising edge and the falling edge of the clock pulse both have a certain time, and by setting the interval between the clock pulse on the first clock signal line Demux1 and the clock pulse on the second clock signal line Demux2 to be the preset time t5, it is ensured that the clock pulse on the first clock signal line Demux1 and the clock pulse on the second clock signal line Demux2 may not be overlapped, thereby avoiding the phenomenon of data signal crosstalk. Illustratively, the time of t5 may be less than one tenth of the clock pulse on the first clock signal line Demux 1.

Referring to fig. 8, the display panel includes a plurality of first data lines, a plurality of second data lines and a plurality of third data lines, the first data lines are connected to a row of sub-pixels including a first color sub-pixel and a second color sub-pixel, the second data lines are connected to a row of sub-pixels including only a third color sub-pixel, and the third data lines are connected to a row of sub-pixels including a first color sub-pixel and a second color sub-pixel; the display panel further comprises a plurality of multiplexers, the first data line is electrically connected with the first output end of the multiplexers, the second data line is electrically connected with the second output end of the multiplexers, the input end of the multiplexers is connected with a data connecting line, and the third data line is connected with a data connecting line

The method comprises the following steps:

step S301, in the same line period, the data connecting line connected with the multiplexer inputs data signals to the first data line and the second data line through the multiplexer in a preset sequence; the data connection line connected with the third data line inputs a data signal to the third data line, and the data signal input time of the third data line overlaps with the data signal input time of the first data line.

Specifically, the third sub-pixels located in the odd-numbered columns and the third sub-pixels located in the even-numbered columns are both connected to the second data line 1022, and the second data line 1022 is electrically connected to the second output end of the corresponding multiplexer, so that the charging modes of the sub-pixels (third sub-pixels) connected to the second data line 1022 are consistent, and the problem of lighting every other column of the columns where the third sub-pixels are located does not occur. In the same row period, the data signal input time of the third data line is overlapped with the data signal input time of the first data line, namely the charging mode of the sub-pixels connected with the third data line is the same as the charging mode of the sub-pixels connected with the first data line, so that the charging mode of the first sub-pixels positioned in odd columns is the same as that of the first sub-pixels positioned in even columns, the problem of alternately bright columns cannot occur, and the problem of alternately bright columns cannot occur in the second sub-pixels similarly, so that the display effect is greatly improved.

Optionally, the multiplexer includes a first transistor connected between the first output terminal and the input terminal of the multiplexer, and a second transistor connected between the second output terminal and the input terminal of the multiplexer, a control terminal of the second transistor is electrically connected to the first clock signal line, and a control terminal of the first transistor is electrically connected to the second clock signal line; a third data line inputs a data signal through a third transistor, and a control end of the third transistor is electrically connected with the second clock signal line;

in the same line period, a data connecting line connected with the multiplexer inputs data signals to the first data line and the second data line in a preset sequence through the multiplexer; the data connection line connected with the third data line inputs a data signal to the third data line, and the data signal input time of the third data line overlaps with the data signal input time of the first data line, including:

in the first stage, the first clock signal line controls the conduction of the second transistor, and the second data line inputs a data signal;

in the second stage, the second clock signal line controls the first transistor and the third transistor to be turned on simultaneously, and the first data line and the third data line input data signals simultaneously.

Specifically, in the first time period, the second transistor is turned on, so that the second data line performs data writing, all the third color sub-pixels are connected to the corresponding second data line, and the second data line is connected to the second transistor, that is, the third color sub-pixels perform data writing through the second transistor, and the data writing modes are the same, so that the problem that every other row of the third color sub-pixels is bright is solved. Meanwhile, the first transistor and the third transistor are simultaneously conducted in the second time period, so that the problem that the first color sub-pixel and the second color sub-pixel are alternately bright is avoided, and the display effect is further improved. The preset sequence can be that the first stage is firstly carried out, and then the second stage is carried out; the predetermined sequence may also be the second stage first and then the first stage, which is not specifically limited in the embodiment of the present invention.

Fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention, and referring to fig. 9, the display device includes a display panel according to any embodiment of the present invention, and the display device may be, for example, a mobile phone, a tablet, a notebook, a display, an MP3, an MP4, a smart watch, or other wearable devices.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.