阅读说明：本技术 一种数据处理方法、装置、设备及存储介质 (Data processing method, device, equipment and storage medium ) 是由 潘攀 陆洋麟 高世洪 段仕勇 齐俊 于 2020-05-25 设计创作，主要内容包括：本发明公开了一种数据处理方法、装置、设备及存储介质。该方法包括：第一器件获取目标数据；所述第一器件将所述目标数据写入存储器的目标区域；所述第一器件在写操作结束后,向寄存器或者中断发送写操作结束指令,以使所述寄存器或者中断向第二器件发送写操作结束信息,所述第二器件根据所述写操作结束信息读取所述目标区域内的所述目标数据,通过本发明的技术方案,能够实现第一器件和第二器件共同使用一个DDR区域,第一器件处理完成的数据放在DDR的特定区域,第二器件可以直接取走,不需要第二器件拷贝数据,只需要第二器件简单的控制读写状态,进而减少第二器件的占用率,提升操作效率。(The invention discloses a data processing method, a data processing device, data processing equipment and a storage medium. The method comprises the following steps: the first device acquires target data; the first device writes the target data to a target area of a memory; after the write operation is finished, the first device sends a write operation finishing instruction to the register or the interrupt so as to enable the register or the interrupt to send write operation finishing information to the second device, and the second device reads the target data in the target area according to the write operation finishing information.)

1. A data processing method, comprising:

the first device acquires target data;

the first device writes the target data to a target area of a memory;

and after the write operation is finished, the first device sends a write operation finishing instruction to a register or an interrupt so as to enable the register or the interrupt to send write operation finishing information to a second device, and the second device reads the target data in the target area according to the write operation finishing information.

2. The method of claim 1, wherein the first device writing the target data to a target area of memory comprises:

the first device sends a write instruction to a controller so that the controller controls the first device to write the target data into a target area of a memory through an interface.

3. The method of claim 1, wherein the target data comprises: collected data and/or processed data.

4. The method of claim 1, wherein the first device comprises: a microprocessor or Field Programmable Gate Array (FPGA), the second device comprising: a microprocessor or a field programmable gate array FPGA, the first device being different from the second device.

5. The method of claim 1, wherein prior to the first device writing the target data to the target region of memory, further comprising:

the microprocessor divides a target area in the memory, wherein the target area can be directly written in or read out by the first device or the second device.

6. The method of claim 5, wherein the target area size is 1 GB.

7. The method of claim 5, wherein the microprocessor maps the target area to a virtual address directly used by the microprocessor via a memory mapping.

8. A data processing apparatus, comprising: a first device, the first device comprising:

the acquisition module is used for acquiring target data;

a write module for writing the target data into a target area of a memory;

and the sending module is used for sending a write operation ending instruction to a register or an interrupt after the write operation is ended so that the register or the interrupt sends write operation ending information to a second device, and the second device reads the target data in the target area according to the write operation ending information.

9. An apparatus which, when run on a computer, causes the computer to perform the method of any one of claims 1-7.

10. A computer-readable storage medium comprising instructions which, when run on a computer, cause the computer to perform the method of any one of claims 1-7.

Technical Field

Embodiments of the present invention relate to computer technologies, and in particular, to a data processing method, an apparatus, a device, and a storage medium.

Background

In Data interaction between a conventional FPGA (Field-Programmable Gate Array) and an MPU (Micro Processor Unit), whenever the FPGA and the MPU interact with each other, the MPU needs to participate in copying Data from a register or a controller to a DDR (DDR SDRAM, a Memory) for processing Data by other software, or copying Data from the DDR to the register for taking away the FPGA. The traditional scheme needs the MPU to participate in each data transmission, when the data interaction is very frequent, the efficiency of the MPU frequently entering the copying operation is too low, or when the data volume is large, the occupation rate of the MPU is too high, or the data cannot be processed at all.

Disclosure of Invention

Embodiments of the present invention provide a data processing method, an apparatus, a device, and a storage medium, so as to implement that a first device and a second device share a DDR area, where data processed by the first device is placed in a specific DDR area, and the second device can be directly taken away without copying data by the second device, and only the second device needs to simply control a read-write state, thereby reducing an occupancy rate of the second device and improving operation efficiency.

In a first aspect, an embodiment of the present invention provides a data processing method, including:

the first device acquires target data;

the first device writes the target data to a target area of a memory;

and after the write operation is finished, the first device sends a write operation finishing instruction to a register or an interrupt so as to enable the register or the interrupt to send write operation finishing information to a second device, and the second device reads the target data in the target area according to the write operation finishing information.

In a second aspect, an embodiment of the present invention further provides a data processing apparatus, where the apparatus includes: a first device, the first device comprising:

the acquisition module is used for acquiring target data;

a write module for writing the target data into a target area of a memory;

and the sending module is used for sending a write operation ending instruction to a register or an interrupt after the write operation is ended so that the register or the interrupt sends write operation ending information to a second device, and the second device reads the target data in the target area according to the write operation ending information.

In a third aspect, embodiments of the present invention further provide an apparatus, which when run on a computer, causes the computer to execute the data processing method according to any one of the embodiments of the present invention.

In a fourth aspect, the embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the data processing method according to any one of the embodiments of the present invention.

The embodiment of the invention obtains target data through a first device; the first device writes the target data to a target area of a memory; after the write operation is finished, the first device sends a write operation finishing instruction to the register or the interrupt so as to enable the register or the interrupt to send write operation finishing information to the second device, the second device reads the target data in the target area according to the write operation finishing information, the first device and the second device can share one DDR area, the data processed by the first device is placed in a specific area of the DDR, the second device can be directly taken away, the second device is not required to copy the data, the read-write state is simply controlled by the second device, the occupancy rate of the second device is reduced, and the operation efficiency is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

FIG. 1 is a flow chart of a data processing method according to a first embodiment of the present invention;

FIG. 2A is a flowchart of a data processing method according to a second embodiment of the present invention;

FIG. 2B is a flow chart of another data processing method according to the second embodiment of the present invention;

FIG. 2C is a block diagram of the hardware connection according to the second embodiment of the present invention;

FIG. 3 is a schematic structural diagram of a data processing apparatus according to a second embodiment of the present invention;

fig. 4 is a schematic structural diagram of an apparatus in the fourth embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.