阅读说明：本技术 场效应晶体管和半导体器件
(Field effect transistor and semiconductor device
) 是由 秋山千帆子 于 2020-02-26 设计创作，主要内容包括：本发明涉及一种场效应晶体管和半导体器件。场效应晶体管包括：半导体区,其包括在第一方向上并排布置的第一非有源区、有源区和第二非有源区；在有源区上的栅电极、源电极和漏电极；在第一非有源区上的栅极焊盘；栅极保护部,其在半导体区上并与半导体区接触,该栅极保护部与栅极焊盘分开并且位于半导体区的第一非有源区侧上的边缘与栅极焊盘之间；在第二非有源区上的漏极焊盘；漏极保护部,其在半导体区上并且与半导体区相接触,该漏极保护部与漏极焊盘分开并且位于半导体区的第二非有源区侧上的边缘与漏极焊盘之间；以及金属膜,该金属膜被电连接到栅极保护部。(The present invention relates to a field effect transistor and a semiconductor device. The field effect transistor includes: a semiconductor region including a first non-active region, an active region, and a second non-active region arranged side by side in a first direction; a gate electrode, a source electrode and a drain electrode on the active region; a gate pad on the first inactive region; a gate protection portion on and in contact with the semiconductor region, the gate protection portion being separated from the gate pad and located between an edge on the first non-active region side of the semiconductor region and the gate pad; a drain pad on the second inactive region; a drain protection portion on and in contact with the semiconductor region, the drain protection portion being separated from the drain pad and located between an edge on the second non-active region side of the semiconductor region and the drain pad; and a metal film electrically connected to the gate protection part.)
1. A field effect transistor, comprising:
a substrate comprising a major surface and a back surface;
a semiconductor region on the main surface, the semiconductor region including a first non-active region, an active region, and a second non-active region arranged side by side in a first direction;
a gate electrode, a source electrode and a drain electrode on the active region;
a gate pad on the first non-active region and electrically connected to the gate electrode;
a gate protection portion on and in contact with the semiconductor region, the gate protection portion being separated from the gate pad and located between the gate pad and an edge on the first inactive region side of a pair of edges of the semiconductor region arranged side by side in the first direction;
a drain pad on the second non-active region and electrically connected to the drain electrode;
a drain protection portion on and in contact with the semiconductor region, the drain protection portion being separated from the drain pad and located between the drain pad and an edge of the pair of edges of the semiconductor region on the second inactive region side; and
a metal film on the back surface and electrically connected to the gate protection part,
wherein the drain protective portion is in a non-conductive state with respect to the metal film, the gate electrode, the source electrode, and the drain electrode.
2. The field effect transistor according to claim 1, further comprising a wire penetrating the substrate and the semiconductor region,
wherein the source electrode is electrically connected to the metal film via the wire, and
wherein the gate protection part is electrically connected to the source electrode.
3. The field effect transistor according to claim 1 or 2, further comprising a source pad electrically connected to the source electrode, the source pad being arranged side by side with the gate pad on the first inactive region side, and
wherein the gate protection part extends from the source pad along the edge of the first inactive area side.
4. The field effect transistor according to any one of claims 1 to 3, further comprising an insulating film having openings on the drain pad and the gate pad,
wherein the gate protection portion and the drain protection portion are covered with the insulating film.
5. The field effect transistor according to any one of claims 1 to 4,
wherein the gate protection part is made of metal.
6. The field effect transistor according to any one of claims 1 to 5,
wherein the drain protection part is made of metal.
7. A semiconductor device, comprising:
the field effect transistor according to any one of claims 1 to 6;
a base member having a metal surface and used for mounting the field effect transistor; and
a conductive bonding material interposed between the metal film of the field effect transistor and a surface of the base member, the conductive bonding material including at least one of Ag, Au, and Cu.
8. The semiconductor device according to claim 7, further comprising a package in which the field effect transistor is accommodated non-hermetically.
9. A field effect transistor, comprising:
a substrate comprising a major surface and a back surface;
a semiconductor region on the main surface, the semiconductor region including a first edge, a first non-active region, an active region, a second non-active region, and a second edge arranged side by side in a first direction;
a gate electrode, a source electrode and a drain electrode on the active region;
a gate pad on the first non-active region and electrically connected to the gate electrode;
a gate protection portion on and in contact with the semiconductor region, the gate protection portion being separate from the gate pad and located between the first edge and the gate pad;
a drain pad on the second non-active region and electrically connected to the drain electrode;
a drain protection portion on and in contact with the semiconductor region, the drain protection portion being separate from the drain pad and located between the second edge and the drain pad; and
a metal film on the back surface and electrically connected to the gate protection part,
wherein the drain protection portion is electrically insulated from the metal film, the gate electrode, the source electrode, and the drain electrode.
10. The field effect transistor of claim 9, further comprising a wire embedded in the substrate and the semiconductor region,
wherein the source electrode is electrically connected to the metal film via the wire, and
wherein the gate protection part is electrically connected to the source electrode.
11. The field effect transistor according to claim 9 or 10, further comprising a source pad electrically connected to the source electrode, the source pad being arranged side by side with the gate pad on the first inactive region side, and
wherein the gate protection portion extends from the source pad along the first edge in a plan view.
12. The field effect transistor according to any one of claims 9 to 11, further comprising an insulating film having a first opening on the drain pad and a second opening on the gate pad,
wherein the gate protection portion and the drain protection portion are covered with the insulating film.
13. The field effect transistor according to any one of claims 9 to 12,
wherein the gate protection part is made of metal.
14. The field effect transistor according to any one of claims 9 to 13,
wherein the drain protection part is made of metal.
Technical Field
The present disclosure relates to a field effect transistor and a semiconductor device.
Background
Japanese unexamined patent publication No.2010-177550 describes a technique related to a semiconductor device. The semiconductor device disclosed in this document includes a semiconductor chip; two electrode pads disposed on the semiconductor chip; and a conductive guard ring disposed between the two electrode pads and a periphery on the semiconductor chip. The guard ring is divided into a plurality of cell regions insulated from each other by eliminating a portion of the guard ring.
Disclosure of Invention
According to one embodiment, there is provided a field effect transistor and a semiconductor device including: a substrate comprising a major surface and a back surface; a semiconductor region on the main surface, the semiconductor region including a first non-active region, an active region, and a second non-active region arranged side by side in a first direction; a gate electrode, a source electrode and a drain electrode on the active region; a gate pad on the first non-active region and electrically connected to the gate electrode; a gate protection portion on and in contact with the semiconductor region, the gate protection portion being separated from the gate pad and located between the gate pad and an edge on a first non-active region side of a pair of edges of the semiconductor region arranged side by side in the first direction; a drain pad on the second non-active region and electrically connected to the drain electrode; a drain protection portion on and in contact with the semiconductor region, the drain protection portion being separated from the drain pad and located between the drain pad and an edge on a second non-active region side of a pair of edges of the semiconductor region; and a metal film on the back surface and electrically connected to the gate protection part. The drain protective portion is in a non-conductive state with respect to the metal film, the gate electrode, the source electrode, and the drain electrode.
Drawings
Fig. 1 is a plan view showing the configuration of a field effect transistor (hereinafter, simply referred to as a transistor) according to a first embodiment.
FIG. 2 is a sectional view taken along line II-II in FIG. 1;
FIG. 3 is a sectional view taken along line III-III in FIG. 1;
FIG. 4 is a sectional view taken along line IV-IV of FIG. 1;
fig. 5A is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to line II-II in fig. 1;
fig. 5B is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to line III-III in fig. 1;
fig. 5C is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to line IV-IV in fig. 1;
fig. 6A is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to line II-II in fig. 1;
fig. 6B is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to line III-III in fig. 1;
fig. 6C is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to line IV-IV in fig. 1;
fig. 7A is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to line II-II in fig. 1;
fig. 7B is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to line III-III in fig. 1;
fig. 7C is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to the line IV-IV in fig. 1;
fig. 8A is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to line II-II in fig. 1;
fig. 8B is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to line III-III in fig. 1;
fig. 8C is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to line IV-IV in fig. 1;
fig. 9A is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to line II-II in fig. 1;
fig. 9B is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to line III-III in fig. 1;
fig. 9C is a cross-sectional view showing a typical step of the manufacturing method according to the first embodiment, and shows a cross-section corresponding to the line IV-IV in fig. 1;
fig. 10 is a partial cross-sectional view of a transistor according to a modification, and shows a sectional view corresponding to the line II-II shown in fig. 1; and
fig. 11 is a plan view showing the configuration of a semiconductor device according to the second embodiment.
Detailed Description
[ problem to be solved by the present disclosure ]
The field effect transistor includes a semiconductor region forming a main surface of a substrate; and a gate electrode, a source electrode, and a drain electrode disposed on the active region in the semiconductor region. Wires extend from these electrodes, and tips of the wires are connected to pads for wire bonding. For example, a gate pad connected to the gate electrode is provided on the non-active region on one side with respect to the active region. A drain pad connected to the drain electrode is provided on the non-active region on the other side with respect to the active region. A metal film is provided on the back surface of the substrate, and the back metal film is conductively bonded to the metal base member via a conductive bonding material. In many cases, the base member is defined as a reference potential (ground potential).
The following problems arise in the field effect transistor having the above configuration. In one use example, a negative voltage lower than the reference potential is applied to the gate electrode. Therefore, an electric field whose gate pad side is negative is generated between the gate pad and the base member. In a humid environment, due to this electric field, ion migration of the metal (e.g., Ag, Au, Cu) included in the conductive bonding material easily occurs between the base member and the back metal film. Ion migration is the phenomenon in which ionized metal moves on the surface of a substance in an electric field. The metal ions are attracted by the electric field to move, return to the metal from an ionized state for some reason, and accumulate to form dendrites. Defects may occur in the operation of the semiconductor device if a dendrite of metal grows from the conductive bonding material and the gate pad and the backside metal film are shorted. Accordingly, an object of the present disclosure is to reduce a short circuit between a backside metal film and a gate pad due to ion migration of a metal contained in a conductive bonding material, and to provide a field effect transistor and a semiconductor device, which can improve moisture resistance of the field effect transistor.
[ effects of embodiments of the present disclosure ]
According to the present disclosure, it is possible to reduce a short circuit between the backside metal film and the gate pad due to ion migration of a metal contained in the conductive bonding material, and to provide a field effect transistor and a semiconductor device, which can improve moisture resistance of the field effect transistor.
[ description of embodiments of the present disclosure ]
First, details of embodiments of the present disclosure will be listed and described. One embodiment of the present disclosure is a field effect transistor including: a semiconductor region provided on a main surface of the substrate and including a first non-active region, an active region, and a second non-active region arranged side by side in a first direction; a gate electrode, a source electrode, and a drain electrode disposed on the active region; a gate pad disposed on the first non-active region and electrically connected to the gate electrode; a gate protection portion made of a metal, provided on and in contact with the semiconductor region so as to be separated from the gate pad between the gate pad and an edge on a first non-active region side of a pair of edges of the semiconductor region arranged side by side in the first direction; a drain pad disposed on the second non-active region and electrically connected to the drain electrode; and a drain protection portion made of a metal, provided on and in contact with the semiconductor region so as to be separated from the drain pad between the gate pad and an edge on a second non-active region side of a pair of edges of the semiconductor region. The gate protection portion is electrically connected to a metal film provided on the back surface of the substrate, and the drain protection portion is in a non-conductive state with respect to the metal film, the gate electrode, the source electrode, and the drain electrode.
The source electrode may be electrically connected to the metal film via a wire penetrating the substrate and the semiconductor region, and the gate protection portion may be electrically connected to the source electrode.
The field effect transistor further includes a source pad arranged on the first non-active region side by side with the gate pad and electrically connected to the source electrode, and the gate protection portion may extend from the source pad along an edge on the first non-active region side.
The field effect transistor may further include an insulating film having openings on the drain pad and the gate pad, and the gate protection portion and the drain protection portion may be covered with the insulating film.
Another embodiment of the present disclosure is a semiconductor device including: a field effect transistor; a base member having a metal surface and mounting a field effect transistor; and a conductive bonding material interposed between the metal film of the field effect transistor and the surface of the base member, and containing at least one of Ag, Au, and Cu.
The package housing the field effect transistor may have a non-sealing structure.
Specific examples of a field effect transistor and a semiconductor device according to the present disclosure will be described below with reference to the accompanying drawings. The present disclosure is not limited to these examples, but is indicated by the appended claims, and is intended to include any modifications within the scope and meaning equivalent to the appended claims. In the following description, in the description of the drawings, like elements will be denoted by like reference numerals, and redundant description will be omitted.
(first embodiment)
Fig. 1 is a plan view showing the configuration of a field effect transistor (hereinafter, simply referred to as a transistor) 1A according to a first embodiment. Fig. 2 is a sectional view taken along line II-II in fig. 1. Fig. 3 is a sectional view taken along line III-III in fig. 1. Fig. 4 is a sectional view taken along line IV-IV of fig. 1. As shown in fig. 1 to 4, the transistor 1A includes a substrate 3, insulating films 5 to 9, a gate electrode 21, a source electrode 22, a drain electrode 23, a gate pad 31, a source pad 32, a drain pad 33, and a field plate 35 (see fig. 4), a metal via 44 (see fig. 2), and a back metal film 45.
The substrate 3 includes a flat main surface 3a and a flat back surface 3b on the opposite side of the main surface 3 a. Substrate 3 includes growth substrate 30 and nitride semiconductor layer 4 provided on main surface 30a of growth substrate 30. The growth substrate 30 is, for example, a SiC substrate and includes a back surface 30 b. The back surface 30b of the growth substrate 30 coincides with the back surface 3b of the substrate 3. The growth substrate 30 is used for epitaxial growth of the nitride semiconductor layer 4.
The nitride semiconductor layer 4 is an example of a semiconductor region in the present embodiment, and is an epitaxial layer formed on the main surface 30a of the growth substrate 30. Nitride semiconductor layer 4 forms main surface 3a of substrate 3. When the transistor 1A is a High Electron Mobility Transistor (HEMT), the nitride semiconductor layer 4 includes, for example, an AlN buffer layer in contact with the main surface 30a, a GaN channel layer provided on the AlN buffer layer, an AlGaN (or InAlN) barrier layer provided on the GaN channel layer, and a GaN cap layer provided on the barrier layer. The AlN buffer layer is undoped and has a thickness in the range of, for example, 10nm to 20 nm. The GaN channel layer is undoped and has a thickness, for example, in the range of 0.4 μm to 1.2 μm. The barrier layer has a thickness in the range of, for example, 10nm to 30 nm. However, in the case of an InAlN barrier layer, its thickness is set to be less than 20 nm. The GaN cap layer is n-type and has a thickness of, for example, 5 nm.
As shown in fig. 1, the nitride semiconductor layer 4 includes an active region 4a and a non-active region 4b disposed around the active region 4 a. The active region 4a is a region operating as a transistor. The inactive region 4b is a region that is electrically deactivated by implanting ions (protons) such as argon (Ar) into the nitride semiconductor layer 4. The non-active region 4b is provided for electrical isolation between the transistors 1A adjacent to each other and for limiting the operation region of the transistors 1A. The inactive area 4b includes a first inactive area 4ba located on one side in a direction D1 (first direction) along the main surface 3a with respect to the active area 4 a; and a second inactive region 4bb located on the other side in the direction D1 with respect to the active region 4a in the direction D1. That is, the first inactive area 4ba, the active area 4a, and the second inactive area 4bb are arranged side by side in this order in the direction D1.
The insulating films 5 to 9 constitute an insulating laminated structure located on the nitride semiconductor layer 4. The insulating films 5 to 9 are provided on substantially the entire surfaces of the active region 4a and the non-active region 4 b. The insulating films 5 to 9 mainly include, for example, a silicon compound such as SiN, SiO2And SiON. In the present embodiment, the insulating films 5 to 9 are in contact with each other, but another layer may be provided in at least a part between the layers.
A plurality of source electrodes 22 are provided on the active region 4a of the nitride semiconductor layer 4, and make ohmic contact with the active region 4a of the nitride semiconductor layer 4 through openings 51 (see fig. 4) formed in the insulating film 5. As shown in fig. 1, the plurality of source electrodes 22 are arranged side by side along a direction D2 (second direction) intersecting (e.g., orthogonal to) the direction D1, and the planar shape of each source electrode 22 is a rectangular shape whose longitudinal direction is the direction D1. The source electrode 22 is formed by alloying a laminated structure including, for example, a Ti layer, an Al layer, and a Ti layer (or a Ta layer, an Al layer, and a Ta layer), and mainly contains Al.
A plurality of drain electrodes 23 are provided on the active region 4a of the nitride semiconductor layer 4, and form ohmic contacts with the active region 4a of the nitride semiconductor layer 4 through openings formed in the insulating film 5. As shown in fig. 1, the drain electrodes 23 are alternately arranged with the source electrodes 22 along the direction D2, and the planar shape of each drain electrode 23 is a rectangular shape whose longitudinal direction is the direction D1. The drain electrode 23 is also formed by alloying a laminated structure including, for example, a Ti layer, an Al layer, and a Ti layer (or a Ta layer, an Al layer, and a Ta layer), and mainly contains Al.
The gate electrode 21 includes a plurality of portions (finger portions) provided on the active region 4a of the nitride semiconductor layer 4 and a portion extending over the first inactive region 4 ba. The finger portion of each gate electrode 21 extends along direction D1 and is located between source electrode 22 and drain electrode 23. The finger portions of these gate electrodes 21 make schottky contact with the active region 4a of the nitride semiconductor layer 4. The contact width (gate length) between the gate electrode 21 and the nitride semiconductor layer 4 in the direction D2 is, for example, 0.5 μm. The gate electrode 21 has a laminated structure including a Ni layer and an Au layer on the Ni layer. In one example, the Ni layer is in contact with the nitride semiconductor layer 4, and the Au layer is in contact with the Ni layer. Alternatively, a Pd layer may be interposed between the Ni layer and the Au layer.
The field plate 35 is a metal film provided along the gate electrode 21. As shown in fig. 4, the insulating film 7 is interposed between the field plate 35 and the gate electrode 21. The field plate 35 has a stacked structure of, for example, a Ti layer (or a Ta layer) and an Au layer.
The gate pad 31 is a metal film provided on a part of the gate electrode 21 on the first inactive area 4ba, and is electrically connected to the gate electrode 21 by being in contact with the gate electrode 21 through openings formed in the insulating films 7 and 8. In the present embodiment, the plurality of gate pads 31 are arranged side by side in the direction D2. Each gate pad 31 is electrically connected to an external wire via a bonding wire. Therefore, the surface of each gate pad 31 is exposed from the opening of the insulating film 9. Each gate pad 31 has a laminated structure including, for example, a TiW layer and an Au layer on the TiW layer.
The source pad 32 is a metal film provided on a portion including the active region 4a and the first inactive region 4ba of the nitride semiconductor layer 4. The source pad 32 of the present embodiment includes portions arranged alternately with the gate pads 31 in the direction D2, and portions (finger portions) extending over the source electrodes 22 and covering the source electrodes 22. The source pad 32 is electrically connected to each source electrode 22 by contacting each source electrode 22 at the finger portion. Portions of the source pads 32 arranged side by side with the gate pads 31 are each exposed from the opening of the insulating film 9, and are each electrically connected to the back metal film 45 through metal vias 44 (see fig. 2) penetrating the substrate 3. The source pad 32 of the present embodiment includes a lower layer 32a (see fig. 2) in contact with the nitride semiconductor layer 4. The lower layer 32a is used to stop etching when forming a via hole 3c for forming the metal via hole 44 in the substrate 3. For example, the lower layer 32a has the same stacked structure as the gate electrode 21. The remaining portion of each source pad 32 other than the lower layer 32a has the same laminated structure as the gate pad 31, for example, a laminated structure including a TiW layer and an Au layer on the TiW layer. The stacked structure is in contact with nitride semiconductor layer 4 around lower layer 32 a.
The metal via 44 is a wire provided in a via hole 3c penetrating the substrate 3 (growth substrate 30 and nitride semiconductor layer 4) from the back surface 3b to the main surface 3 a. Metal via 44 reaches source pad 32 from back surface 3b of substrate 3 and is in contact with source pad 32. The metal via 44 is provided to electrically connect the back surface metal film 45 provided on the back surface 3b and the source electrode 22 having a low resistance through the source pad 32. When the transistor 1A is mounted on a base member defined at a ground potential (reference potential), the base member and the back metal film 45 are electrically connected to each other via a conductive bonding material such as a sintered type Ag paste. As a result, a ground potential is applied to the source electrode 22.
The drain pad 33 is a metal film provided on a portion including the second inactive region 4bb and the active region 4a of the nitride semiconductor layer 4. The drain pad 33 has the same laminated structure as the gate pad 31 and the source pad 32, for example, a laminated structure including a TiW layer and an Au layer on the TiW layer. The drain pad 33 includes portions (finger portions) extending on the drain electrodes 23 and covering the drain electrodes 23, respectively, and is electrically connected to each drain electrode 23 by being in contact with each drain electrode 23. Further, a portion provided on the second inactive region 4bb in the drain pad 33 has, for example, a rectangular shape whose longitudinal direction is the direction D2, and is electrically connected to an external wire via a bonding wire. Therefore, the surface of the portion of the drain pad 33 is exposed from the opening of the insulating film 9.
The transistor 1A of the present embodiment further includes a gate protection portion 11 and a drain protection portion 12 provided on the main surface 3a (on the nitride semiconductor layer 4). The gate protection portion 11 is made of a metal film, fills the openings formed in the insulating films 5 to 8, and is in contact with the first inactive area 4ba of the nitride semiconductor layer 4. Gate protecting part 11 is disposed between edge 3aa and gate pad 31, edge 3aa being located on first inactive area 4ba of a pair of edges 3aa and 3ab of main surface 3a (in other words, a pair of edges of nitride semiconductor layer 4) arranged side by side in direction D1. Gate protection portion 11 is spaced apart from both edge 3aa and gate pad 31. In the illustrated example, gate protecting portion 11 mainly extends along direction D2 (along edge 3aa of main surface 3 a). Further, the gate protection portion 11 includes a portion 11a extending along the side edge 3ac of the main surface and a portion 11b extending along the side edge 3ad of the main surface 3 a. The portions 11a and 11b are arranged side by side in the direction D2. These portions 11a and 11b extend from the vicinity of the edge 3aa and along the side edges 3ac and 3ad, respectively, in the direction D1. The gate protection part 11 has such a planar shape, and thus surrounds the pad group including the plurality of gate pads 31 from three sides.
The gate protection portion 11 is electrically connected with the source pad 32 at low resistance by the wires 13 provided respectively corresponding to the plurality of source pads 32 arranged side by side in the direction D2, and is electrically connected to the source electrode 22 via the source pad 32. In the present embodiment, gate protecting portion 11 extends from source pad 32 along edge 3aa of main surface 3 a. The gate protection portion 11 is electrically connected to the backside metal film 45 with low resistance via the wire 13, the source pad 32, and the metal via 44, and is defined at the same potential (e.g., reference potential) as the source electrode 22.
Referring to fig. 3, a contact width W1 between gate protection portion 11 and main surface 3a in a direction intersecting the extending direction of gate protection portion 11 is, for example, in the range of 1 μm to 10 μm, and is 6 μm in one embodiment. The distance L1 between the gate protection portion 11 and the gate electrode 21 on the main surface 3a is, for example, in the range of 5 μm to 20 μm, and is 15 μm in one embodiment. The distance L2 between the gate protection part 11 and the end face (edge 3aa) of the substrate 3 is, for example, in the range of 5 μm to 40 μm, and 25 μm in one embodiment. The height h1 of the gate protection portion 11 with respect to the main surface 3a (equal to the thickness of the gate protection portion 11 in the present embodiment) is, for example, in the range of 2 μm to 8 μm, and in one example, in the range of 4 μm.
The drain protection portion 12 is made of a metal film, fills the openings formed in the insulating films 5 to 8, and is in contact with the second inactive region 4bb of the nitride semiconductor layer 4. The drain protection portion 12 is provided between the edge 3ab of the main surface 3a on the second inactive region 4bb side and the drain pad 33 so as to be apart from both the edge 3ab and the drain pad 33. In the illustrated example, the drain protection portion 12 extends mainly along the direction D2 (along the edge 3ab of the main surface 3 a). The drain protection portion 12 includes a portion 12a extending along the side edge 3ac and a portion 12b extending along the side edge 3 ad. These portions 12a and 12b extend from the vicinity of the edge 3ab and along the side edges 3ac and 3ad, respectively, in the direction D1. The drain protection part 12 has such a planar shape, and thus surrounds the pad group including the plurality of drain protection parts 33 from three sides.
The drain protective portion 12 is in a non-conductive state with respect to the back metal film 45, the gate electrode 21, the source electrode 22, and the drain electrode 23. That is, the drain protective portion 12 is insulated from the back metal film 45, the gate electrode 21, the source electrode 22, and the drain electrode 23. The drain protection portion 12 of the present embodiment is connected to the electrodes 21 to 23 and the back metal film 45 via the second inactive region 4bb of the nitride semiconductor layer 4 and the insulating films (dielectrics) 5 to 9. During the operation of the transistor 1A, the potential of the drain protection portion 12 is a value divided by a potential difference between the drain pad 33 and the back surface metal film 45 according to a ratio of a resistance value between the drain pad 33 and the drain protection portion 12 to a resistance value between the back surface metal film 45 and the drain protection portion 12. Since the distance between the drain pad 33 and the drain protection portion 12 is shorter than the distance between the back metal film 45 and the drain protection portion 12, the potential of the drain protection portion 12 is close to the potential of the drain pad 33.
The contact width between the drain protection portion 12 and the main surface 3a in the direction intersecting the extending direction of the drain protection portion 12 is, for example, in the range of 1 μm to 10 μm, and is 6 μm in one embodiment. The distance between the drain protection portion 12 and the drain pad 33 on the main surface 3a is, for example, in the range of 5 μm to 20 μm, and 15 μm in one embodiment. The distance between the drain protection portion 12 and the end face (edge 3ab) of the substrate 3 is, for example, in the range of 5 μm to 40 μm, and 25 μm in one embodiment. The height of the drain protection portion 12 with respect to the main surface 3a (equal to the thickness of the drain protection portion 12 in the present embodiment) is, for example, in the range of 2 μm to 8 μm, and is 4 μm in one example.
The gate protection portion 11 and the drain protection portion 12 are formed simultaneously with the gate pad 31, the source pad 32, and the drain pad 33, and are made of the same material as these pads 31 to 33. That is, the gate protection portion 11 and the drain protection portion 12 of the present embodiment have the same laminated structure as the pads 31 to 33, for example, a laminated structure including a TiW layer and an Au layer on the TiW layer. The gate protection portion 11 and the drain protection portion 12 are covered with the insulating film 9.
A method for manufacturing the transistor 1A of the present embodiment having the above-described structure will be described. Fig. 5A to 9C are cross-sectional views showing typical steps of the manufacturing method according to the present embodiment. Fig. 5A, 6A, 7A, 8A and 9A show cross sections corresponding to line II-II in fig. 1. Fig. 5B, 6B, 7B, 8B and 9B show cross-sections corresponding to line III-III. Fig. 5C, 6C, 7C, 8C and 9C show cross-sections corresponding to line IV-IV.
First, nitride semiconductor layer 4 is formed on growth substrate 30, and substrate 3 is manufactured. Specifically, first, an AlN buffer layer is epitaxially grown on the growth substrate 30, a GaN channel layer is epitaxially grown thereon, an AlGaN (or InAlN) barrier layer is epitaxially grown thereon, and a GaN cap layer is epitaxially grown thereon. Then, by reacting Ar+Ions are implanted into the nitride semiconductor layer 4 except for the active region 4a to form a non-active region 4 b. Thus, the substrate 3 shown in fig. 1 to 4 is manufactured.
Next, as shown in fig. 5A to 5C, the insulating film 5 is deposited on the main surface 3a of the substrate 3. For example, when the insulating film 5 is made of a silicon compound such as SiN, the insulating film 5 is deposited by a plasma CVD method or a low pressure CVD (lpcvd) method. In the case of LPCVD, the film formation temperature is, for example, 850 ℃, and the film formation pressure is, for example, 10Pa or less. The raw material for forming the film is, for example, NH3And SiH2Cl2. The thickness of the insulating film 5 is, for example, in the range of 60nm to 100nm, and in one embodiment, 60 nm.
Subsequently, as shown in fig. 6C, an opening 51 corresponding to the source electrode 22 is formed in the insulating film 5. Meanwhile, other openings corresponding to the drain electrodes 23 are formed in the insulating film 5. Specifically, a resist mask having an opening pattern corresponding to these openings is formed on the insulating film 5, and the insulating film 5 is etched through the opening pattern to form these openings. Then, the source electrode 22 is formed in the opening 51 by a lift-off method, and the drain electrode 23 is formed in the other opening. That is, each metal layer (for example, Ti/Al/Ti or Ta/Al/Ta) for the source electrode 22 and the drain electrode 23 is successively deposited using a physical vapor deposition method or the like with the resist mask left. The thickness of each Ti layer (or Ta layer) is, for example, in the range of 10nm to 30nm (10 nm in one embodiment), and the thickness of the Al layer is, for example, in the range of 200nm to 400nm (300 nm in one embodiment). After removing the metal material deposited on the resist mask together with the resist mask, heat treatment (annealing) is performed at a temperature range of 500 ℃ to 600 ℃ (550 ℃ in one embodiment) to alloy the source electrode 22 and the drain electrode 23. The time for maintaining the temperature in the range of 500 ℃ to 600 ℃ is, for example, 1 minute.
Subsequently, as illustrated in fig. 6A to 6C, the insulating film 6 covering the insulating film 5, the source electrode 22, and the drain electrode 23 is deposited. For example, when the insulating film 6 is made of a silicon compound such as SiN, the insulating film 6 is deposited by a plasma CVD method. The film forming temperature is, for example, 300 ℃ and the film forming material is, for example, NH3And SiH4. The thickness of the insulating film 6 is, for example, 100 nm. By this step, the region where the gate electrode 21 is to be formed is covered with the double insulating films 5 and 6.
Subsequently, the lower layer 32a of the source pad 32 and the gate electrode 21 are formed. First, a resist for electron beams (EB resist) is deposited on the insulating film 6, and an opening pattern for the gate electrode 21 and the lower layer 32a of the source pad 32 is formed in the EB resist by EB writing. Next, the insulating film 6 and the insulating film 5 are successively etched through the opening pattern of the EB resist, as shown in fig. 7B and 7C, openings 52 and 53 penetrating the insulating films 5 and 6 are formed to expose the nitride semiconductor layer 4. Then, the gate electrode 21 is formed in the opening 52 and the lower layer 32a of the source pad 32, and at the same time, the lower layer 32a of the source pad 32 is formed in the opening 53 by using a lift-off method. That is, the respective metal layers (for example, Ni/Au or Ni/Pd/Au) for the gate electrode 21 and the lower layer 32a are successively deposited by using a physical vapor deposition method or the like while leaving the EB resist. The thickness of the Ni layer is, for example, in the range of 70nm to 150nm (100 nm in one embodiment), the thickness of the Pd layer is, for example, in the range of 50nm to 100nm (50 nm in one embodiment), and the thickness of the Au layer is, for example, in the range of 300nm to 700nm (500 nm in one embodiment). Thereafter, the metal material deposited on the EB resist is removed together with the EB resist.
Subsequently, as illustrated in fig. 8A to 8C, the insulating film 7 is deposited. First, the insulating film 7 is formed on the entire surface on the main surface 3a, and covers the insulating film 6, the gate electrode 21, and the lower layer 32 a. For example, when the insulating film 7 is made of a silicon compound such as SiN, the insulating film 7 is deposited by a plasma CVD method. The film forming temperature is, for example, 300 ℃ and the film forming material is, for example, NH3And SiH4. The thickness of the insulating film 7 is, for example, 100 nm.
Subsequently, as shown in fig. 8C, a field plate 35 is formed on the insulating film 7 along the gate electrode 21 on the active region 4 a. In this step, the field plate 35 is formed using, for example, a lift-off method. That is, a resist mask having an opening pattern corresponding to the planar shape of the field plate 35 is formed, and each metal layer (e.g., Ti (or Ni)/Au) for the field plate 35 is successively deposited using a physical vapor deposition method or the like. In one embodiment, the thickness of the Ti layer (or Ni layer) is 10nm and the thickness of the Au layer is 200 nm. Thereafter, the metal material deposited on the resist mask is removed together with the resist mask.
Subsequently, the insulating film 8 covering the insulating film 7 and the field plate 35 is deposited. Initially, the insulating film 8 is formed on the entire main surface 3 a. For example, when the insulating film 8 is made of a silicon compound such as SiN, the insulating film 8 is deposited by a plasma CVD method. The film forming temperature is, for example, 300 ℃ and the film forming material is, for example, NH3And SiH4. The thickness of the insulating film 8 is, for example, 200nm to 500 nm.
Subsequently, as shown in fig. 8A, the insulating films 7 and 8 on the lower layer 32a are removed by etching to form an opening, and the lower layer 32a is exposed. At this time, by successively etching the insulating films 5 to 8 around the lower layer 32a, the nitride semiconductor layer 4 around the lower layer 32a is exposed. At the same time, the insulating films 5 to 8 in the regions corresponding to the source pad 32 and the drain pad 33 are removed by etching to form openings. These openings include an area on the source electrode 22 and an area on the drain electrode 23, in which the source electrode 22 and the drain electrode 23 are exposed, as shown in fig. 8C. These openings include regions corresponding to the source pad 32 and the drain pad 33 on the non-active region 4b, and in the regions, the nitride semiconductor layer 4 is exposed. Meanwhile, as shown in fig. 8B, the insulating films 7 and 8 in the region corresponding to the gate pad 31 are removed by etching to form an opening 55, and the gate electrode 21 is exposed. Further, in this step, as shown in fig. 8A and 8B, the insulating films 5 to 8 in the region corresponding to the gate protection portion 11 are removed by etching to form the opening 54, and the nitride semiconductor layer 4 is exposed. Meanwhile, the insulating films 5 to 8 in the region corresponding to the drain protection portion 12 are removed by etching to form an opening, and the nitride semiconductor layer 4 is exposed. Specifically, a resist mask having an opening pattern corresponding to the above-described openings is formed on the insulating film 8, and the insulating films 5 to 8 are etched through the opening pattern to form the openings.
As shown in fig. 9A to 9C, after the resist mask is removed, the gate protection portion 11, the drain protection portion 12, the wire 13, the gate pad 31, the source pad 32, and the drain pad 33 are simultaneously formed. Specifically, a seed metal layer (Ti/TiW/Ti/Au) is formed on the entire main surface 3a by a sputtering method. The thickness of each Ti layer is, for example, 10nm, the thickness of the TiW layer is, for example, 100nm, and the thickness of the Au layer is, for example, 100 nm. Then, a resist mask having openings in regions where the gate protection portion 11, the drain protection portion 12, the wires 13, the gate pad 31, the source pad 32, and the drain pad 33 are to be formed is formed on the seed metal layer. Thereafter, a plating process is performed to form an Au layer in each opening of the resist mask. In this case, the thickness of the Au layer is, for example, 3 μm. After the electroplating process, the resist mask is removed, and the exposed seed metal layer is removed.
Subsequently, an insulating film (passivation film) 9 is deposited on the entire surface on the main surface 3 a. For example, when the insulating film 9 is made of a silicon compound such as SiN,the insulating film 9 is deposited by a plasma CVD method. The film forming temperature is, for example, 300 ℃ and the film forming material is, for example, NH3And SiH4. The thickness of the insulating film 9 is, for example, 200nm to 500 nm. Then, openings of the insulating film 9 are formed on the gate pad 31, the source pad 32, and the drain pad 33 in the non-active region 4b to expose the gate pad 31, the source pad 32, and the drain pad 33, respectively. In this way, the process on the main surface 3a side is completed.
Subsequently, a protective resist is formed on the main surface 3a by spin coating, and the resist covers all components on the main surface 3 a. Then, the support substrate is attached to the resist. The support substrate is, for example, a glass plate. Then, the back surface 3b of the substrate 3 is polished to thin the substrate 3. At this time, for example, the growth substrate 30 having a thickness of 500 μm is thinned to 100 μm.
Subsequently, a seed metal film (e.g., TiW/Au) is formed on the back surface 3b and the side surfaces of the substrate 3 by, for example, a sputtering method. After a resist pattern is formed at a position overlapping the lower layer 32a of the source pad 32, a Ni mask is formed by performing a Ni plating process. Then, the resist pattern is removed, and the exposed seed metal film is removed by etching. Thereby, the region of the back surface 3b overlapping the lower layer 32a is exposed through the opening of the Ni mask. When the seed metal film is made of TiW/Au, the seed metal film can be easily removed by Reactive Ion Etching (RIE) using a fluorine-based gas.
Subsequently, a through hole 3c (see fig. 2) is formed in the substrate 3 by etching the growth substrate 30 and the nitride semiconductor layer 4 through the opening of the Ni mask. The through-hole 3c reaches the lower layer 32a from the back surface 3b of the substrate 3. Thereby, the lower layer 32a is exposed to the back surface 3b through the through hole 3 c. Then, a seed metal film (e.g., TiW/Au) is formed on the back surface 3b of the substrate 3 and on the inner surface of the through-hole 3c (including on the exposed lower layer 32 a) by, for example, a sputtering method. By performing electroplating on the seed metal film, a back metal film 45 is formed on the back surface 3b, and a metal via 44 reaching the lower layer 32a from the back surface 3b is formed in the via hole 3 c. Finally, the components on the main surface 3a side of the substrate 3 are separated from the supporting substrate. After cleaning the substrate product including the taken-out substrate 3, dicing is performed along the dicing lines to separate the respective chips from each other. Through the above steps, the transistor 1A of the present embodiment is completed.
The effect obtained by the transistor 1A of the present embodiment described above will be described together with the conventional problem. Typically, the back metal film 45 is conductively bonded to the metal base member via a conductive bonding material. In many cases, the base member is set to a reference potential (ground potential). In this case, when a negative voltage lower than the reference potential is applied to the gate electrode 21, an electric field that is negative with respect to the gate pad 31 side is generated between the gate pad 31 and the base member. In a humid environment, due to this electric field, ion migration of metals (e.g., Ag, Au, Cu) contained in the conductive bonding material may occur. Ion migration is a phenomenon in which ionized metal moves between electric fields over the surface of a substance. The metal ions are attracted by the electric field and move, for some reason, from an ionized state back to the metal and accumulate to form dendrites. Defects may occur in the operation of the transistor if a dendrite of metal grows from the conductive bonding material and the gate pad 31 and the backside metal film 45 are shorted.
In recent years, the use of GaN, SiC, Ga has been actively developed2O3Etc. as a main semiconductor material, and put it into practical use. Since the wide gap semiconductor device has a high withstand voltage, the performance of the semiconductor is enhanced by increasing the power supply voltage to increase the mobility, reducing the parasitic capacitance between the electrodes, and the like. Therefore, in the wide gap semiconductor device, the electric field mentioned above becomes strong, and ion migration easily occurs.
Therefore, transistor 1A of the present embodiment includes gate protection portion 11 between edge 3aa of main surface 3a and gate pad 31. The gate protection portion 11 is electrically connected to the back metal film 45, and is defined at the same potential (e.g., reference potential) as the back metal film 45. As a result, an electric field is generated mainly between the gate protection portion 11 and the gate pad 31, and the electric field generated between the gate protection portion 11 and the back metal film 45 is small. Therefore, since the force for moving metal ions between the gate protection portion 11 and the back metal film 45 is extremely weak, the growth of dendrites on the side surface of the substrate 3 can be suppressed, and short-circuiting between the back metal film 45 and the pad electrode 31 can be reduced.
The transistor 1A of the present embodiment includes the drain protection portion 12 between the edge 3ab of the main surface 3a and the drain pad 33. Therefore, entry of moisture into the active region 4a can be suppressed together with the gate protection portion 11, and the moisture resistance of the transistor 1A can be improved. Here, if the drain protection portion 12 is electrically connected to the gate protection portion 11 with low resistance, the following problem occurs. Normally, a positive bias voltage is applied to the drain electrode 23. In the case of a transistor using GaN as a main semiconductor material, a bias voltage to the drain electrode 23 is a high voltage exceeding, for example, 50V. When the drain protection portion 12 is electrically connected to the gate protection portion 11, the drain protection portion 12 is defined to be the same potential (e.g., reference potential) as the backside metal film 45. Since the drain protection portion 12 is disposed close to the drain pad 33, an electric field between the drain protection portion 12 and the drain pad 33 increases. The surface of the drain pad 33 is exposed from the opening of the insulating film 9, and moisture enters the boundary between the insulating film 9 and the drain pad 33. The electric field accelerates the entrance of moisture between the drain protection portion 12 and the drain pad 33. Therefore, the moisture resistance of the transistor 1A is lowered.
In order to solve this problem, in the present embodiment, the drain protective portion 12 is in a non-conductive state with respect to the back metal film 45, the gate electrode 21, the source electrode 22, and the drain electrode 23. In this case, the electric field between the drain protection portion 12 and the drain pad 33 can be reduced as compared with the case where the drain protection portion 12 is electrically connected to the gate protection portion 11 with low resistance. Therefore, a decrease in the moisture resistance of the transistor 1A can be suppressed.
As in the present embodiment, the source pad 32 may be arranged on the first inactive area 4ba side by side with the gate pad 31, and the gate protection part 11 may extend from the source pad 32 along the edge 3aa on the first inactive area 4ba side. For example, with such a configuration, the gate protection part 11 may be electrically connected to the source electrode 22, and the gate protection part 11 may be arranged between the gate pad 31 and the edge 3 aa.
As in the present embodiment, the gate protection portion 11 and the drain protection portion 12 may be covered by the insulating film 9 having openings on the drain pad 33 and the gate pad 31. In this case, the moisture resistance of the transistor 1A can be further improved.
(amendment)
Fig. 10 is a partial cross-sectional view of the transistor 1B according to the modification of the above-described embodiment, and shows a cross-sectional view corresponding to the line II-II shown in fig. 1. In the present modification, unlike the above-described embodiment, the insulating films 5 to 8 are not interposed between the wiring 13 connecting the gate protection portion 11 and the source pad 32 and the nitride semiconductor layer 4, and the wiring 13 and the nitride semiconductor layer 4 are in contact with each other. That is, the wires 13 of the present modification are formed directly on the exposed nitride semiconductor layer 4. In this case, the wires 13 each serve as a part of the gate protecting portion 11, and the effects of the above-described embodiments can be made more remarkable.
(second embodiment)
Fig. 11 is a plan view showing the configuration of a semiconductor device 100 according to the second embodiment. Fig. 11 shows a state where the cap of the semiconductor device 100 is removed. The semiconductor device 100 includes the transistor 1A of the first embodiment, a package 101, an input matching circuit 106, an output matching circuit 108, and an output capacitor 109. The transistor 1A, the input matching circuit 106, the output matching circuit 108, and the output capacitor 109 are accommodated in the package circuit 101. The package 101 has a non-hermetic structure in which hermetic sealing is not performed.
The package 101 includes a base member 103, a sidewall 104, two input leads 150, and two output leads 160. The base member 103 is a plate-like member including a flat main surface 103a made of metal. The base member 103 is made of, for example, copper, an alloy of copper and molybdenum, an alloy of copper and tungsten, or a laminated material of a copper plate, a molybdenum plate, a tungsten plate, an alloy plate of copper and molybdenum, and an alloy plate of copper and tungsten. The surface of the base member material of the base member 103 is plated with nickel-chromium (nichrome) gold, nickel-palladium-gold, silver, or nickel-palladium. Gold, silver and palladium are plating materials, and NiCr and Ni are seed materials. When the plating material and the seed material are contained, the adhesion can be enhanced as compared with the case where only the plating material is used. The thickness of the base member 103 is, for example, 0.5mm to 1.5 mm. The planar shape of the base member 103 is, for example, a rectangle.
The side wall 104 is a substantially rectangular frame-like member made of ceramic as a dielectric body. The side wall 104 includes a pair of portions 141 and 142 facing each other in the direction D1 along the main surface 103a of the base member 103, and a pair of portions 143 and 144 facing each other in the direction D2 intersecting the direction D1. Portions 141 and 142 extend parallel to each other along direction D2, and portions 143 and 144 extend parallel to each other along direction D1. A cross section of each of the portions 141 to 144 perpendicular to the extending direction is rectangular or square. The height of the sidewall 104 in the normal direction of the main surface 103a is, for example, 0.5mm to 1.0 mm. The side wall 104 is coupled with the main surface 103a of the base member 103 via an adhesive material such as silver brazing.
The input lead 150 and the output lead 160 are metal plate-like members, and in one example, are metal pieces of copper, copper alloy, or iron alloy. Input lead 150 has one end coupled to the upper surface of portion 141 of sidewall 104 in direction D1. The input lead 150 is insulated from the main surface 103a of the base member 103 by a portion 141 of the sidewall 104. Output lead 160 has one end coupled to the upper surface of portion 142 of sidewall 104 in direction D1. The output lead 160 is insulated from the main surface 103a of the base member 103 by the lining portion 142 of the sidewall 104.
The transistor 1A, the input matching circuit 106, the output matching circuit 108, and the output capacitor 109 are mounted in a region surrounded by the sidewall 104 on the main surface 3a of the base member 103. The input matching circuit 106, the transistor 1A, the output matching circuit 108, and the output capacitor 109 are provided in this order from the portion 141 of the sidewall 104. The input matching circuit 106 and the output matching circuit 108 are, for example, parallel plate type capacitors each having electrodes on the upper and lower surfaces of a ceramic substrate.
The input matching circuit 106, the transistor 1A, and the output matching circuit 108 are fixed on the base member 103 by a conductive bonding material such as a sintered conductive paste. The conductive bonding material includes at least one of Ag, Au, and Cu. In one embodiment, the conductive bonding material is obtained by sintering a sintered silver paste. A conductive bonding material for fixing the transistor 1A is interposed between the backside metal film 45 of the transistor 1A and the main surface 103a of the base member 103, and electrically and firmly connects them. An input matching circuit 106 is mounted on the input side of the transistor 1A, and an output matching circuit 108 is mounted on the output side of the transistor 1A, respectively. The input matching circuit 106 and the transistor 1A, the transistor 1A and the output matching circuit 108, the output matching circuit 108 and the output capacitor 109, and the output capacitor 109 and the output lead 160 are electrically connected to corresponding wires (not shown).
Input matching circuit 106 performs impedance matching between input lead 150 and transistor 1A. One end of the input matching circuit 106 is electrically connected to the input lead 150 via a bonding wire. The other end of the input matching circuit 106 is electrically connected to the gate pad 31 of the transistor 1A via a bonding wire (see fig. 1).
The output matching circuit 108 performs impedance matching between the transistor 1A and an external circuit. The output matching circuit 108 performs matching so that desired output, efficiency, and frequency characteristics are obtained. One end of the output matching circuit 108 is electrically connected to the drain pad 33 of the transistor 1A via a bonding wire (see fig. 1). The other end of the output matching circuit 108 is electrically connected to an output lead 160 via a bonding wire and an output capacitor 109.
The semiconductor device 100 of the present embodiment includes the transistor 1A of the first embodiment. Therefore, the growth of dendrites due to ion migration of the conductive bonding material interposed between the transistor 1A and the main surface 103a of the base member 103 can be suppressed, and the short circuit between the main surface 103a of the base member 103 and the gate pad 31 can be reduced. Moisture can be suppressed from entering the active region 4a, and the moisture resistance of the transistor 1A can be improved. When the package 101 housing the transistor 1A has a non-sealing structure as in the present embodiment, the usefulness of the transistor 1A becomes more remarkable.
The field effect transistor and the semiconductor device according to the present disclosure are not limited to the above-described embodiments, and various other modifications may be made thereto. For example, in the above-described embodiment, the metal via 44 is provided directly below the source pad 32 in the non-active region 4b, but may be provided directly below the source electrode 22 in the active region 4a (or directly below the opening formed in the source electrode 22). In the above-described embodiment, the gate protection portion 11 includes the portions 11a and 11b, and the drain protection portion 12 includes the portions 12a and 12b, but at least one of these portions may be omitted as needed. In the above-described embodiment, the gate protection portion 11, the drain protection portion 12, and the source pad 32 have the same configuration and are formed simultaneously. However, they may have different configurations and may be formed at different timings.
