阅读说明：本技术 光检测装置 (Optical detection device ) 是由 马场隆 枦达也 铃木祥仁 牧野健二 中村重幸 于 2019-01-24 设计创作，主要内容包括：光检测装置(1)具备由化合物半导体构成的雪崩光电二极管阵列基板(10)。电路基板(50)具有多个时间测量电路(40)及时钟驱动器(35)。各时间测量电路(40)具有延迟线部,根据延迟线(47)的动作结果,取得表示自对应的雪崩光电二极管(20)输入脉冲信号的时机的时间信息。延迟线部对应于脉冲信号输入到该时间测量电路(40)而开始延迟线(47)的动作,对应于来自时钟驱动器(35)的时钟信号输入到该时间测量电路(40)而停止延迟线(47)的动作,通过延迟线(47)的动作检测较时钟信号的周期短的时间间隔。(A photodetection device (1) is provided with an avalanche photodiode array substrate (10) composed of a compound semiconductor. The circuit board (50) has a plurality of time measurement circuits (40) and a clock driver (35). Each time measurement circuit (40) has a delay line section, and acquires time information indicating the timing of inputting a pulse signal from the corresponding avalanche photodiode (20) on the basis of the operation result of the delay line (47). The delay line section starts the operation of the delay line (47) in response to the input of a pulse signal to the time measurement circuit (40), stops the operation of the delay line (47) in response to the input of a clock signal from the clock driver (35) to the time measurement circuit (40), and detects a time interval shorter than the cycle of the clock signal by the operation of the delay line (47).)

1. A light detection device, wherein,

comprises the following steps:

an avalanche photodiode array substrate in which a plurality of avalanche photodiodes operating in a geiger mode and connected to a quenching circuit are two-dimensionally arranged, and which is composed of a compound semiconductor; and

a circuit substrate on which the avalanche photodiode array substrate is mounted,

the circuit board includes a plurality of time measurement circuits two-dimensionally arranged on the circuit board in correspondence with the plurality of avalanche photodiodes, and a clock driver for supplying a clock signal to the plurality of time measurement circuits,

each of the time measuring circuits has a delay line section including a delay line composed of a plurality of delay elements connected in series, and acquires time information indicating a timing at which a pulse signal is input from the corresponding avalanche photodiode to the time measuring circuit based on an operation result of the delay line,

the delay line section starts the operation of the delay line in response to the input of the pulse signal output from the corresponding avalanche photodiode to the time measurement circuit, and stops the operation of the delay line in response to the input of the clock signal from the clock driver to the time measurement circuit,

by the action of the delay line, a time interval shorter than the cycle of the clock signal is detected.

2. The light detection arrangement of claim 1,

each of the time measurement circuits further includes a counter for counting the clock signal, and acquires time information indicating a timing at which a pulse signal is input from the corresponding avalanche photodiode, based on an operation result of the counter and an operation result of the delay line.

3. The light detection arrangement of claim 2,

the counter starts to operate in response to the stop of the operation of the delay line and stops operating in synchronization with the clock signal from the clock driver.

4. The light detection arrangement of claim 3,

the circuit board includes a memory and a control circuit for controlling the time measuring circuit,

the control circuit resets the corresponding time measurement circuit in response to input of a reset signal to the control circuit, and stops input of the clock signal to the counter in response to input of a stop signal to the control circuit,

the reset signal and the stop signal are synchronized with the clock signal,

the delay line section stores the number of the delay elements which operate until the clock signal from the clock driver is input to the time measurement circuit after the reset signal is input to the corresponding time measurement circuit and the pulse signal output from the corresponding avalanche photodiode is input to the time measurement circuit,

the counter stores the number of the clock signals counted from the stop of the operation of the delay line to the input of the stop signal in the memory.

5. The light detection device according to any one of claims 1 to 4,

the plurality of time measurement circuits are two-dimensionally arranged in a region overlapping with a light detection region in which the plurality of avalanche photodiodes are two-dimensionally arranged, when viewed in a thickness direction of the avalanche photodiode array substrate, and the clock driver is arranged in a region not overlapping with the light detection region.

6. The light detection device according to any one of claims 1 to 5,

the quenching circuit is an active quenching circuit and is formed on the circuit substrate.

7. The light detection device according to any one of claims 1 to 6,

the avalanche photodiode array substrate is connected with the circuit substrate through a bump electrode.

8. The light detection device according to any one of claims 1 to 7,

the circuit substrate includes a silicon substrate.

Technical Field

The present invention relates to a photodetection device.

Background

A photodetector in which a plurality of avalanche photodiodes are two-dimensionally arranged is known (for example, non-patent document 1). The plurality of avalanche photodiodes operate in a geiger mode. The generation of the pulse signal in the plurality of avalanche photodiodes is detected using a plurality of time measurement circuits. The plurality of time measuring circuits operate in accordance with a clock signal supplied from a clock driver. In this photodetection device, a plurality of time measurement circuits are two-dimensionally arranged corresponding to a plurality of avalanche photodiodes.

Disclosure of Invention

Problems to be solved by the invention

In a configuration in which a plurality of time measurement circuits are two-dimensionally arranged, a clock signal is supplied to each time measurement circuit for each row or column. In this case, the wiring distance from the clock driver to each of the plurality of time measuring circuits arranged in the same row or the same column is not constant. The longer the wiring length from the clock driver to the time measurement circuit is, the more likely the waveform of the clock signal supplied to each time measurement circuit is broken. Specifically, as the length of wiring from the clock driver to the time measuring circuit is longer, the time from the lower limit value to the upper limit value and the time from the upper limit value to the lower limit value of the clock signal in the time measuring circuit tend to be longer. The time when the clock signal reaches the upper limit value from the lower limit value is the rising time of the clock signal. The time when the clock signal reaches the lower limit value from the upper limit value is the fall time of the clock signal.

In the photodetection device, a clock signal having a relatively high frequency (for example, 500MHz) is supplied from a clock driver to each time measurement circuit in order to improve the time resolution for detecting the generation of the pulse signal in each avalanche photodiode. If the frequency of the clock signal is high, that is, if the period of the clock signal is short, the interval between the rise and the fall of the clock signal is narrow. As a result, the time measurement circuit may not appropriately recognize the rise and fall of the clock signal input to the time measurement circuit due to the waveform collapse. If the rise and fall of the clock signal are not properly recognized in the time measurement circuit, the time measurement circuit cannot properly acquire time information indicating the timing at which the pulse signal from the avalanche photodiode is input to the time measurement circuit. If the time information indicating the timing at which the pulse signal is input to each time measurement circuit is not appropriately acquired, the occurrence of the pulse signal in the corresponding avalanche photodiode cannot be appropriately detected.

The larger the area of the detection surface of the photodetection device is, the larger the difference in wiring distance from the clock driver to each time measurement circuit is. Therefore, when the cycle of the clock signal is relatively short, the pixel circuit that does not appropriately perform time measurement may increase as the area of the detection surface of the light detection device increases.

In the photodetector, for example, an avalanche photodiode is formed by a compound semiconductor in order to improve sensitivity characteristics in a wavelength region of Near Infrared (NIR) or Short Wavelength Infrared (SWIR). In this case, a plurality of avalanche photodiodes operating in the geiger mode are arranged on a semiconductor substrate formed of a compound semiconductor. In a photodetection device in which an avalanche photodiode is formed using a compound semiconductor, the dark count rate may increase due to heat. The higher the frequency of the clock signal supplied from the clock driver, the greater the power consumption, and the more heat generated from the clock driver. Therefore, in the above-described photodetection device, there is a possibility that time measurement may be performed at an erroneous timing due to an increase in the dark count.

An object of one embodiment of the present invention is to provide a photodetection device capable of suppressing erroneous detection of measurement time and power consumption due to an increase in dark count, and capable of achieving both an improvement in accuracy of measurement time and an increase in size of a photodetection surface.

Means for solving the problems

A photodetection device according to one embodiment of the present invention includes an avalanche photodiode array substrate and a circuit substrate. The avalanche photodiode array substrate is composed of a compound semiconductor. An avalanche photodiode array substrate is mounted on the circuit substrate. In the avalanche photodiode array substrate, a plurality of avalanche photodiodes are two-dimensionally arranged. The plurality of avalanche photodiodes operate in a geiger mode. Each avalanche photodiode is connected to a quenching circuit. The circuit substrate has a plurality of time measurement circuits and a clock driver. The plurality of time measurement circuits are two-dimensionally arranged on the circuit substrate corresponding to the plurality of avalanche photodiodes. The clock driver supplies a clock signal to the plurality of time measurement circuits. Each time measurement circuit has a delay line section including a delay line composed of a plurality of delay elements connected in series. Each time measurement circuit acquires time information from the operation result of the delay line. The acquired time information is time information indicating a timing at which a pulse signal is input from the corresponding avalanche photodiode. The delay line section starts the operation of the delay line in response to the input of the pulse signal output from the corresponding avalanche photodiode to the time measurement circuit. The delay line section stops the operation of the delay line in response to a clock signal from the clock driver being input to the time measurement circuit. The delay line section detects a time shorter than the cycle of the clock signal by the operation of the delay line.

In the present embodiment, a time interval shorter than the cycle of the clock signal is detected by the operation of the delay line. Therefore, even if the period of the clock signal is long, the time resolution for detecting the generation of the pulse signal can be ensured. If the period of the clock signal is long, the rising and falling intervals of the clock signal supplied to the time measurement circuit are wide. Therefore, even if the wiring from the clock driver to the time measurement circuit is long and the rise time and fall time of the pulse signal supplied to the time measurement circuit are long, the rise and fall of the clock signal can be easily recognized in the time measurement circuit. As a result, the photodetection device can appropriately detect the generation of the pulse signal in each avalanche photodiode while securing the time resolution even if the area of the detection surface is large. If the clock driver is disposed on the circuit substrate, the wiring length from the clock driver to the time measuring circuit can be reduced.

If the frequency of the clock signal is reduced, power consumption can be suppressed and the amount of heat generated from the clock driver can also be reduced. In the photodetection device, the clock driver is provided on a circuit substrate different from the avalanche photodiode array substrate. Therefore, the distance between the clock driver and each avalanche photodiode is further separated than in the case where the clock driver is formed on the same substrate as the avalanche photodiode. Since the clock driver is provided on the circuit board, the density of the clock driver formed can be relaxed. Therefore, heat generated by the clock driver is not easily transferred to the avalanche photodiode. Therefore, erroneous detection of the measurement time can be suppressed.

In this embodiment, each time measuring circuit may further include a counter for counting the clock signal. Each time measuring circuit may acquire time information indicating a timing at which the pulse signal is input from the corresponding avalanche photodiode, based on an operation result of the counter and an operation result of the delay line. In this case, a longer time measurement is achieved than can be measured by the delay line alone.

In this embodiment, the counter may start operating in response to the stop of the operation of the delay line and stop operating in synchronization with the clock signal from the clock driver. In this case, if a pulse signal is not input from the corresponding avalanche photodiode, the delay line does not operate, and the counter does not operate. Therefore, power consumption can be reduced.

In this embodiment, the circuit board may include a memory and a control circuit for controlling the time measurement circuit for each time measurement circuit. The control circuit may also perform resetting of the corresponding time measurement circuit corresponding to the input of the reset signal to the control circuit, and input stop of the clock signal to the counter corresponding to the input of the stop signal to the control circuit. The reset signal and the stop signal may also be synchronized with the clock signal. The delay line section may store in the memory the number of delay elements which operate from the time when the pulse signal output from the corresponding avalanche photodiode after the time measurement circuit is reset is input to the time measurement circuit to the time when the clock signal from the clock driver is input to the time measurement circuit. The counter may store the number of clock signals counted from the stop of the delay line to the input of the stop signal in the memory.

In the present embodiment, the plurality of time measurement circuits may be two-dimensionally arranged in a region overlapping with a light detection region in which the plurality of avalanche photodiodes are two-dimensionally arranged, and the clock driver may be arranged in a region not overlapping with the light detection region, as viewed from the thickness direction of the avalanche photodiode array substrate. In this case, the influence of the heat generated by the clock driver on each avalanche photodiode can be further reduced.

In this embodiment, the quenching circuit may be an active quenching circuit and formed on the circuit board. In the case where the semiconductor substrate is made of a compound semiconductor, dark counts and residual pulses may occur more frequently than in the case where the semiconductor substrate is made of silicon. The active quenching circuit is formed on the circuit substrate, so that quenching time can be realized arbitrarily, and noise caused by dark count and residual pulse can be reduced easily.

In this embodiment mode, the avalanche photodiode array substrate and the circuit substrate may be connected to each other through the bump electrode. In this case, the influence of heat generated by the clock driver on each avalanche photodiode can be further reduced as compared with a case where the avalanche photodiode array substrate and the circuit substrate are connected by direct bonding or the like.

The circuit substrate may also include a silicon substrate. In this case, the manufacturing process of the configuration having the time measuring circuit and the clock driver can be simplified.

ADVANTAGEOUS EFFECTS OF INVENTION

According to one aspect of the present invention, there is provided a photodetection device capable of suppressing erroneous detection of measurement time and power consumption due to an increase in dark count, and capable of achieving both an improvement in accuracy of measurement time and an increase in size of a photodetection surface.

Drawings

Fig. 1 is a perspective view of a light detection device according to an embodiment.

Fig. 2 is a diagram showing a cross-sectional structure of the light detection device.

Fig. 3 is a plan view of the circuit substrate.

Fig. 4 is a plan view of a light detection region of the avalanche photodiode array substrate.

Fig. 5 is a diagram showing the structure of the circuit substrate.

Fig. 6 is a plan view of the mounting region of the circuit substrate.

Fig. 7 is a diagram showing the structure of the pixel circuit.

Fig. 8 is a timing chart showing the operation of the time measuring circuit.

Fig. 9 is a diagram showing a time measurement circuit supplied with a global clock signal.

Fig. 10 is a diagram showing a comparison of waveforms of global clock signals supplied to the respective time measurement circuits.

Fig. 11 is a diagram showing a comparison of waveforms of global clock signals supplied to the respective time measurement circuits.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the description, the same elements or elements having the same function are denoted by the same reference numerals, and redundant description thereof is omitted.

First, the overall configuration of the light detection device according to the present embodiment will be described with reference to fig. 1 to 7. Fig. 1 is a perspective view of a light detection device according to the present embodiment. Fig. 2 is a diagram showing a cross-sectional structure of the photodetection device according to the present embodiment. In fig. 2, hatching is omitted to improve visibility. Fig. 3 is a plan view of the circuit substrate. Fig. 4 is a top view showing a portion of the avalanche photodiode array substrate. Fig. 5 is a diagram showing the structure of the circuit substrate. Fig. 6 is a plan view showing a part of the circuit substrate. Fig. 7 is a diagram showing the structure of the pixel circuit.

As shown in fig. 1, the photodetector 1 includes an avalanche photodiode array substrate 10 and a circuit substrate 50. Hereinafter, the "avalanche photodiode" is referred to as "APD". The "avalanche photodiode array substrate" is referred to as an "APD array substrate". The circuit substrate 50 is disposed opposite to the APD array substrate 10. The APD array substrate 10 and the circuit substrate 50 are rectangular in plan view.

The APD array substrate 10 includes a main surface 10A, a main surface 10B, and a side surface 10C that face each other. The circuit board 50 includes a main surface 50A, a main surface 50B, and a side surface 50C that face each other. The main surface 10B of the APD array substrate 10 faces the main surface 50A of the circuit substrate 50. The surfaces parallel to the principal surfaces of the APD substrate 10 and the circuit substrate 50 are XY-axis planes, and the direction orthogonal to the principal surfaces is a Z-axis direction.

The side surface 50C of the circuit substrate 50 is located outside the side surface 10C of the APD array substrate 10 in the XY-axis plane direction. That is, the area of the circuit substrate 50 is larger than the area of the APD array substrate 10 in a plan view. The side surface 10C of the APD array substrate 10 and the side surface 50C of the circuit substrate 50 may be the same plane. In this case, the outer edge of the APD substrate 10 coincides with the outer edge of the circuit substrate 50 in a plan view.

A glass substrate may be disposed on the main surface 10A of the APD array substrate 10. The glass substrate is optically connected to the APD array substrate 10 by an optical adhesive. The glass substrate may also be formed directly on the APD array substrate 10. The side surface 10C of the APD array substrate 10 and the side surface of the glass substrate may be the same surface. In this case, the outer edge of the APD substrate 10 coincides with the outer edge of the glass substrate in a plan view. The side surface 10C of the APD array substrate 10, the side surface 50C of the circuit substrate 50, and the side surface of the glass substrate may be the same surface. In this case, the outer edge of the APD array substrate 10, the outer edge of the circuit substrate 50, and the outer edge of the glass substrate coincide with each other in a plan view.

The APD array substrate 10 includes an N-type semiconductor substrate 11 made of a compound semiconductor. The semiconductor substrate 11 has a substrate 12 made of InP forming a main surface 10A. On the substrate 12, a buffer layer 13 made of InP, an absorption layer 14 made of InGaAsP, an electric field relaxation layer 15 made of InGaAsP, and a multiplication layer 16 made of InP are formed in this order from the principal surface 10A side to the principal surface 10B side. The absorption layer 14 may also be formed of InGaAs. The semiconductor substrate 11 may be formed of GaAs, InGaAs, AlGaAs, inalgas, or the like.

As shown in fig. 2, the APD array substrate 10 is mounted to a circuit substrate 50. The APD array substrate 10 and the circuit substrate 50 are connected by bump electrodes 70. Specifically, as shown in fig. 3, the APD array substrate 10 is connected to the mounting region α disposed at the center of the circuit substrate 50 by the bump electrode 70 when viewed in the thickness direction of the APD array substrate 10. In the present embodiment, the mounting region α has a rectangular shape.

The APD array substrate 10 has a plurality of APDs 20 operating in geiger mode. As shown in fig. 4, the APDs 20 are two-dimensionally arranged in the light detection region β of the semiconductor substrate 11 when viewed from the thickness direction of the APD array substrate 10. The light detection region β has a rectangular shape, and overlaps the mounting region α of the circuit substrate 50 when viewed in the thickness direction of the APD array substrate 10. Each APD20 is surrounded by the insulating portion 21 when viewed from the thickness direction of the APD array substrate 10. Each APD20 has a P-type active region 22 formed by doping the multiplication layer 16 with impurities from the main surface 10B side. The doped impurity is, for example, Zn (zinc). The insulating portion 21 is formed by forming a polyimide film in a trench formed by wet etching or dry etching, for example. The active region 22 is formed in a circular shape when viewed in the thickness direction, and the insulating portion 21 is formed in an annular shape along the edge of the active region 22. The insulating portion 21 reaches the substrate 12 from the main surface 10B side of the semiconductor substrate 11 in the thickness direction of the APD array substrate 10.

The APD array substrate 10 has an insulating layer 23 and a plurality of electrode pads 24. The insulating layer 23 covers the semiconductor substrate 11 on the main surface 10B side. The electrode pad 24 is formed on the semiconductor substrate 11 on the main surface 10B side of each APD20, and is in contact with the active region 22. The electrode pad 24 is exposed from the insulating layer 23, passes through the bump electrode 70, and is connected to the circuit substrate 50.

The circuit substrate 50 has a main surface 50A and a main surface 50B, and is connected to the APD array substrate 10 on the main surface 50A side through the bump electrode 70. As shown in fig. 5, the circuit board 50 includes an interface circuit 31, a memory 32, a PLL (Phase Locked Loop) 33, a row (row) random access decoder 34, a clock driver 35, a plurality of pixel circuits 36, a column (column) random access decoder 37, and an I/O port 38.

The Interface circuit 31 corresponds to, for example, an SPI (Serial Peripheral Interface) bus. The interface circuit 31 receives digital signals such as SCLK (Serial Clock), CS (Chip Select), MOSI (Master Output/Slave Input), MISO (Master Input/Slave Output), and the like, which are Input from the outside, and stores setting information of registers included in the signals in the memory 32.

The PLL33 generates a global Clock signal based on a Master Clock (MCLK) input from the outside and data stored in the memory 32, and transmits the generated global Clock signal to the Clock driver 35. PLL33 includes a programmable frequency divider, and sets the frequency division number with reference to the data stored in memory 32. That is, the frequency division number of the PLL33 can be set to an arbitrary value in accordance with an input from the outside to the interface circuit 31. In this embodiment, the frequency of the master clock input from the outside is 10MHz, and the frequency of the global clock signal generated by the PLL33 is 200 MHz. The PLL33 outputs a control bias voltage of the time measurement circuit 40 that controls each pixel circuit 36 together with the global clock signal.

The clock driver 35 supplies a global clock signal to each pixel circuit 36. The plurality of pixel circuits 36 are electrically connected to the corresponding APDs 20 through the bump electrodes 70, respectively. The pulse signal from the corresponding APD20 is input to each pixel circuit 36, and each pixel circuit 36 processes the input pulse signal. The signal processed by each pixel circuit 36 is output to the I/O port 38 at a timing corresponding to the signals from the row random access decoder 34 and the column random access decoder 37.

The plurality of pixel circuits 36 are two-dimensionally arranged in the mounting region α overlapping the light detection region β corresponding to the respective APDs 20, as viewed from the thickness direction of the APD array substrate 10. As shown in fig. 3, the PLL33 and the clock driver 35 are disposed in the non-mounting region γ that does not overlap the light detection region β when viewed in the thickness direction of the APD array substrate 10.

As shown in fig. 2, the circuit board 50 includes a silicon substrate 51 and a wiring layer 52 laminated on the silicon substrate 51 in the mounting region α. The wiring layer 52 includes an electrode pad 54, a plurality of via holes 55, a plurality of Metal layers 56 disposed at different layers from each other, a plurality of gate electrodes 57 for forming MOSFETs (Metal-oxide-semiconductor field-effect transistors), a plurality of readout bus bars 58, and an insulating layer 59 in each pixel circuit 36. The electrode pad 54 is formed on the main surface 50A side for each pixel circuit 36, passes through the bump electrode 70, and is connected to the electrode pad 24 of the APD array substrate 10. That is, as shown in fig. 6, the electrode pads 54 are two-dimensionally arranged on the main surface 50A side.

The readout bus 58 is connected to the I/O port 38. The readout bus bar 58 is disposed closer to the main surface 50A than the main surface 50B. Therefore, this configuration can reduce parasitic capacitance generated in the readout bus 58. Therefore, even when the detection surface of the detector is large, the output signal from the pixel circuit can be read with less delay. The parasitic capacitance generated in the readout bus bar 58 is generated by the influence of the silicon substrate 51 and the circuit formed in the periphery thereof.

The plurality of via holes 55 are formed through the insulating layer 59 to electrically connect the electrode pad 54, the plurality of metal layers 56, and the plurality of gate electrodes 57. Each APD20 is connected to the gate 57 of the corresponding pixel circuit 36 through the electrode pad 24, the bump electrode 70, the electrode pad 54, the plurality of vias 55, and the plurality of metal layers 56. In the silicon substrate 51, a plurality of wells 60 are formed for each pixel circuit 36. In the wells 60, a source 61 and a drain 62 are formed corresponding to the respective gates 57.

As shown in fig. 7, each pixel circuit 36 includes a time measuring circuit 40, an active quenching circuit 41, a control circuit 42, and a readable memory 43. That is, the active quenching circuit 41, the control circuit 42, and the memory 43 are provided for each time measurement circuit 40. The plurality of time measurement circuits 40 are two-dimensionally arranged in the mounting region α of the circuit substrate 50 as viewed from the thickness direction of the APD array substrate 10. At least the time measuring circuit 40 is constituted by a MOSFET constituted by a gate electrode 57, a source electrode 61, and a drain electrode 62.

The active quenching circuit 41 is formed on the circuit substrate 50, and is connected to the corresponding APD20 through the electrode pad 24, the bump electrode 70 and the electrode pad 54. The pulse signal output from the corresponding APD20 passes through the active quench circuit 41 and is input to the control circuit 42. A bias for adjusting the quenching time is also applied to the active quenching circuit 41 from a wiring not shown.

The control circuit 42 receives a pulse signal from the corresponding APD20, a global clock signal supplied from the clock driver 35, a reset signal, and a stop signal. The reset signal and the stop signal are generated, for example, at ports outside the control circuit board 50. Control circuit 42 supplies time measurement circuit 40 with pulse signals from the corresponding APDs 20 and a global clock signal from clock driver 35. Control circuit 42 receives the reset signal and resets the corresponding time measurement circuit 40, receives the pulse signal from APD20 and instructs the time measurement circuit 40 to begin operation. The reset signal resets and sets the control circuit 42 and the time measuring circuit 40 to a standby state. The control circuit 42 stops the input of the clock signal to the coarse counter unit 45 in response to the input of a stop signal instructing the stop of the operation of the corresponding time measuring circuit 40 from a port outside the circuit board 50. The stop signal is synchronized with the incoming global clock signal.

The memory 43 stores the signal output from the time measuring circuit 40. The signals stored in the memory 43 correspond to the signals from the row random access decoder 34 and the column random access decoder 37, and are output to the I/O port 38 through the read bus 58.

Each time measuring circuit 40 has a fine section 44 for detecting a time interval shorter than the cycle of the global clock signal, and a coarse counter section 45 for counting the global clock signal. Fine features 44 are included in the delay line portion. The coarse counter unit 45 is included in the counter. Each time measuring circuit 40 acquires time information indicating the timing of inputting the pulse signal from the corresponding APD20 based on the operation result of the fine section 44 and the global clock signal generated by the clock driver 35. In the present embodiment, each time measurement circuit 40 measures the time from the input of the pulse signal to the input of the stop signal by the corresponding APD20, based on the operation result of the fine unit 44 and the operation result of the coarse counter unit 45 stored in the memory 43. This makes it possible to derive the timing of inputting the pulse signal from the corresponding APD20 with respect to the stop signal.

The fine section 44 includes a delay line 47 to which a plurality of delay elements 46 are connected in series and an encoder 48. In the present embodiment, the plurality of delay elements 46 are 16 buffers connected in series. The delay elements 46 have the same delay amount. The same delay amount includes an error to the extent that the time measurement circuit 40 does not affect the measured time. The amount of delay in each delay element 46 is a time interval that is shorter than the period of the global clock signal. Each delay element 46 is controlled by a control bias supplied from the PLL 33. The encoder 48 stores the delay amount delayed by the delay line 47 in the memory 43. That is, the operation result of the delay line 47 is stored in the memory 43. The coarse counter unit 45 counts the global clock signal and stores the count result in the memory 43. That is, the operation result of the coarse counter unit 45 is stored in the memory 43.

Referring to fig. 8, a specific operation of the time measurement circuit 40 will be described. The control circuit 42 is Reset in synchronization with the rise of the Global clock signal Global CLK in response to the input of the Reset signal Reset (timing t1 in fig. 8). The Reset signal Reset indicates light emission of a light source such as a laser, and is generated at a port of the control circuit substrate 50. The fine section 44 resets the control circuit 42 in response to the Reset signal Reset, and then starts the operation of the delay line 47 in response to the pulse signal SPADIN output from the APD20 connected to the fine section 44 being input to the time measuring circuit 40 (timing t2 in fig. 8). The fine section 44 stops the operation of the delay line 47 in response to the input of the Global clock signal Global CLK after the start of the operation of the delay line 47 to the time measuring circuit 40 (timing t3 in fig. 8).

The fine section 44 continues the operation of the delay line 47 from the time when the pulse signal output from the APD20 is input to the time when the next global clock signal rises. Specifically, in the fine section 44, the pulse signal output from the corresponding APD20 is input to the time measurement circuit 40, and the pulse propagates through the delay line 47. The rise of the global clock is input before the propagating pulse reaches the end of the delay line 47.

The encoder 48 generates a signal (signal shown by Fine Encode in fig. 8) which changes in accordance with the signal (signal shown by Delay Line in fig. 8) from the Delay Line 47, counts the number of stages in which the Delay elements 46 of the Delay Line 47 operate, and converts the counted number into a binary signal. Since the delay amount in each delay element 46 is a time interval shorter than the cycle of the global clock signal, the fine section 44 detects a time interval shorter than the cycle of the global clock signal by the operation of the delay line 47. Specifically, the encoder 48 counts the number of delay elements that operate from the time when the pulse signal output from the corresponding APD20 after the corresponding time measurement circuit 40 is reset is input to the time measurement circuit 40 to the time when the global clock signal is input to the time measurement circuit 40. In the example shown in fig. 8, the encoder 48 sets the number of delay elements 46 to be operated to 4.

The encoder 48 stores the number of activated delay elements 46 in the memory 43. The encoder 48 represents the number of delay elements 46 acting in binary. That is, the encoder 48 represents the time interval from the start to the stop of the action of the delay line 47 in binary, and the user can know the measurement time by multiplying the binary value by the delay amount of the delay element 46. The encoder 48 stores the binary data in the memory 43.

When the operation of the delay line 47 is stopped, the coarse counter unit 45 starts operating. When the coarse counter unit 45 starts operating, it counts the rise of the global clock signal until the stop signal is input to the control circuit 42. Specifically, the Coarse counter unit 45 generates a signal Coarse Count that changes in accordance with the rise of the global clock signal, and counts the global clock signal.

The coarse counter unit 45 stops operating under the control of the control circuit 42. In other words, when the control circuit 42 inputs the Stop signal Stop from the outside of the circuit board 50 (timing t4 in fig. 8), the input of the global clock signal to the coarse counter unit 45 is stopped. That is, in the present embodiment, the coarse counter unit 45 starts operating in response to the stop of the operation of the delay line 47, and stops operating in response to the input of a stop signal to the control circuit 42. Since the stop signal is synchronized with the global clock signal, the coarse counter unit 45 stops operating in synchronization with the global clock signal.

In the example shown in fig. 8, the coarse counter unit 45 sets the number of rises of the global clock signal to 5. The coarse counter unit 45 stores the counted number in the memory 43. In other words, the coarse counter unit 45 stores the number of global clock signals counted from the stop of the operation of the delay line 47 to the input of the stop signal in the memory 43. The time from when the delay line 47 of the fine section 44 stops until the stop signal is input can be calculated by multiplying the number counted by the coarse counter section 45 by the period of the global clock signal.

As described above, the time measurement circuit 40 stores, in the fine section 44, the delay amount from the input of the pulse signal from the APD20 to the rise of the input global clock signal, i.e., the time interval, in the memory 43. The time measurement circuit 40 stores in the coarse counter unit 45 the number of rises of the global clock signal from the stop of the operation of the delay line 47 of the fine unit 44 to the input of the stop signal in the memory 43. That is, the time measuring circuit 40 measures the time from the input of the pulse signal to the input of the stop signal by the corresponding APD20, based on the operation result of the delay line in the fine section 44 and the operation result of the coarse counter section 45. Therefore, the time measurement circuit 40 acquires time information indicating the timing of inputting the pulse signal from the APD20 with respect to the stop signal.

Next, the operation and effects of the photodetector 1 will be described with reference to fig. 9 to 11. Fig. 9 shows a time measurement circuit supplied with a global clock signal. Fig. 10 and 11 show a comparison of waveforms of the global clock signals supplied to the respective time measurement circuits.

The clock driver 35 supplies a global clock signal to each row of the plurality of time measurement circuits 40 two-dimensionally arranged in the mounting region α.FIG. 9 shows N time measurement circuits 40 arranged in the same row at a pitch of 100 μm₁～40_NIn electrical connection with clock driver 35. "N" is any integer. As shown in fig. 9, the time measuring circuits 40 arranged in the same row₁～40_NConnected in parallel with each other by 1 line connected to the clock driver 35. Measuring circuit 40 at N times₁～40_NIn the middle, the time measuring circuit 40₁The wiring distance from the clock driver 35 is minimum. Measuring circuit 40 at N times₁～40_NIn the middle, the time measuring circuit 40_NThe wiring distance from the clock driver 35 is the largest.

FIGS. 10 and 11 show that the global clock signal outputted from the clock driver 35 is supplied to the time measuring circuit 40 in a case where the period is 5ns (the frequency is 200MHz)₁And a time measurement circuit 40_NThe waveform of the global clock signal. In the graph shown in fig. 10, the horizontal axis represents the phase (ns) and the vertical axis represents the voltage (V).

FIG. 10 shows a time measurement circuit 40₁And time measuring circuit 40₃₂Comparison of (1). FIG. 11 shows a time measurement circuit 40₁And time measuring circuit 40₁₂₈Comparison of (1). In other words, fig. 10 shows a comparison of the waveform of the global clock signal supplied to the time measurement circuit 40 closest to the clock driver 35 among the time measurement circuits 40 arranged in the same row and the waveform of the global clock signal supplied from the clock driver 35 to the time measurement circuit No. 32. Fig. 11 shows a comparison of the waveform of the global clock signal supplied to the time measurement circuit 40 closest to the clock driver 35 among the time measurement circuits 40 arranged in the same row and the waveform of the global clock signal supplied from the clock driver 35 to the No. 128 time measurement circuit 40.

As shown in fig. 10 and 11, the time measuring circuit 40₁And a time measurement circuit 40₁₂₈The difference time measuring circuit 40 of the waveform of the supplied global clock signal₁And a time measurement circuit 40₃₂The difference in the waveform of the global clock signal supplied in (b) is larger. Thus, the further apart the distance from the clock driver 35 to the time measurement circuit 40, the more significantShowing a collapse of the waveform of the global clock signal supplied to the time measurement circuit 40.

In the case where the frequency of the global clock signal is 200MHz, the period from rising to falling is 2.5 ns. Time measuring circuit 40₁₂₈In the above description, the time from the lower limit to the upper limit, i.e., the rise time, and the time from the upper limit to the lower limit, i.e., the fall time, are about 2.5 ns. Therefore, if the frequency of the global clock signal is set to be higher than 200Hz, the cycle is shorter than the rise time and the fall time, and therefore the rise of the global clock signal may not be recognized properly by the time measurement circuit 40 or the control circuit 42. Namely, the time measuring circuit 40₁₂₈In this case, due to the influence of waveform collapse, there is a possibility that the timing at which the delay line 47 stops operating and the coarse counter unit 45 starts operating after the pulse signal is input from the APD20 to the time measurement circuit 40 cannot be appropriately detected. In other words, when the time measurement circuits 40 are arranged at a pitch of 100 μm, the arrival time of the pulse signal at the APD20 may not be appropriately recorded in the pixels having the time measurement circuits 40 from the clock driver 35 to No. 128.

In the photodetection device 1, each time measurement circuit 40 acquires time information indicating the timing at which the pulse signal is input from the corresponding APD20 to the time measurement circuit 40, based on the operation result of the delay line 47. The fine section 44 detects a time interval shorter than the period of the global clock signal by the action of the delay line 47.

In this way, since a time interval shorter than the cycle of the global clock signal is detected by the operation of the delay line 47, even if the cycle of the global clock signal is long, the time resolution for detecting the generation of the pulse signal can be secured. If the period of the global clock signal is long, the rising and falling intervals of the global clock signal supplied to the time measurement circuit 40 are wide. Therefore, even if the wiring from the clock driver 35 to the time measurement circuit 40 is long, and thus the rise time and the fall time of the pulse signal supplied to the time measurement circuit 40 are long, the rise and the fall of the global clock signal are easily recognized in the time measurement circuit 40. That is, the accuracy of light detection can be improved by achieving both the improvement of the accuracy of measurement time and the enlargement of the light detection surface.

For example, in the example shown in fig. 11, when the time measurement circuits 40 are arranged at a pitch of 100 μm while the frequency of the global clock signal is suppressed to 200MHz, the time measurement circuits 40 from the clock driver 35 to No. 128 are less susceptible to the influence of waveform collapse. Therefore, even if the area of the detection surface is large, the photodetection device can appropriately detect the generation of the pulse signal in each APD20 while ensuring the time resolution. When the clock driver 35 is provided on the circuit board 50, the wiring length from the clock driver 35 to the time measuring circuit 40 can be reduced.

If the frequency of the global clock signal is reduced, power consumption can be suppressed and the amount of heat generated from the clock driver 35 can also be reduced. Since the clock driver 35 is disposed on the circuit substrate 50 different from the APD array substrate 10, the distance between the clock driver 35 and each APD20 is further spaced apart than in the case where the clock driver 35 is formed on the same substrate as the APD 20. Since the clock driver 35 is provided on the circuit board 50, the density with which the clock driver 35 is formed can be relaxed. Therefore, heat generated by clock driver 35 is not easily transferred to APD 20. Therefore, erroneous detection of the measurement time can be suppressed.

Each time measurement circuit 40 has a coarse counter unit 45 that counts the global clock signal. Each time measuring circuit 40 acquires time information indicating the timing of inputting the pulse signal from the corresponding APD20, based on the operation result of the coarse counter unit 45 and the operation result of the delay line 47. Thus, a longer time measurement is achieved than can be measured by the delay line alone.

The coarse counter unit 45 starts operation in response to the stop of operation of the delay line 47, and stops operation in synchronization with the global clock signal from the clock driver 35. In this case, if no pulse signal is input from the corresponding APD20, the delay line 47 does not operate and the coarse counter unit 45 does not operate, so that power consumption can be reduced.

The plurality of time measurement circuits 40 are two-dimensionally arranged in a mounting region α overlapping with a light detection region β in which the plurality of APDs 20 are two-dimensionally arranged, and the clock driver 35 is disposed in a non-mounting region γ not overlapping with the light detection region β, as viewed from the thickness direction of the APD array substrate 10. Therefore, the influence of the heat generated by the clock driver 35 on each APD20 can be further reduced.

The quenching circuit connected to the APD20 is the active quenching circuit 41 and is formed on the circuit substrate 50. In the case where the semiconductor substrate 11 is made of a compound semiconductor, dark counts and residual pulses may occur more frequently than in the case where the semiconductor substrate 11 is made of silicon. By forming the active quenching circuit 41 on the circuit board 50, the quenching time can be easily realized, and noise due to the dark count and the residual pulse can be easily reduced.

The APD array substrate 10 and the circuit substrate 50 are connected by bump electrodes 70. Therefore, the influence of the heat generated by the clock driver 35 on each APD20 can be further reduced as compared with the case where the APD array substrate 10 and the circuit substrate 50 are connected by direct bonding or the like.

The circuit substrate 50 may also include a silicon substrate 51. In this case, the manufacturing process having the structures of the time measurement circuit 40 and the clock driver 35 described above can be simplified.

While the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention.

In the present embodiment, the coarse counter unit 45 counts the number of rises of the global clock signal from the stop of the operation of the delay line 47 of the fine unit 44 to the input of the stop signal. However, the coarse counter unit 45 may count the number of rises of the global clock signal from the time the reset signal is input to the control circuit 42 to the time the operation of the delay line 47 is stopped. In other words, the coarse counter unit 45 may count the number of rises of the global clock signal from the timing t1 to the timing t3 in fig. 8. In this case, the time interval from the input of the pulse signal from the APD20 based on the count to the rise of the input global clock signal is subtracted from the operation result of the coarse counter unit 45. Thus, the time interval from the input of the reset signal to the input of the pulse signal from the APD20 can be calculated. That is, the time interval from the input of the reset signal to the input of the pulse signal from the APD20 can be calculated by subtracting the operation result in the refinement unit 44 from the operation result of the coarse counter unit 45. In this case, each time measurement circuit 40 acquires time information indicating a timing at which the pulse signal from the APD20 is input to the reset signal.

The time measuring circuit 40 may not have the coarse counter section 45. In this case, the fine section 44 detects a time interval from when the pulse signal from the APD20 is input to when the stop signal is input. That is, in this case, each time measurement circuit 40 also acquires time information indicating the timing at which the pulse signal from APD20 is input to the stop signal. In this case, the structure of the time measurement circuit can be made simple.

In the present embodiment, the time measuring circuit 40 operates based on the rise of each pulse signal, but may operate based on the fall.

Description of the symbols

1 … light detection device, 10 … APD array substrate, 20 … APD, 35 … clock driver, 40 … time measurement circuit, 44 … fine detail part, 45 … coarse counter part, 50 … circuit substrate, 70 … bump electrode, alpha … mounting area, beta … light detection area and gamma … non-mounting area.