阅读说明：本技术 一种高介电常数栅介质材料及其制备方法 (High-dielectric-constant gate dielectric material and preparation method thereof ) 是由 夏经华 张文婷 田丽欣 安运来 田亮 查祎英 杨霏 吴军民 于 2020-06-10 设计创作，主要内容包括：本发明属于半导体器件制备技术领域,具体涉及一种高介电常数栅介质材料及其制备方法。该高介电常数栅介质材料,自下至上,包括依次叠加的AlN层、AlO<Sub>x</Sub>N<Sub>y</Sub>层和Al<Sub>2</Sub>O<Sub>3</Sub>层；该栅介质层具有较高的界面质量、界面态密度和高可靠性,同时该栅介质层的均匀性较好,漏电流的问题较少。(The invention belongs to the technical field of semiconductor device preparation, and particularly relates to a high-dielectric-constant gate dielectric material and a preparation method thereof. The high-dielectric-constant gate dielectric material comprises an AlN layer and AlO which are sequentially superposed from bottom to top x N y Layer and Al 2 O 3 A layer; the gate dielectric layer has high interface quality, interface state density and high reliability, and meanwhile, the gate dielectric layer has good uniformity and less leakage current problem.)

1. A high dielectric constant gate dielectric material is characterized by comprising an AlN layer and AlO which are sequentially superposed from bottom to top_xN_yLayer and Al₂O₃A layer;

wherein x and y are the molar ratio of AlO to AlN in the xAlO/yAlN layer, the value range of x is 1-10, and the value range of y is 1-10.

2. A method for preparing the high dielectric constant gate dielectric material of claim 1, comprising,

pretreating the silicon carbide epitaxial wafer;

then depositing an AlN layer, an xAlO/yAlN layer and an AlO layer on the silicon carbide epitaxial wafer in sequence;

forming an AlN layer and AlO in sequence after thermal annealing_xN_yLayer of Al₂O₃And (5) layering to obtain the gate dielectric material.

3. The production method according to claim 2, characterized in that the thermal annealing is performed under an atmosphere of nitrogen, argon, or nitrous oxide;

the thermal annealing adopts a rapid annealing method, the annealing temperature is 800-1200 ℃, and the time is 10-60 s; or the like, or, alternatively,

the temperature of the thermal annealing is 600-1000 ℃, and the time is 30-60 min.

4. The production method according to claim 2 or 3, characterized in that the xAlO/yAlN layers are obtained by alternately depositing AlO nanolayers and AlN nanolayers; wherein the molar ratio of AlO in the AlO nano layer to AlN in the AlN nano layer is x: y.

5. The method for preparing the AlO nanolayer of claim 4, wherein the reaction precursor A of the AlO nanolayer is TMA and the reaction precursor B is O₃Or H₂O；

The reaction precursor A of the AlN nano layer is TMA, and the reaction precursor B is N₂And/or H₂；

The deposition temperature of the AlO nano layer and the AlN nano layer is 200-350 ℃;

the thickness of the xAlO/yAlN layer is 10-100 nm.

6. The method of any one of claims 2-5, wherein the deposition method is an atomic layer deposition process;

the deposition temperature of the AlN layer is 100-350 ℃, the reaction precursor A is TMA, and the reaction precursor B is N₂And/or H₂The thickness of the AlN layer is 1-5 nm;

the deposition temperature of the AlO layer is 100-350 ℃, the reaction precursor A is TMA, and the reaction precursor B is O₃Or H₂And O, wherein the thickness of the AlO layer is 1-10 nm.

7. The method according to any one of claims 2 to 6, wherein the pretreatment comprises the steps of sequentially performing a first cleaning, ion implantation, a second cleaning, a high-temperature sacrificial oxidation treatment and a high-temperature surface treatment on the epitaxial wafer.

8. The method of claim 7, further comprising an etching step between the ion implantation and the second cleaning.

9. The preparation method according to claim 7 or 8, wherein the high-temperature sacrificial oxidation treatment specifically comprises an operation step of oxidizing the second cleaned silicon carbide epitaxial wafer at 1000-1400 ℃ for 10-30 min in an oxygen atmosphere to obtain a sacrificial oxide layer, and removing the sacrificial oxide layer by wet etching; wherein the flow rate of the oxygen is 0.1-10 slm, and the purity is 6N.

10. The production method according to any one of claims 7 to 9, wherein the high-temperature surface treatment comprises an operation step of subjecting the surface of the epitaxial wafer to a high-temperature surfacing treatment in an atmosphere of HCl gas; the temperature of the high-temperature surface treatment is 1000-1500 ℃, the time is 0.1-4 h, the purity of HCl is 6N, and the flow of HCl is 0.01-1 slm.

11. The production method according to any one of claims 7 to 10, wherein the silicon carbide epitaxial wafer comprises a substrate and an epitaxial layer;

the substrate is n-type 4H-SiC or 6H-SiC, and the thickness is 100-1000 mu m;

the substrate is a silicon carbide substrate heavily doped with nitrogen or phosphorus, and the resistivity is 0.001-0.1 omega cm; or the substrate is a vanadium doped or undoped semi-insulating silicon carbide substrate with the resistivity more than 10⁵Ω·cm；

The epitaxial layer is n-type 4H-SiC or 6H-SiC, and the thickness is 2-300 mu m.

12. The method of claim 11, wherein the epitaxial layer is a doped silicon carbide epitaxial layer with a doping concentration of 1 × 10¹³～1×10¹⁶cm^-3(ii) a Or the like, or, alternatively,

the epitaxial layer comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer;

the first epitaxial layer is an n-type nitrogen or phosphorus doped silicon carbide epitaxial wafer with the doping concentration of 1 × 10¹³～1×10¹⁶cm^-3The thickness of the first epitaxial layer is 2-300 mu m;

the second epitaxial layer is a p-type aluminum or boron doped silicon carbide epitaxial wafer with the doping concentration of 1 × 10¹⁵～1×10¹⁷cm^-3The thickness of the second epitaxial layer is 0.2-10 mu m;

the third epitaxial layer is an n-type nitrogen or phosphorus doped silicon carbide epitaxial wafer with the doping concentration of 1 ×10¹⁸～1×10²⁰cm^-3And the thickness of the third epitaxial layer is 0.1-0.5 mu m.

13. The method according to any one of claims 7-12, wherein the ion implantation comprises well region ion implantation, base contact region ion implantation, and source contact region ion implantation;

the ion implanted in the well region is aluminum or boron, the implantation depth is 0.2-1.0 μm, and the concentration is 1 × 10¹⁵～1×10¹⁷cm^-3；

The base contact region is implanted with aluminum or boron to an implantation depth of 0.1-0.8 μm and a concentration of 1 × 10¹⁹～1×10²¹cm^-3；

The ion implantation of the source contact region is nitrogen or phosphorus with an implantation depth of 0.1-0.5 μm and a concentration of 1 × 10¹⁸～1×10²⁰cm^-3。

Technical Field

The invention belongs to the technical field of semiconductor device preparation, and particularly relates to a high-dielectric-constant gate dielectric material and a preparation method thereof.

Background

As a model of the third generation wide band gap semiconductor material, the SiC semiconductor material has a wider 4H-SiC theoretical value of 3.2eV, a higher breakdown electric field intensity (2.2MV/cm), a higher saturated electron transfer rate (2.0 × 10)⁷cm/s), higher high thermal conductivity (5.0W/cm K), excellent physical and chemical stability and the like, and is suitable for being used as a manufacturing material of power semiconductor devices with high power, high voltage, high working temperature and high working frequency.

Compared with other compound semiconductor materials, SiC can be naturally oxidized like silicon to form dense SiO with high quality₂On one hand, the SiC process and the conventional CMOS process have higher process compatibility and maturity, and on the other hand, a corresponding gate medium growth process is provided for the SiC-based MOS device, so that the SiC power MOS device has a more mature manufacturing process.

At present, the high-temperature thermal oxidation process provides important technical support for the SiC-based MOSFET device, and becomes a mainstream process of the gate dielectric process. Although the high-temperature thermal oxidation process is used in the SiC-based MOSFET deviceThe process has been successfully applied, but it also has some important problems with respect to the oxidation process of Si, for example, (1) due to the high chemical stability of SiC (3.2 g-cm)^-3High atomic density andshort chemical bond length) so that the thermal oxidation temperature (1200-1400 ℃) is far higher than that of Si, thereby bringing about the problems of process-induced defects, including deep level traps, surface quality degradation and the like; (2) compared with the thermal oxidation of Si, the existence of C in SiC leads the thermal oxidation mechanism to be far more complicated than that of Si, and interface state defects which are at least 2 orders of magnitude higher than that of Si are generated, and SiC is oxidized to generate SiO₂During the oxidation process, the carbon residue generated by the oxidation reaction exists in the form of dangling bonds and carbon clusters, which causes SiC/SiO₂One of the main reasons for the presence of a higher density of interface states at the interface(s); (3) 4H-SiC which is a close-packed hexagonal crystal type has strong anisotropy, so that the oxidation rate and the oxidation quality of the 4H-SiC are different in different crystal directions, which has adverse effects on SiC devices with structures such as VMOS, UMOS and the like with a trench gate structure, the oxidation rate of the bottom of a trench gate needing a thicker oxidation layer is lower, the oxidation rate of a side wall channel part needing a thinner gate dielectric layer is higher, and the oxidation rates of different surfaces are different; (4) because the SiC has high critical breakdown electric field intensity (2.2-2.5 MV cm < -1 >) which is about 10 times of the critical breakdown electric field intensity of Si, SiO obtained by thermal oxidation₂Dielectric constant K of_ODielectric constant (K) of only 3.9, to SiC_O9.7) lower by a factor of 2.5, so that in SiC/SiO₂The electric field intensity distribution at the interface is due to SiO₂Higher electric field strength occurs on the side, so that the advantage of high breakdown electric field strength of SiC is limited.

Therefore, in response to the above problems, there is a need and room for improvement in the gate dielectric of SiC-based MOS devices, both in materials and in process methods. And the high dielectric constant (HK) material has natural advantages in the aspects of solving and optimizing electric field distribution at an interface and fully playing the advantage of high intrinsic critical electric field intensity of SiC. Currently, Chemical Vapor Deposition (CVD) processes by including Atomic Layer Deposition (ALD) processes are typical process techniques for depositing various HK dielectric materials.

HK dielectric material such as HfO₂And the like have been successfully used in 90nm processes and more advanced Si-based CMOS standard processes. However, for a wide bandgap semiconductor material such as SiC (bandgap width 3.2eV), an HK dielectric material is required to have a sufficiently wide bandgap, breakdown field strength and a sufficiently high dielectric constant at the same time. However, studies have shown that the forbidden bandwidth of a material is generally inverse to the dielectric constant, and therefore a compromise needs to be made in these parameters.

In the HK dielectric materials studied, Al₂O₃With its band gap width and breakdown field strength closest to that of SiO₂Can reach 8.8eV and 10eV, respectively, and the dielectric constant is about SiO₂2.5 times of the total weight of the product, and has excellent thermal stability. These make Al₂O₃Become a substitute for SiO₂The method is suitable for selecting the gate dielectric material of the SiC MOS device. Growing Al on 4H-SiC as gate dielectric and passivation dielectric material by growing/depositing in ALD, MOCVD, reactive ion sputtering, etc₂O₃The process of (a) has been widely studied. However, it has been found that the interface quality, leakage and reliability are not ideal and need to be improved because of the large lattice mismatch with SiC and the energy difference at the conduction band bottom of only 1.7 eV.

Disclosure of Invention

Therefore, the technical problem to be solved by the invention is to overcome the defects of poor interface quality, easy occurrence of electric leakage, poor reliability and the like of the gate dielectric material in the prior art, thereby providing the gate dielectric material with high dielectric constant and the preparation method thereof.

Therefore, the invention provides the following technical scheme.

The invention provides a high-dielectric-constant gate dielectric material which comprises an AlN layer and AlO layer which are sequentially superposed from bottom to top_xN_yLayer and Al₂O₃A layer;

wherein x and y are the molar ratio of AlO to AlN in the xAlO/yAlN layer, the value range of x is 1-10, and the value range of y is 1-10.

The invention also provides a method for preparing the high dielectric constant gate dielectric material, which comprises the following steps,

pretreating the silicon carbide epitaxial wafer;

then depositing an AlN layer, an xAlO/yAlN layer and an AlO layer on the silicon carbide epitaxial wafer in sequence;

forming an AlN layer and AlO in sequence after thermal annealing_xN_yLayer of Al₂O₃And (5) layering to obtain the gate dielectric material.

The thermal annealing is carried out in an atmosphere of nitrogen, argon or nitrous oxide;

the thermal annealing adopts a rapid annealing method, the annealing temperature is 800-1200 ℃, and the time is 10-60 s; or the like, or, alternatively,

the temperature of the thermal annealing is 600-1000 ℃, and the time is 30-60 min.

The xAlO/yAlN layer is obtained by alternately depositing an AlO nano layer and an AlN nano layer; wherein the molar ratio of AlO in the AlO nano layer to AlN in the AlN nano layer is x: y.

The reaction precursor A of the AlO nano layer is TMA, and the reaction precursor B is O₃Or H₂O；

The reaction precursor A of the AlN nano layer is TMA, and the reaction precursor B is N₂And/or H₂；

The deposition temperature of the AlO nano layer and the AlN nano layer is 200-350 ℃;

the thickness of the xAlO/yAlN layer is 10-100 nm.

The deposition method is an atomic layer deposition process;

the deposition temperature of the AlN layer is 100-350 ℃, the reaction precursor A is TMA, and the reaction precursor B is N₂And/or H₂The thickness of the AlN layer is 1-5 nm;

the deposition temperature of the AlO layer is 100-350 ℃, the reaction precursor A is TMA, and the reaction precursor B is O₃Or H₂And O, wherein the thickness of the AlO layer is 1-10 nm.

The pretreatment comprises the operation steps of sequentially carrying out first cleaning, ion implantation, second cleaning, high-temperature sacrificial oxidation treatment and high-temperature surface treatment on the epitaxial wafer.

The methods of the first cleaning and the second cleaning both comprise standard Piranha process cleaning, RCA process cleaning and DHF process cleaning.

And an etching step is also included between the ion implantation step and the second cleaning step.

The etching depth is determined according to the thickness of the epitaxial layer.

The high-temperature sacrificial oxidation treatment specifically comprises the operation steps of oxidizing the second cleaned silicon carbide epitaxial wafer for 10-30 min at 1000-1400 ℃ in an oxygen atmosphere to obtain a sacrificial oxide layer, and removing the sacrificial oxide layer through wet etching; wherein the flow rate of the oxygen is 0.1-10 slm, and the purity is 6N.

The thickness of the sacrificial oxide layer is 1-50 nm.

The solvent adopted by the wet etching is a DHF solution or a BOE solution with the concentration of 1-50%; the wet etching is performed at normal temperature.

The high-temperature surface treatment comprises the operation step of carrying out high-temperature surface treatment on the surface of the epitaxial wafer in an HCl gas environment; the temperature of the high-temperature surface treatment is 1000-1500 ℃, the time is 0.1-4 h, the purity of HCl is 6N, and the flow of HCl is 0.01-1 slm.

The silicon carbide epitaxial wafer comprises a substrate and an epitaxial layer;

the substrate is n-type 4H-SiC or 6H-SiC, and the thickness is 100-1000 mu m;

the substrate is a silicon carbide substrate heavily doped with nitrogen or phosphorus, and the resistivity is 0.001-0.1 omega cm; or the substrate is a vanadium doped or undoped semi-insulating silicon carbide substrate with the resistivity more than 10⁵Ω·cm；

The epitaxial layer is n-type 4H-SiC or 6H-SiC, and the thickness is 2-300 mu m.

The epitaxial layer is a doped silicon carbide epitaxial layer with the doping concentration of 1 × 10¹³～1×10¹⁶cm^-3(ii) a Or the like, or, alternatively,

the epitaxial layer comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer;

the first epitaxial layer is an n-type nitrogen or phosphorus doped silicon carbide epitaxial wafer with the doping concentration of 1 × 10¹³～1×10¹⁶cm^-3The thickness of the first epitaxial layer is 2-300 mu m;

the second epitaxial layer is a p-type aluminum or boron doped silicon carbide epitaxial wafer with the doping concentration of 1 × 10¹⁵～1 ×10¹⁷cm^-3The thickness of the second epitaxial layer is 0.2-10 mu m;

the third epitaxial layer is an n-type nitrogen or phosphorus doped silicon carbide epitaxial wafer with the doping concentration of 1 × 10¹⁸～1 ×10²⁰cm^-3And the thickness of the third epitaxial layer is 0.1-0.5 mu m.

The ion implantation comprises well region ion implantation, base electrode contact region ion implantation and source electrode contact region ion implantation;

the ion implanted in the well region is aluminum or boron, the implantation depth is 0.2-1.0 μm, and the concentration is 1 × 10¹⁵～1×10¹⁷cm^-3；

The base contact region is implanted with aluminum or boron to an implantation depth of 0.1-0.8 μm and a concentration of 1 × 10¹⁹～1×10²¹cm^-3；

The ion implantation of the source contact region is nitrogen or phosphorus with an implantation depth of 0.1-0.5 μm and a concentration of 1 × 10¹⁸～1×10²⁰cm^-3。

After the ion implantation process is finished, annealing all the ion implantation areas at 1500-2100 ℃ for 10-30 min under the protection of a protective mask and an inert atmosphere.

The technical scheme of the invention has the following advantages:

1. the high dielectric constant gate dielectric material provided by the invention comprises an AlN layer and AlO which are sequentially superposed from bottom to top_xN_yLayer and Al₂O₃A layer; the gate dielectric layer has high interface quality, interface state density and high reliability, and meanwhile, the gate dielectric layer has good uniformity and less leakage current problem.

2. The preparation method of the high dielectric constant gate dielectric material provided by the invention can form the composite HK gate dielectric optimized AlO with high dielectric constant and wide forbidden bandwidth after thermal annealing process by depositing an xAlO/yAlN layer_xN_yLayer of at least one of AlO_xN_yThe AlN layer is arranged below the layer, so that the interface structure of the gate dielectric material can be optimized, the interface quality is improved, and the interface state density is reduced; in AlO_xN_yAn AlO layer is arranged above the layer, and Al with wide forbidden band and high density can be introduced₂O₃(ii) a The preparation method provided by the invention can improve the quality of the gate dielectric material, reduce the density of the interface state of the dielectric, improve the voltage endurance capability of the SiC MOS power device and improve the leakage characteristic and reliability.

The AlN and the silicon carbide epitaxial wafer have a better bonding surface, the lattice mismatch is less than 1 percent, and the AlN layer, the xAlO/yAlN layer and the AlO layer can grow into compact, uniform and high-quality AlN/AlO after thermal annealing_xN_ythe/AlO composite gate dielectric material.

3. The preparation method of the high-dielectric-constant gate dielectric material provided by the invention is favorable for forming the AlO with high dielectric constant and wide forbidden bandwidth by adopting the ALD process to deposit the AlN and the AlO nano layer, adjusting the molar ratio of the AlO in the AlO nano layer to the AlN in the AlN nano layer and combining the thermal annealing process_xN_yA layer;

the thickness of the AlO nano layer can be controlled to be 0.1-5 nm and the thickness of the AlN nano layer to be 0.1-5 nm by adjusting the molar ratio of AlO in the AlO nano layer to AlN in the AlN nano layer and the thickness of the xAlO/yAlN layer.

The high-temperature sacrificial oxidation treatment is beneficial to eliminating the crystal lattice damage on the surface and the near surface of the SiC epitaxial wafer and reducing various defects (interface states) of the interface caused by the surface crystal lattice defect at the interface of the SiC/gate medium; the surface is subjected to high-temperature surface corrosion treatment through high-temperature HCl surface treatment, the treated SiC surface has atomic-level surface flatness, the surface roughness degradation caused by the SiC wafer and a later processing technology is improved and eliminated, and the interface flatness of the SiC/gate medium is improved. The combination of the two operation steps of the high-temperature sacrificial oxidation treatment and the high-temperature surface treatment is beneficial to improving the carrier channel mobility, the conduction characteristic, the stability and the reliability of the SiC power MOSFET device.

4. The preparation method of the high dielectric constant gate dielectric material provided by the invention has the advantages that the selected ALD technology has high uniformity of conventional Chemical Vapor Deposition (CVD), can deposit a uniform and controllable HK dielectric material with a complex structure on the surface of any complex shape, has the specific accuracy of controlling the thickness of the dielectric layer and the real low-temperature deposition process characteristic of the ALD technology, and avoids the problems of inconsistent thickness of oxide layers formed in different crystal directions caused by high interface state density and oxidized anisotropic characteristic due to interface quality degradation caused by the conventional high-temperature SiC thermal oxidation process.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic flow chart of a production process in example 1 of the present invention;

FIG. 2 is a schematic structural view of a silicon carbide epitaxial wafer in example 1 of the present invention;

fig. 3 is a schematic structural view after the ion implantation process is completed in embodiment 1 of the present invention;

FIG. 4 is a schematic structural view after completion of the high-temperature sacrificial oxidation treatment in example 1 of the present invention;

FIG. 5 is a schematic view of the structure after completion of the high-temperature surface treatment in example 1 of the present invention;

FIG. 6 is a schematic view of a structure after completion of deposition in example 1 of the present invention;

fig. 7 is a schematic structural view after the thermal annealing process is completed in embodiment 1 of the present invention;

FIG. 8 is a schematic structural view of a silicon carbide epitaxial wafer in example 2 of the present invention;

FIG. 9 is a schematic structural diagram after trench etching is completed in embodiment 2 of the present invention;

FIG. 10 is a schematic structural view after completion of the high-temperature sacrificial oxidation treatment in example 2 of the present invention;

FIG. 11 is a schematic structural view after completion of the high-temperature surface treatment in example 2 of the present invention;

FIG. 12 is a schematic view of a structure after completion of deposition in example 2 of the present invention;

fig. 13 is a schematic structural view after the thermal annealing process is completed in embodiment 2 of the present invention;

FIG. 14 is a schematic structural view of a silicon carbide epitaxial wafer in example 3 of the present invention;

fig. 15 is a schematic structural view after the ion implantation process is completed in embodiment 3 of the present invention;

FIG. 16 is a schematic structural view after completion of the high-temperature sacrificial oxidation treatment in example 3 of the present invention;

FIG. 17 is a schematic structural view after completion of the high-temperature surface treatment in example 3 of the present invention;

FIG. 18 is a schematic view of a structure after completion of deposition in example 3 of the present invention;

fig. 19 is a schematic structural view after completion of the thermal annealing process in embodiment 3 of the present invention;

FIG. 20 is a schematic structural view of a MOS capacitor according to an example of the invention;

FIG. 21 shows AlN/AlON/Al in the test examples of the present invention₂O₃Scanning electron microscopy of the gate dielectric material;

FIG. 22 shows C-V characteristics of a test MOS capacitor in a test example of the present invention;

FIG. 23 shows interface state density distribution characteristics of a test MOS capacitor according to an example of the present invention;

FIGS. 24 to 26 are views each showing Al in the test examples of the present invention₂O₃AlON composite HK material and AlN/AlON/Al₂O₃MOS capacitance TZDB test of gate dielectric materialThe resulting current characteristic (I-V) curve;

FIG. 27 shows the leakage current distribution of the test MOS capacitor of the invention at an electric field strength of 4 MV/cm;

FIG. 28 shows Weibull distribution of breakdown field strength of MOS capacitors tested in the test example of the present invention:

1-an aluminum gate electrode; 2-a gate dielectric material; 3-4H-SiC; 4-Ni bottom electrode.

Detailed Description

The following examples are provided to better understand the present invention, not to limit the best mode, and not to limit the content and scope of the present invention, and any product similar or similar to the present invention, which is obtained by combining the present invention with other prior art features or the teaching of the present invention, falls within the scope of the present invention.