阅读说明：本技术 半导体器件的制作方法 (Method for manufacturing semiconductor device ) 是由 蒋洋 于洪宇 汪青 于 2020-06-02 设计创作，主要内容包括：本发明实施例公开了一种半导体器件的制作方法,包括：氧化半导体外延片表面栅介质区域的势垒层以形成第一栅介质层；形成覆盖所述第一栅介质层的钝化层并在所述钝化层形成暴露部分第一栅介质层的第一开口；基于所述第一开口对暴露的第一栅介质层以及势垒层交替进行干法氧化和湿法刻蚀工艺,直至所述势垒层对应第一开口的位置被刻蚀到预设深度；氧化所述第一开口处被刻蚀预设深度后的势垒层以形成第二栅介质层；形成覆盖所述第二栅介质层的栅极。本发明实施例实现了势垒层刻蚀深度的精确控制,能有效避免势垒层过刻蚀或刻蚀未尽的现象发生,并且能有效降低刻蚀后势垒层的表面粗糙度,提升半导体器件的饱和电流,降低栅极漏电。(The embodiment of the invention discloses a manufacturing method of a semiconductor device, which comprises the following steps: oxidizing the barrier layer of the gate dielectric region on the surface of the semiconductor epitaxial wafer to form a first gate dielectric layer; forming a passivation layer covering the first gate dielectric layer and forming a first opening exposing a part of the first gate dielectric layer on the passivation layer; alternately carrying out dry oxidation and wet etching processes on the exposed first gate dielectric layer and the barrier layer based on the first opening until the barrier layer is etched to a preset depth at a position corresponding to the first opening; oxidizing the etched barrier layer with the preset depth at the first opening to form a second gate dielectric layer; and forming a grid electrode covering the second grid dielectric layer. The embodiment of the invention realizes the accurate control of the etching depth of the barrier layer, can effectively avoid the phenomenon that the barrier layer is over-etched or under-etched, can effectively reduce the surface roughness of the etched barrier layer, improves the saturation current of a semiconductor device and reduces the electric leakage of a grid electrode.)

1. A method for manufacturing a semiconductor device, comprising:

oxidizing the barrier layer of the gate dielectric region on the surface of the semiconductor epitaxial wafer to form a first gate dielectric layer;

forming a passivation layer covering the first gate dielectric layer and forming a first opening exposing a part of the first gate dielectric layer on the passivation layer;

alternately carrying out dry oxidation and wet etching processes on the exposed first gate dielectric layer and the barrier layer based on the first opening until the barrier layer is etched to a preset depth at a position corresponding to the first opening;

oxidizing the etched barrier layer with the preset depth at the first opening to form a second gate dielectric layer;

and forming a grid electrode covering the second grid dielectric layer.

2. The method of claim 1, wherein before forming the metal electrode on the surface of the barrier layer of the semiconductor epitaxial wafer, further comprising:

sequentially growing a buffer layer, a channel layer, a space isolation layer and a barrier layer on a substrate to form a semiconductor epitaxial wafer;

defining an ohmic contact pattern of a metal electrode on the surface of a barrier layer of the semiconductor epitaxial wafer through photoetching operation;

and forming a metal electrode in the ohmic contact pattern region by metal evaporation and metal stripping.

3. The method of claim 2, wherein the metal electrode comprises a source electrode and a drain electrode, and wherein oxidizing the barrier layer of the gate dielectric region on the surface of the semiconductor epitaxial wafer to form the first gate dielectric layer comprises:

defining a gate dielectric region on the surface of the barrier layer of the semiconductor epitaxial wafer through photoetching operation, wherein the gate dielectric region is a region between the source electrode and the drain electrode;

and placing the semiconductor epitaxial wafer in etching equipment, and introducing oxidizing gas into the etching equipment to oxidize the barrier layer in the gate dielectric region to form a first gate dielectric layer.

4. The method of claim 3, wherein forming a first opening in the passivation layer that exposes a portion of the first gate dielectric layer comprises:

defining a first opening pattern on the surface of the passivation layer through photoetching operation;

and placing the semiconductor epitaxial wafer in etching equipment, and introducing first etching gas into the etching equipment to etch away the passivation layer in the first opening pattern region to form a first opening exposing the first gate dielectric layer.

5. The method of claim 4, wherein alternately performing dry oxidation and wet etching processes on the exposed first gate dielectric layer and the barrier layer based on the first opening until the barrier layer is etched to a predetermined depth at a position corresponding to the first opening, comprises:

placing the semiconductor epitaxial wafer in etching equipment, and introducing second etching gas into the etching equipment to etch away the first gate dielectric layer exposed at the first opening so as to expose the barrier layer at the first opening;

and alternately carrying out dry oxidation and wet etching processes on the barrier layer exposed from the first opening until the position of the barrier layer corresponding to the first opening is etched to a preset depth.

6. The method of claim 5, wherein alternately performing a dry oxidation and a wet etching process on the barrier layer exposed by the first opening until the barrier layer is etched to a predetermined depth at a position corresponding to the first opening, comprises:

placing the semiconductor epitaxial wafer in etching equipment, and introducing oxidizing gas into the etching equipment to oxidize the barrier layer at the first opening to form an oxide layer;

placing the semiconductor epitaxial wafer with the oxide layer formed in a corrosive solution to remove the oxide layer;

and determining the etching depth of the position of the barrier layer corresponding to the first opening after the oxide layer is removed, and repeating the two steps until the etching depth reaches the preset depth.

7. The method of claim 6, wherein the oxidizing gas is oxygen at 40 seem and the corrosive solution is a diluted hydrochloric acid solution.

8. The method of claim 7, further comprising, after forming a gate overlying the second gate dielectric layer:

defining a source electrode pad opening pattern on the surface of the passivation layer of the source electrode and a drain electrode pad opening pattern on the surface of the passivation layer of the drain electrode through photoetching operation;

placing the semiconductor device in etching equipment, introducing first etching gas into the etching equipment, etching the passivation layer of the source pad opening pattern region to form a second opening exposing part of source metal, and etching the passivation layer of the drain pad opening pattern region to form a third opening exposing part of drain metal;

and forming a source electrode pad at the second opening through metal evaporation and metal stripping, and forming a drain electrode pad at the third opening.

9. The method of any of claims 3-8, wherein the etching apparatus is an inductively coupled plasma-reactive ion etching apparatus.

10.The method of claim 5, wherein the first etch gas is SF₆/Ar, the second etching gas is Cl₂/Ar。

Technical Field

The embodiment of the invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.

Background

Semiconductor (semiconductor) refers to a material having a conductive property between a conductor (semiconductor) and an insulator (insulator) at normal temperature, and has been widely used in various social fields due to controllability of the conductive property, wherein a GaN High Electron Mobility Transistor (HEMT) device is a hot point of research.

In the preparation process of the GaN HEMT device, the barrier layer of the GaN HEMT device is usually required to be etched to realize an enhancement type device or a depletion type device, but the traditional etching method is often difficult to accurately control the etching depth, the phenomenon of over-etching or incomplete etching is easily caused, the surface obtained by etching is rough, and the saturation current of the device can be reduced. There is also a method for implementing an enhancement device by using fluorine ion implantation, but the fluorine ion implantation technology has strong ion energy and is easy to cause great damage to the device, and meanwhile, fluorine ions have poor thermal stability at high temperature and are easy to influence the reliability of the device, thereby reducing the performance and service life of the device and being not beneficial to wide application.

Disclosure of Invention

In view of this, embodiments of the present invention provide a method for manufacturing a semiconductor device, so as to achieve accurate control of an etching depth, reduce roughness of an etched surface, and improve performance of the semiconductor device.

The embodiment of the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:

oxidizing the barrier layer of the gate dielectric region on the surface of the semiconductor epitaxial wafer to form a first gate dielectric layer;

forming a passivation layer covering the first gate dielectric layer and forming a first opening exposing a part of the first gate dielectric layer on the passivation layer;

alternately carrying out dry oxidation and wet etching processes on the exposed first gate dielectric layer and the barrier layer based on the first opening until the barrier layer is etched to a preset depth at a position corresponding to the first opening;

oxidizing the etched barrier layer with the preset depth at the first opening to form a second gate dielectric layer;

and forming a grid electrode covering the second grid dielectric layer.

Further, before forming the metal electrode on the surface of the barrier layer of the semiconductor epitaxial wafer, the method further comprises the following steps:

sequentially growing a buffer layer, a channel layer, a space isolation layer and a barrier layer on a substrate to form a semiconductor epitaxial wafer;

defining an ohmic contact pattern of a metal electrode on the surface of a barrier layer of the semiconductor epitaxial wafer through photoetching operation;

and forming a metal electrode in the ohmic contact pattern region by metal evaporation and metal stripping.

Further, the metal electrode includes a source electrode and a drain electrode, and the barrier layer of the gate dielectric region on the surface of the semiconductor epitaxial wafer is oxidized to form a first gate dielectric layer, including:

defining a gate dielectric region on the surface of the barrier layer of the semiconductor epitaxial wafer through photoetching operation, wherein the gate dielectric region is a region between the source electrode and the drain electrode;

and placing the semiconductor epitaxial wafer in etching equipment, and introducing oxidizing gas into the etching equipment to oxidize the barrier layer in the gate dielectric region to form a first gate dielectric layer.

Further, forming a first opening in the passivation layer to expose a portion of the first gate dielectric layer includes:

defining a first opening pattern on the surface of the passivation layer through photoetching operation;

and placing the semiconductor epitaxial wafer in etching equipment, and introducing first etching gas into the etching equipment to etch away the passivation layer in the first opening pattern region to form a first opening exposing the first gate dielectric layer.

Further, alternately performing dry oxidation and wet etching processes on the exposed first gate dielectric layer and the barrier layer based on the first opening until the barrier layer is etched to a preset depth at a position corresponding to the first opening, including:

placing the semiconductor epitaxial wafer in etching equipment, and introducing second etching gas into the etching equipment to etch away the first gate dielectric layer exposed at the first opening so as to expose the barrier layer at the first opening;

and alternately carrying out dry oxidation and wet etching processes on the barrier layer exposed from the first opening until the position of the barrier layer corresponding to the first opening is etched to a preset depth.

Further, alternately performing dry oxidation and wet etching processes on the barrier layer exposed by the first opening until the barrier layer is etched to a preset depth at a position corresponding to the first opening, including:

placing the semiconductor epitaxial wafer in etching equipment, and introducing oxidizing gas into the etching equipment to oxidize the barrier layer at the first opening to form an oxide layer;

placing the semiconductor epitaxial wafer with the oxide layer formed in a corrosive solution to remove the oxide layer;

and determining the etching depth of the position of the barrier layer corresponding to the first opening after the oxide layer is removed, and repeating the two steps until the etching depth reaches the preset depth.

Further, the oxidizing gas is oxygen gas of 40sccm, and the corrosive solution is a diluted hydrochloric acid solution.

Further, after forming a gate covering the second gate dielectric layer, the method further includes:

defining a source electrode pad opening pattern on the surface of the passivation layer of the source electrode and a drain electrode pad opening pattern on the surface of the passivation layer of the drain electrode through photoetching operation;

placing the semiconductor device in etching equipment, introducing first etching gas into the etching equipment, etching the passivation layer of the source pad opening pattern region to form a second opening exposing part of source metal, and etching the passivation layer of the drain pad opening pattern region to form a third opening exposing part of drain metal;

and forming a source electrode pad at the second opening through metal evaporation and metal stripping, and forming a drain electrode pad at the third opening.

Furthermore, the etching equipment is inductively coupled plasma-reactive ion etching equipment.

Further, the first etching gas is SF₆/Ar, the second etching gas is Cl₂/Ar。

According to the manufacturing method of the semiconductor device, provided by the embodiment of the invention, the barrier layer is etched through the dry oxidation and wet etching processes, so that the accurate control of the etching depth of the barrier layer is realized, the phenomenon that the barrier layer is over-etched or is not completely etched can be effectively avoided, the surface roughness of the etched barrier layer can be effectively reduced, the saturation current of the semiconductor device is improved, and the electric leakage of the grid electrode is reduced.

Drawings

Fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

fig. 2 is a flowchart of a method for manufacturing a semiconductor device according to a second embodiment of the present invention;

fig. 3A is a schematic structural diagram of a semiconductor epitaxial wafer according to a second embodiment of the present invention;

fig. 3B is a schematic structural diagram of a semiconductor epitaxial wafer for forming an isolation region according to a second embodiment of the present invention;

fig. 3C is a schematic structural diagram of a semiconductor epitaxial wafer for forming a metal electrode according to a second embodiment of the present invention;

fig. 3D is a schematic structural diagram of a semiconductor epitaxial wafer for forming a passivation layer according to a second embodiment of the present invention;

fig. 3E is a schematic structural diagram of a semiconductor epitaxial wafer for forming a first opening according to a second embodiment of the present invention;

fig. 3F is a schematic structural diagram of a semiconductor epitaxial wafer for forming a second gate dielectric layer according to a second embodiment of the present invention;

fig. 3G is a schematic structural diagram of a gate-forming semiconductor epitaxial wafer according to a second embodiment of the present invention;

fig. 3H is a schematic structural diagram of a semiconductor epitaxial wafer for forming pad openings according to a second embodiment of the present invention;

fig. 3I is a schematic structural diagram of a semiconductor device etched by half-etching according to a second embodiment of the present invention;

fig. 3J is a schematic structural diagram of a semiconductor device etched by using a full-process according to an alternative embodiment of the second embodiment of the present invention;

fig. 4A is a schematic structural diagram of a semiconductor epitaxial wafer for forming a metal electrode according to a third embodiment of the present invention;

fig. 4B is a schematic structural diagram of a semiconductor epitaxial wafer for forming a passivation layer according to a third embodiment of the present invention;

fig. 4C is a schematic structural diagram of a semiconductor epitaxial wafer for forming a gate pad according to a third embodiment of the present invention;

fig. 4D is a schematic structural diagram of a semiconductor device adopting non-recovery etching according to a third embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Before discussing exemplary embodiments in more detail, it should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although a flowchart may describe the steps as a sequential process, many of the steps can be performed in parallel, concurrently or simultaneously. In addition, the order of the steps may be rearranged. A process may be terminated when its operations are completed, but may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc.

Furthermore, the terms "first," "second," and the like may be used herein to describe various orientations, actions, steps, elements, or the like, but the orientations, actions, steps, or elements are not limited by these terms. These terms are only used to distinguish one direction, action, step or element from another direction, action, step or element. For example, a first opening may be referred to as a second opening, and similarly, a second opening may be referred to as a first opening, without departing from the scope of the present application. Both the first opening and the second opening are openings, but they are not the same opening. The terms "first", "second", etc. are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "plurality", "batch" means at least two, e.g., two, three, etc., unless specifically limited otherwise.