阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 颜逸飞 朱家仪 于 2020-03-27 设计创作，主要内容包括：本发明提供了一种半导体结构及其形成方法。通过使栅极结构侧边的衬底呈现为台阶状,从而使得金属硅化物层能够形成在源漏区其位于最低台阶的台面上,进而能够将金属硅化物层内陷在衬底的较深位置中,增加了金属硅化物层和栅极结构之间的距离。如此,即可有效改善在金属硅化物层的制备过程中以及金属硅化物层制备完成后出现的金属扩散至栅极结构的问题。(The invention provides a semiconductor structure and a forming method thereof. The substrate on the side of the gate structure is stepped, so that the metal silicide layer can be formed on the table top of the source drain region which is located at the lowest step, the metal silicide layer can be recessed in the deeper position of the substrate, and the distance between the metal silicide layer and the gate structure is increased. Therefore, the problem that metal diffuses to the grid structure in the preparation process of the metal silicide layer and after the preparation of the metal silicide layer is finished can be effectively solved.)

1. A semiconductor structure, comprising:

a substrate;

the grid structure is formed on the substrate, and at least part of the substrate on the side edge of the grid structure is sequentially recessed in a step shape in the direction far away from the grid structure so as to form a step part;

the source and drain regions are formed in the substrate on the side of the gate structure, and the top surfaces of the source and drain regions, which correspond to the step parts, are reduced in a gradient manner in the direction away from the gate structure;

the metal silicide layer is formed on the surface of the source drain region, which is positioned on the lowest step, and extends into the source drain region; and the number of the first and second groups,

and the contact plug is formed at the side of the gate structure, and the bottom of the contact plug extends to the metal silicide layer.

2. The semiconductor structure of claim 1, wherein the step portion has N steps, N is a positive integer greater than or equal to 2, wherein a mesa of a 1 st step of the N steps is lower than a surface of the substrate directly below the gate structure, and heights of the mesas from the 1 st step to the nth step decrease in order in a direction away from the gate structure.

3. The semiconductor structure of claim 2, further comprising at least N-1 isolation spacers, wherein the at least N-1 isolation spacers are respectively located on the mesa from the level 1 step to the level N-1 step of the step portion, and wherein the isolation spacers on some of the steps are aligned with the boundaries of the steps below and away from the sidewalls of the gate structure.

4. The semiconductor structure of claim 1, wherein the step portion comprises a first step and a second step, a mesa of the second step being lower than a mesa of the first step; the semiconductor structure further comprises a first isolation side wall and a second isolation side wall, and the first isolation side wall and the second isolation side wall sequentially cover the side wall of the grid structure;

the first isolation side wall is located on the table top of the first step, the side wall, far away from the grid structure, of the first isolation side wall is aligned with the boundary of the first step, the second isolation side wall is formed on the table top of the second step, and the side wall, far away from the grid structure, of the second isolation side wall is aligned with the boundary of the second step.

5. The semiconductor structure of claim 4, wherein the source and drain regions comprise a first doped region and a second doped region, wherein the first doped region extends from below the gate structure to below the second isolation sidewall, and the second doped region is connected to the first doped region and extends from below the second isolation sidewall in a direction away from the gate structure.

6. The semiconductor structure of claim 5, wherein the step portion further has a third step having a mesa lower than the mesa of the second step and a fourth step having a mesa lower than the mesa of the third step;

and at least one layer of isolation side wall is formed on the third step, the contact plug is positioned on one side of the at least one layer of isolation side wall, which is far away from the gate structure, part of the side wall of the contact plug is adjacent to the side wall of the outermost isolation side wall in the at least one layer of isolation side wall, and the bottom of the contact plug extends to the fourth step.

7. The semiconductor structure of claim 6, in which a center of the fourth step and a center of the second doped region are aligned.

8. The semiconductor structure of claim 6, wherein a third isolation sidewall and a fourth isolation sidewall are sequentially formed on the third step, and a top of the contact plug laterally extends to the third isolation sidewall, so that a top sidewall of the contact plug is adjacent to a sidewall of the third isolation sidewall, and a bottom sidewall of the contact plug is adjacent to a sidewall of the fourth isolation sidewall.

9. The semiconductor structure of claim 1, wherein a top width dimension of the contact plug is greater than a bottom width dimension of the contact plug, and a lateral width dimension of the metal silicide layer is greater than the bottom width dimension of the contact plug and less than the top width dimension of the contact plug.

10. A method of forming a semiconductor structure, comprising:

providing a substrate and forming a gate structure on the substrate;

forming a source drain region on the side edge of the gate structure, and sequentially etching the substrate to enable the part, located on the side edge of the gate structure, of the substrate to be sequentially recessed in a step shape in the direction away from the gate structure to form a step part, wherein the top surface, corresponding to the step part, of the source drain region is reduced in a gradient manner in the direction away from the gate structure;

forming a metal silicide layer on the surface of the source drain region at the lowest step, wherein the metal silicide layer also extends into the source drain region; and the number of the first and second groups,

and forming a contact plug at the side of the gate structure, wherein the bottom of the contact plug extends to the metal silicide layer.

11. The method for forming a semiconductor structure according to claim 10, wherein the forming method further comprises forming at least two layers of isolation spacers on sidewalls of the gate structure, and etching the substrate using the at least two layers of isolation spacers as a mask after forming a portion of the at least two layers of isolation spacers, so that a top surface of the substrate is recessed to form the step portion.

12. The method for forming a semiconductor structure according to claim 10, wherein the substrate is etched in sequence to form a step portion having N steps; the forming method of the step part of the N-level step comprises the following steps:

forming N-2 layers of isolation side walls, and etching the substrate after each isolation side wall is formed so that the surface of the substrate sinks in sequence to form a 1 st-level step to an N-2 nd-level step, wherein the N-2 layers of isolation side walls are respectively positioned on the table tops of the 1 st-level step to the N-2 nd-level step;

etching the (N-2) th step by taking the (N-2) th isolation side wall as a mask to enable part of the substrate to sink so as to form an (N-1) th step;

forming a dielectric layer on the substrate, wherein the dielectric layer covers the periphery of the isolation side wall and covers the source drain region; and the number of the first and second groups,

etching the dielectric layer to the substrate to expose the N-1 level step of the substrate, and further etching the mesa of the N-1 level step to enable the mesa to sink to form a contact window, wherein the bottom surface of the contact window is lower than the mesa of the N-1 level step and forms the N-level step of the step part.

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

Transistor devices are widely used as main devices in semiconductor integrated circuits, such as memories and logic circuits. Referring specifically to fig. 1, a transistor generally includes a gate structure 20 formed on a surface of a substrate 10 and a source/drain region 30 formed in the substrate 10 and located at a side of the gate structure 20, wherein the source/drain region 30 generally needs to be electrically extracted through a contact plug 50, that is, a bottom of the contact plug 50 extends to the substrate 10 to be electrically connected to the source/drain region 30.

Disclosure of Invention

The present invention is directed to a semiconductor structure to solve the problem that metal in a metal silicide layer is easy to diffuse into a gate structure.

To solve the above technical problem, the present invention provides a semiconductor structure, comprising:

a substrate;

the grid structure is formed on the substrate, and at least part of the substrate on the side edge of the grid structure is sequentially recessed in a step shape in the direction far away from the grid structure so as to form a step part;

the source and drain regions are formed in the substrate on the side of the gate structure, and the top surfaces of the source and drain regions, which correspond to the step parts, are reduced in a gradient manner in the direction away from the gate structure;

the metal silicide layer is formed on the surface of the source drain region, which is positioned on the lowest step, and extends into the source drain region; and the number of the first and second groups,

and the contact plug is formed at the side of the gate structure, and the bottom of the contact plug extends to the metal silicide layer.

Optionally, the step portion has N steps, where N is a positive integer greater than or equal to 2, a mesa of a 1 st step of the N steps is lower than a surface of the substrate right below the gate structure, and heights of the mesas from the 1 st step to the nth step decrease in sequence in a direction away from the gate structure.

Optionally, the semiconductor structure further includes at least N-1 layers of isolation side walls, where the at least N-1 layers of isolation side walls are respectively located on the mesa from the level 1 step to the level N-1 step of the step portion, and the isolation side walls on some of the steps are far away from the side wall of the gate structure and are aligned with the boundary of the step below the gate structure.

Optionally, the stepped portion includes a first step and a second step, and a mesa of the second step is lower than a mesa of the first step; the semiconductor structure further comprises a first isolation side wall and a second isolation side wall, and the first isolation side wall and the second isolation side wall sequentially cover the side wall of the grid structure;

the first isolation side wall is located on the table top of the first step, the side wall, far away from the grid structure, of the first isolation side wall is aligned with the boundary of the first step, the second isolation side wall is formed on the table top of the second step, and the side wall, far away from the grid structure, of the second isolation side wall is aligned with the boundary of the second step.

Optionally, the source-drain region includes a first doped region and a second doped region, where the first doped region extends from below the gate structure to below the second isolation sidewall, and the second doped region is connected to the first doped region and extends from below the second isolation sidewall toward a direction away from the gate structure.

Optionally, the stepped portion further has a third step and a fourth step, a mesa of the third step is lower than a mesa of the second step, and a mesa of the fourth step is lower than a mesa of the third step; and at least one layer of isolation side wall is formed on the third step, the contact plug is positioned on one side of the at least one layer of isolation side wall, which is far away from the gate structure, part of the side wall of the contact plug is adjacent to the side wall of the outermost isolation side wall in the at least one layer of isolation side wall, and the bottom of the contact plug extends to the fourth step.

Optionally, a center of the fourth step is aligned with a center of the second doped region.

Optionally, a top width dimension of the contact plug is greater than a bottom width dimension of the contact plug, and a lateral width dimension of the metal silicide layer is greater than the bottom width dimension of the contact plug and smaller than the top width dimension of the contact plug.

Another object of the present invention is to provide a method for forming a semiconductor structure, including:

providing a substrate and forming a gate structure on the substrate;

forming a source drain region on the side edge of the gate structure, and sequentially etching the substrate to enable the part, located on the side edge of the gate structure, of the substrate to be sequentially recessed in a step shape in the direction away from the gate structure to form a step part, wherein the top surface, corresponding to the step part, of the source drain region is reduced in a gradient manner in the direction away from the gate structure;

forming a metal silicide layer on the surface of the source drain region at the lowest step, wherein the metal silicide layer also extends into the source drain region; and the number of the first and second groups,

and forming a contact plug at the side of the gate structure, wherein the bottom of the contact plug extends to the metal silicide layer.

Optionally, the forming method further includes forming at least two layers of isolation side walls on the side walls of the gate structure, and etching the substrate by using part of the isolation side walls as a mask after forming part of the isolation side walls in the at least two layers of isolation side walls, so that the top surface of the substrate sinks to form the step portion.

Optionally, the substrate is etched in sequence to form a step part with N steps; the forming method of the step part of the N-level step comprises the following steps:

forming N-2 layers of isolation side walls, and etching the substrate after each isolation side wall is formed so that the surface of the substrate sinks in sequence to form a 1 st-level step to an N-2 nd-level step, wherein the N-2 layers of isolation side walls are respectively positioned on the table tops of the 1 st-level step to the N-2 nd-level step;

etching the (N-2) th step by taking the (N-2) th isolation side wall as a mask to enable part of the substrate to sink so as to form an (N-1) th step;

forming a dielectric layer on the substrate, wherein the dielectric layer covers the periphery of the isolation side wall and covers the source drain region; and the number of the first and second groups,

etching the dielectric layer to the substrate to expose the N-1 level step of the substrate, and further etching the mesa of the N-1 level step to enable the mesa to sink to form a contact window, wherein the bottom surface of the contact window is lower than the mesa of the N-1 level step and forms the N-level step of the step part.

In the semiconductor structure provided by the invention, the substrate surface at the side of the gate structure is stepped and has a step part, and the source and drain regions at least partially correspond to the step part, so that the metal silicide layer is formed on the surface of the lowest step corresponding to the source and drain regions, and at the moment, the metal silicide layer is correspondingly formed in the deeper position of the substrate, so that the distance between the metal silicide layer and the gate structure is effectively increased, and the problem that metal diffuses to the gate structure in the process of preparing the metal silicide layer and after the metal silicide layer is formed can be effectively improved. The method is favorable for improving the device performance of the formed semiconductor structure.

Drawings

FIG. 1 is a schematic diagram of a conventional semiconductor structure;

FIG. 2a is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

FIG. 2b is a schematic view of a semiconductor structure illustrating a substrate according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of another semiconductor structure in an embodiment of the invention;

FIG. 4 is a flow chart illustrating a method of forming a semiconductor structure according to an embodiment of the present invention;

fig. 5a to 5j are schematic structural views illustrating a method for forming a semiconductor structure in a manufacturing process according to an embodiment of the invention.

Wherein the reference numbers are as follows:

10/100-a substrate;

100 a-a first surface;

100 b-a second surface;

110-a step portion;

110 a-a first step;

110 b-a second step;

110 c-a third step;

110 d-fourth step;

20/200-gate structure;

210-a gate oxide layer;

220-a first gate conductive layer;

230-a second gate conductive layer;

240-third gate conductive layer;

250-a gate shield layer;

30/300-source drain regions;

310 — a first doped region;

320-a second doped region;

40/400-metal silicide layer;

50/500-contact plugs;

500 a-contact window;

510-a first conductive layer;

520-a second conductive layer;

610-first isolation sidewall spacers;

620-second isolation sidewall spacers;

630-a third isolation sidewall;

640-a fourth isolation sidewall;

700-dielectric layer.

Detailed Description

The semiconductor structure and the method for forming the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 2a is a schematic view of a semiconductor structure according to an embodiment of the invention, and fig. 2b is a schematic view of a semiconductor structure according to an embodiment of the invention, which mainly illustrates a structure of a substrate.

As shown in fig. 2a and 2b, the semiconductor structure in this embodiment includes: a substrate 100; a gate structure 200 formed on a top surface of the substrate 100; and source and drain regions 300 formed in the substrate 100. Specifically, the source/drain regions 300 are located on the side of the gate structure 200, and the source/drain regions 300 may be electrically led out by using a contact plug.

That is, the semiconductor structure further includes a contact plug 500, the contact plug 500 is formed at a side of the gate structure 200, and a bottom of the contact plug 500 further extends to the substrate 100 to electrically connect the source drain region 300.

With continued reference to fig. 2a, the semiconductor structure further includes a metal silicide layer 400, the metal silicide layer 400 is formed on the contact surface of the source/drain region 300 and extends into the source/drain region 300, and the bottom of the contact plug 500 extends to the metal silicide layer 400, so that the contact plug 500 contacts the metal silicide layer 400. That is, the metal silicide layer 400 is formed between the source/drain region 300 and the contact plug 500, so that the source/drain region 300 and the contact plug 500 can be electrically connected through the metal silicide layer 400, which is beneficial to reducing the contact resistance between the source/drain region 300 and the contact plug 500.

Referring to fig. 2b, at least a portion of the substrate 100 on the side of the gate structure 200 is recessed in a step-like manner in a direction away from the gate structure 200 to form a step portion 110. In this embodiment, the step portion 110 is adjacent to the gate structure 200 and extends away from the gate structure 200.

In a specific embodiment, the step portion 110 includes N steps, for example, where N is a positive integer greater than or equal to 2. And the N steps, that is, the corresponding mesas with N different mesa heights, and the mesa heights of the N steps decrease sequentially in the direction away from the gate structure 200, for example, the N steps include a 1 st step and a 2 nd step … … nth step extending and arranged sequentially in the direction away from the gate structure 200, where the mesa height of the 1 st step is the highest, and the mesa height of the nth step is the lowest.

Note that the top surface of the substrate (i.e., the second surface 100b) on the side of the step portion 110 away from the gate structure 200 may be lower than the top surface of the substrate (i.e., the first surface 100a) directly below the gate structure; alternatively, the top surface of the substrate (i.e., the second surface 100b) on the side of the stepped portion 110 away from the gate structure 200 may be flush with the top surface of the substrate (i.e., the first surface 100a) directly below the gate structure. For example, in the present embodiment, the top surface of the substrate (i.e., the second surface 100b) on the side of the stepped portion 110 away from the gate structure 200 is lower than the top surface of the substrate (i.e., the first surface 100a) directly below the gate structure and is higher than the lowest mesa of the stepped portion 110.

Further, the source drain region 300 has a portion corresponding to the step portion 110. Specifically, the source/drain regions 300 are formed on the side of the gate structure 200 and extend along a direction away from the gate structure 200, so that the source/drain regions 300 extend to at least the lowest mesa position of the step portion 110. The top surface of the source/drain region 300 corresponding to the step portion 100 is correspondingly reduced in a gradient manner in a direction away from the gate structure 200, that is, at least a portion of the top surface of the source/drain region 300 conforms to the mesa of the step portion 110 in a step shape. In this embodiment, the source/drain regions 300 further extend laterally to the position of the second surface 100 b.

With reference to fig. 2a and fig. 2b, the metal silicide layer 400 is formed on the surface of the source/drain region 300 at the lowest step and extends into the source/drain region 300. That is, the metal silicide layer 400 is formed on the mesa of the N-level step farthest from the gate structure 200 (e.g., the metal silicide layer 400 is formed on the mesa of the N-th step thereof).

It should be noted that, in the preparation of the metal silicide layer 400, the metal is usually formed by reacting with silicon in the substrate 100, and in the process, the metal diffuses in the substrate 100 to form the metal silicide layer 400 with a certain thickness. Therefore, when the formed metal silicide layer is closer to the gate structure, the metal is likely to diffuse into the gate structure during the process of preparing the metal silicide layer or after the metal silicide layer is formed, thereby affecting the device performance, for example, causing the leakage current phenomenon and poor contact of the device.

For example, referring to fig. 1, in the conventional semiconductor structure, the metal silicide layer 40 is closer to the gate structure 20, and especially, the top position of the metal silicide layer 40 and the bottom position of the gate structure 20 are both located at the same height position (i.e., the top of the metal silicide layer 20 extends to the top surface of the substrate 10, and the bottom of the gate structure 20 is formed on the top surface of the substrate 10), so that the metal in the metal silicide layer 40 is easily laterally diffused to the gate structure 20 when laterally diffused.

However, in this embodiment, as shown in fig. 2a and fig. 2b, since the substrate 100 at the side of the gate structure 200 has the step portion 110, the top surface of the source/drain region 300 correspondingly has a step-shaped portion, and the metal silicide layer 400 is further formed on the mesa of the source/drain region 300 located at the lowest step, so that the metal silicide layer 400 is recessed in a deeper position of the substrate 100, and the top position of the metal silicide layer 400 is lower than the bottom position of the gate structure 200. At this time, the metal silicide layer 400 is located obliquely below the gate structure 200, that is, the distance between the metal silicide layer 400 and the gate structure 200 is increased, and when there is metal diffusion, since metal particles are difficult to cross the N-level step and thus difficult to diffuse to the gate structure 200, the problem of metal diffusion to the gate structure 200 during the preparation of the metal silicide layer 400 and after the preparation of the metal silicide layer 400 is completed is effectively improved.

With continued reference to fig. 2a and 2b, in the present embodiment, the step part 110 having 4 steps is taken as an example for explanation. Specifically, the step portion 110 includes a first step 110a, a second step 110b, a third step 110c and a fourth step 110d, which are sequentially arranged along a direction away from the gate structure. The mesa of the second step 110b is lower than the mesa of the first step 110a, the mesa of the third step 110c is lower than the mesa of the second step 110b, and the mesa of the fourth step 110d is lower than the mesa of the third step 110c, that is, the mesa of the first step 110a is the highest, and the mesa of the fourth step 110d is the lowest.

In this embodiment, the first step 110a has a lower mesa than the first surface 100a, and the second surface 100b is flush with the mesa of the third step 110 c.

And, the source drain region 300 laterally extends from the gate structure 300 to at least the fourth step 110d, and based on this, the metal silicide layer 400 is formed on the surface of the fourth step 110 d.

It should be noted that, in this embodiment, the mesa of the 1 st step (e.g., the first step 110a in this embodiment) of the N steps is lower than the top surface of the substrate (i.e., the first surface 100a) directly below the gate structure, and the mesas of the 2 nd step to the nth step are sequentially decreased, that is, the mesa height position of the 1 st step with the highest mesa among the N steps in this embodiment is still lower than the bottom position of the gate structure 200. It should be appreciated, however, that in other embodiments, the mesa of the level 1 step of the N steps may be flush with the top surface of the substrate (i.e., the first surface 100a) directly below the gate structure.

With continued reference to fig. 2a, the semiconductor structure further includes at least two layers of isolation spacers, and the at least two layers of isolation spacers sequentially cover the sidewalls of the gate structure 200. And at least part of the at least two side isolation side walls are located on different mesas of the step part 110. For example, in the at least two layers of isolation side walls, part of the isolation side walls are formed on the mesa of the 1 st step, and part of the isolation side walls are formed on the mesa of the 2 nd step. It should be appreciated that each step may have one or more isolation sidewall spacers formed on the mesa.

Further, the at least two layers of isolation side walls include at least N-1 layers of isolation side walls, and the at least N-1 layers of isolation side walls are respectively located on the mesa from the level 1 step to the level N-1 step of the step portion 110. That is, in the N-level steps of the step portion 110, an isolation sidewall is formed on the mesa from the 1 st step to the N-1 st step, a metal silicide layer 400 is formed on the mesa of the N-level step, and the electrical contact between the contact plug 500 and the metal silicide layer 400 is realized on the mesa of the N-level step.

In this embodiment, the width of the mesa of a part of the steps can be defined by using the isolation sidewall, which will be described in detail in a subsequent step forming method. Based on this, the side wall of the isolation side wall on the partial step, which is far away from the gate structure, can be aligned with the boundary of the step below the isolation side wall. For example, the at least two layers of isolation side walls may include at least N-1 layers of isolation side walls, wherein the 1 st isolation layer to the N-2 nd isolation side walls in the N-1 layers of isolation side walls are formed on the mesa of the 1 st step to the N-2 nd step of the step portion 110 in a one-to-one correspondence, and the side walls of the 1 st isolation layer to the N-2 nd isolation side walls are aligned with the boundaries of the 1 st step to the N-2 nd step one by one.

That is to say, in the present embodiment, the at least two layers of isolation spacers are not only used to cover the gate structure 200 to isolate and protect the gate structure, but also used to define the step width and position of the step portion 110, and further define the formation position of the metal silicide layer 400. Based on this, it is equivalent to that the formation position of the metal silicide layer 400 can be effectively controlled by using the at least two isolation spacers. For example, the number of steps of the step 110 may be increased by increasing the number of layers of the isolation sidewall spacer, so that the metal silicide layer 400 may be formed in a deeper position of the substrate 100.

Specifically, in this embodiment, the step portion 110 includes a first step 110a, a second step 110b, a third step 110c and a fourth step 110d, and the at least two layers of isolation side walls include a first isolation side wall 610 and a second isolation side wall 620. The first isolation sidewall spacers 610 cover the sidewalls of the gate structure 200, and the second isolation sidewall spacers 620 cover the sidewalls of the first isolation sidewall spacers 610 far away from the gate structure 200. And the first isolation sidewall 610 is located on the mesa of the first step 110a, the sidewall of the first isolation sidewall 610 far from the gate structure 200 is aligned with the boundary of the first step 110a, the second isolation sidewall 620 is formed on the mesa of the second step 110b, and the sidewall of the second isolation sidewall 620 far from the gate structure 200 is aligned with the boundary of the second step 110 b. At this time, the bottom position of the second isolation sidewall 620 is correspondingly lower than the bottom position of the first isolation sidewall 610.

It is considered that, in the present embodiment, the first isolation sidewall 610 defines the mesa width of the first step 110a (i.e., the first isolation sidewall 610 defines the boundary of the first step 110a away from the gate structure), and the second isolation sidewall 620 defines the mesa width of the second step 110b (i.e., the second isolation sidewall 620 defines the boundary of the second step 110b away from the gate structure), which is equivalent to the second isolation sidewall 620 defining the boundary of the third step 110c close to the gate structure.

In addition, in the present embodiment, the fourth step 110d may be defined by a patterning process. For example, in the process of preparing a contact window to form the contact plug 500, the substrate 100 may be directly etched, so that the surface of the etched substrate is sunken relative to the mesa of the third step 110c, thereby forming the fourth step 110 d. It can be considered that the fourth step 110d is formed by etching a portion of the mesa of the third step 110 c.

It should be noted that, in the present embodiment, the 1 st step (i.e., the first step 110a) is sunken with respect to the first surface 100a of the substrate 100, and the boundary of the 1 st step near the gate structure 200 is aligned with the sidewall of the gate structure 200. It can be considered that the first step 110a is defined by the gate structure 200 near the boundary of the gate structure.

With continued reference to fig. 2a and 2b, the at least two isolation side walls further include a third isolation side wall 630, the third isolation side wall 630 covers a side wall of the second isolation side wall 620 away from the gate structure 200, and the third isolation side wall 630 is located on a mesa of the third step 110 c. At this time, the bottom position of the third isolation sidewall 630 is correspondingly lower than the bottom position of the second isolation sidewall 620.

In this embodiment, the isolation material layer for forming the third isolation sidewall 630 further covers the second surface 100b of the side of the step portion 110. Specifically, the source/drain regions 300 laterally extend to a position corresponding to the second surface 100b, and the isolation material layer also covers the second surface 100b, so that the isolation material layer can cover the source/drain regions 300 correspondingly.

Further, the at least two layers of isolation side walls further include a fourth isolation side wall 640, and the fourth isolation side wall 640 is formed on the third isolation side wall 630. In this embodiment, the fourth isolation sidewall 640 and the third isolation sidewall 630 are both formed on the third step 110c, and the isolation material layer for forming the fourth isolation sidewall 640 further covers the second surface 100b of the side edge of the step portion 110. That is, the isolation material layer used to form the fourth isolation sidewall spacers 640 covers the isolation material layer used to form the third isolation sidewall spacers 630.

With continued reference to fig. 2a and 2b, the source drain region 300 includes a first doped region 310 and a second doped region 320, the doping concentration of the first doped region 310 is lower than the doping concentration of the second doped region 320, the first doped region 310 is closer to the gate structure 200 and extends to the lower side of the gate structure 200, and the second doped region 320 is connected to the first doped region 310 and extends to the direction away from the gate structure 200.

In this embodiment, the first doped region 310 laterally extends from the bottom of the gate structure 200 to the bottom of the second isolation sidewall 620 (i.e., the first doped region 310 further extends from the bottom of the gate structure 200 to the second step 110b through the first step 110a), and the second doped region 320 laterally extends from the second step 110b to the fourth step 110d and can further extend to the position of the second surface 100 b. At this time, the highest top position of the second doped region 320 is correspondingly lower than the highest top position of the first doped region 310.

In a specific embodiment, the semiconductor structure further includes a dielectric layer 700, where the dielectric layer 700 at least covers the outer side of the gate structure 200 and covers the substrate 100 at the side of the gate structure. In this embodiment, the dielectric layer 700 covers the outer sidewalls of the at least two layers of isolation spacers.

Further, the contact plug 500 penetrates through the dielectric layer 700 to extend to the substrate 100, and is electrically connected to the source drain region 300. In this embodiment, the dielectric layer 700 covers the sidewalls of the fourth isolation sidewall spacers 640, the contact plugs 500 are formed at positions of the dielectric layer 700 close to the fourth isolation sidewall spacers 640, and a part of the sidewalls of the contact plugs 500 are adjacent to the sidewalls of the fourth isolation sidewall spacers 640.

It can be understood that the at least two isolation spacers can be used to isolate the contact plug 500 from the word line 200, and an outermost isolation spacer (for example, the fourth isolation spacer 640 in this embodiment) of the at least two isolation spacers can also be used as a boundary barrier layer to control a forming position of the contact plug 500, so that the contact plug 500 can be controlled at a side of the outermost isolation spacer away from the gate structure (for example, so that a part of a sidewall of the contact plug 500 is adjacent to a sidewall of the outermost isolation spacer). By controlling the formation position of the contact plug 500, the isolation performance between the contact plug 500 and the word line 200 can be ensured, the coupling performance between the contact plug 500 and the word line 200 can be effectively improved based on the isolation of the multilayer isolation side wall, and the parasitic capacitance is reduced.

In a further aspect, the at least two isolation side walls may be formed of at least two materials. For example, the material of part of the isolation sidewall spacers comprises silicon oxide, and the material of the other part of the isolation sidewall spacers comprises silicon nitride and the like. In this embodiment, the first isolation sidewall spacers 610 are made of silicon nitride, the second isolation sidewall spacers 620 are made of silicon oxide, the third isolation sidewall spacers 630 are made of silicon oxide, and the fourth isolation sidewall spacers 640 are made of silicon nitride.

In addition, the material of the outermost isolation sidewall of the at least two isolation sidewalls may be different from the material of the dielectric layer 700, so that when the dielectric layer 700 is etched to prepare the contact plug 500, the outermost isolation sidewall can be used to realize the side etching blocking. That is, in this embodiment, the material of the fourth isolation sidewall spacer 640 is different from the material of the dielectric layer 700, for example, the material of the fourth isolation sidewall spacer 640 includes silicon nitride, and the material of the dielectric layer 700 includes silicon oxide.

It should be noted that, in an alternative scheme, when the contact window is formed by etching, the outermost isolation sidewall is used to realize etching blocking, and at this time, only a small amount of the outermost isolation sidewall is consumed, so that at least the top sidewall of the contact plug filled in the contact window is adjacent to the outermost isolation sidewall. For example, referring to fig. 2a, the top sidewall of the contact plug 500 abuts the sidewall of the outermost isolation sidewall (i.e., the fourth isolation sidewall 640).

In other schemes, the outermost isolation sidewall may be further consumed when the contact window is formed by etching, for example, the top of the outermost isolation sidewall is consumed, and the bottom of the outermost isolation sidewall is reserved, so that the top sidewall of the contact plug filled in the contact window can be adjacent to the inner isolation sidewall, and the bottom sidewall of the contact plug can be adjacent to the outermost isolation sidewall. For example, referring to fig. 3, the top of the contact plug 500 extends laterally to the third isolation sidewall 630, so that the top sidewall of the contact plug 500 is adjacent to the sidewall of the third isolation sidewall 630, and the bottom sidewall of the contact plug 500 is adjacent to the sidewall of the fourth isolation sidewall 640.

As described above, in the present embodiment, the fourth step 110d may be formed by etching a portion of the mesa of the third step 110c when the contact window of the contact plug 500 is prepared. Specifically, before the contact window is formed, the isolation material layer used for forming the third isolation sidewall 630 and the isolation material layer used for forming the fourth isolation sidewall 640 may extend to cover the mesa of the third step 110c, and when the contact window is formed, the dielectric layer 700 and the isolation material layer are sequentially etched, and the mesa of the third step 110c is further etched, so as to form the recessed fourth step 110 d.

It is understood that the formation position of the contact plug 500 may be adjusted by forming one or more isolation spacers on the third step 110c, and at this time, the position of the fourth step 110d and the position of the metal silicide layer 400 may be adjusted accordingly. For example, the center of the fourth step 110d and the center of the second doped region 320 may be adjusted to be aligned, thereby enabling the metal silicide layer 400 and the contact plug 500 to be formed at the center of the second doped region 320.

With continued reference to fig. 2a, in the present embodiment, the mesa of the recessed fourth step 110d is an arc-shaped surface, and the metal silicide layer 400 is formed on the arc-shaped surface and further expands inward. And, the contact plug 500 sequentially penetrates through the dielectric layer 700 and the isolation material layer to extend to the metal silicide layer 400, and is further connected with the metal silicide layer 400.

Further, a top width dimension of the contact plug 500 is greater than a bottom width dimension of the contact plug 500, and a lateral width dimension of the metal silicide layer 400 is greater than the bottom width dimension of the contact plug 500 and less than the top width dimension of the contact plug 500.

As shown with continued reference to fig. 2a, the contact plug 500 includes a first conductive layer 510 and a second conductive layer 520. Wherein the first conductive layer 510 covers the contact window bottom wall and the sidewall, i.e. correspondingly covers the metal silicide layer 400; and, the second conductive layer 520 is formed on the first conductive layer 510 and fills the contact window.

It should be noted that in the solution shown in fig. 2a, only one gate structure 200 is illustrated, thereby forming a transistor device. However, in other schemes (for example, as shown in fig. 3), the gate structures 200 may be formed on both sides of the same source/drain region 300 to respectively form two transistor devices, and the two formed transistor devices share the source/drain region 300. Further, in the semiconductor structure shown in fig. 3, the common source/drain regions 300 are symmetrically disposed with the second doped region 320, and two mutually symmetric step portions 110 are correspondingly disposed between the two gate structures 200.

Based on the semiconductor structure as described above, a method for forming the semiconductor structure will be described in detail below. Fig. 4 is a flowchart illustrating a method for forming a semiconductor structure according to an embodiment of the invention, and fig. 5a to 5j are structural diagrams illustrating the method for forming a semiconductor structure according to an embodiment of the invention during a manufacturing process thereof. The steps for forming the semiconductor structure in this embodiment will be described in detail with reference to the drawings.

In step S100, specifically referring to fig. 5a, a substrate 100 is provided, and a gate structure 200 is formed on the substrate 100.

The gate structure 200 may include a gate oxide layer 210, a first gate conductive layer 220, a second gate conductive layer 230, a third gate conductive layer 240, and a gate shielding layer 250, which are sequentially stacked from bottom to top. Specifically, the material of the first gate conductive layer 220 includes, for example, polysilicon, the material of the second gate conductive layer 230 includes, for example, titanium nitride or titanium, the material of the third gate conductive layer 240 may include tungsten, and the material of the gate shielding layer 250 includes, for example, silicon nitride.

In step S200, specifically referring to fig. 5b to 5e, forming a source/drain region 300 on a side of the gate structure 200, and sequentially etching the substrate 100, so that portions of the substrate 100 on the side of the gate structure 200 are sequentially recessed in a step shape in a direction away from the gate structure 200, so as to form a step portion 110, wherein a top surface of the source/drain region 300 corresponding to the step portion 110 is reduced in a gradient manner in a direction away from the gate structure 200.

Wherein, a part of the steps in the step part 110 may be defined by at least two layers of isolation sidewalls. For example, at least two layers of isolation side walls may be formed, and after a part of the at least two layers of isolation side walls is formed, the substrate 100 is etched by using the part of the isolation side walls as a mask, so that the top surface of the substrate 100 sequentially sinks to form the step 110.

In an optional scheme, at least N-2 layers of isolation side walls may be formed to define a level 1 step to a level N-2 step of the N-level step 110 (at this time, the at least N-2 layers of isolation side walls are respectively located on a mesa from the level 1 step to the level N-2 step of the step 110), and the level N-2 step is etched by using the level N-2 isolation side walls as a mask to sink a part of the substrate, thereby forming the level N-1 step with a lower mesa. And the nth step may be formed by etching the nth-1 step in the process of preparing the contact plug.

In the present embodiment, the step portion 110 having 4 steps is formed as an example for explanation. And, the source drain region 300 may be formed in the process of preparing the isolation sidewall and the step portion 110. Specifically, the method for forming the source/drain regions 300 and the step portion 110 of the substrate 100 includes the following steps, for example.

First, referring to fig. 5b specifically, the gate structure 200 is used as a mask to etch the substrate 100 on the side of the gate structure 200, so that the substrate surface on the side of the gate structure 200 sinks to form a first step 110a of the step 110. At this time, the mesa of the first step 110a is correspondingly lower than the first surface 100a directly below the gate structure.

A second step, specifically referring to fig. 5c, forming a first isolation sidewall 610, where the first isolation sidewall 610 at least covers the sidewall of the gate structure 200, and a bottom of the first isolation sidewall 610 is located on the first step 110 a. In this embodiment, the isolation material layer used for forming the first isolation sidewall spacers 610 also covers the top surface of the gate structure 200.

A third step, continuing to refer to fig. 5c, forming a first doped region 310 in the substrate 100 and located at a side of the first isolation sidewall 610, and the first doped region 310 further diffuses to a lower portion of the gate structure 200 through the first isolation sidewall 610.

Further, the forming method of the first doped region 310 includes, for example, an ion implantation process and a thermal annealing process, so that the implanted ions can diffuse to the lower side of the gate structure 200 through the first isolation sidewall spacers 610.

A fourth step, specifically referring to fig. 5d, using the first isolation sidewall 610 as a mask, etching the substrate 100 at the side of the first isolation sidewall 610, so that the substrate surface at the side of the first isolation sidewall 610 sinks to form the second step 110b of the step portion 110. At this time, the mesa of the second step 110b is correspondingly lower than the mesa of the first step 110 a.

It should be appreciated that the step width of each step can be adjusted by adjusting the thickness of the isolation sidewall. For example, the width of the mesa of the first step 110a can be adjusted by adjusting the thickness of the first isolation sidewall 610, and accordingly, the boundary position of the second step 110b close to the gate structure 200 is adjusted.

In addition, the order of the third step of forming the first doping region 310 and the fourth step of etching the substrate to form the second step 110b may be adjusted. For example, in other embodiments, the substrate may be etched to form the second step, and then an ion implantation process is performed to form the first doped region.

A fifth step, specifically referring to fig. 5e, forming a second isolation sidewall 620, where the second isolation sidewall 620 covers the sidewall of the first isolation sidewall 610, and the bottom of the second isolation sidewall 620 is located on the second step 110 b.

In the subsequent process, the substrate 100 is further etched by using the second isolation sidewall 620 as a mask to further form a third step, and similarly, the width of the mesa of the second step 110b can be correspondingly adjusted by adjusting the width of the second isolation sidewall 620.

A sixth step, specifically referring to fig. 5f, etching the substrate 100 on the side of the second isolation sidewall 620 by using the second isolation sidewall 620 as a mask, so that the substrate surface on the side of the second isolation sidewall 620 sinks to form a third step 110c of the step 110. At this time, the mesa of the third step 110c is correspondingly lower than the mesa of the second step 110 b.

And forming a second doped region 320 in the substrate 100 and located at a side of the second isolation sidewall 620, wherein the second doped region 320 is connected to the first doped region 310 below the second isolation sidewall 620. Wherein the doping concentration of the second doping region 320 is higher than the doping concentration of the first doping region 310, and the second doping region 320 is diffused in a deeper position of the substrate with respect to the first doping region 310.

Likewise, the order of the step of forming the second doping region 320 and the step of etching the substrate to form the third step 110c may be adjusted. For example, in other embodiments, an ion implantation process may be performed to form the second doped region 320, and then the substrate is etched to form the third step 110 c.

Further, referring to fig. 5g, after the third step 110c is formed, the method further includes: a third isolation sidewall 630 and a fourth isolation sidewall 640 are sequentially formed on the third step 110 c. And the isolation material layer for forming the third and fourth isolation sidewalls 630 and 640 further extends to cover the mesa of the third step 110c, so that the isolation material layer further covers the surface of the second doped region 320.

With continued reference to fig. 5g, the method of forming the semiconductor structure further includes: forming a dielectric layer 700 on the substrate 100, wherein the dielectric layer 700 covers the periphery of the isolation sidewall spacer and covers the source drain region 300. The material of the dielectric layer 700 may be different from the material of the outermost isolation sidewall, that is, in this embodiment, the material of the dielectric layer 700 is different from the material of the fourth isolation sidewall 640. For example, the material of the dielectric layer 700 includes silicon oxide, and the material of the fourth isolation sidewall spacer 640 includes silicon nitride.

It should be noted that, in the present embodiment, in the process of forming the step portion 110 with N steps, the 1 st step to the N-2 nd step may be defined by using an isolation sidewall. For example, the method of forming the 1 st step to the N-2 nd step includes: and sequentially forming N-2 layers of isolation side walls, and etching the substrate after each isolation side wall is formed so as to enable the surface of the substrate to sequentially sink to form a 1 st-stage step to an N-2 nd-stage step, wherein the N-2 layers of isolation side walls are respectively positioned on the table tops of the 1 st-stage step to the N-2 nd-stage step. And, the method for forming the step of the (N-1) th level may be: and etching the (N-2) th step by taking the (N-2) th isolation side wall as a mask to enable part of the substrate to sink so as to form the (N-1) th step. And the nth step may be formed by etching the nth-1 step in the process of preparing the contact plug.

Specifically, referring to fig. 5h, the dielectric layer 700 and the isolation material layer are sequentially etched to the substrate 100 to expose the nth-1 step of the substrate, and a portion of the mesa of the nth-1 step is further etched to sink the mesa to form a contact window 500a, where the bottom surface of the contact window 500a is lower than the mesa of the nth-1 step and forms the nth step of the step portion, that is, the mesa of the nth step is lower than the mesa of the nth-1 step.

In this embodiment, the bottom surface of the contact window 500a corresponds to the fourth step 110d, and the contact window 500a exposes the second doped region 320.

As described above, the material of the dielectric layer 700 is different from the material of the fourth isolation sidewall 640, so that when the dielectric layer 700 is etched to form the contact window 500a, the fourth isolation sidewall 640 can be used to realize the lateral etching stop, thereby effectively controlling the position of the formed contact window 500 a. Based on this, for example, a portion of the fourth isolation sidewall 640 is exposed on the sidewall of the formed contact window 500 a.

In an optional scheme, the number of layers of the isolation side walls on the third step 110c may be adjusted to further adjust the position of the outermost isolation side wall, so that the position of the formed contact window 500a can be correspondingly adjusted. In this embodiment, the contact window 500a is located at the center or near the center of the second doped region 320.

In step S300, referring to fig. 5i specifically, a metal silicide layer 400 is formed on the surface of the source/drain region 300 at the lowest step, and the metal silicide layer 400 further extends into the source/drain region 300. In this embodiment, the metal silicide layer 400 is formed on the surface of the second doped region 320, and the boundary of the metal silicide layer 400 in the second doped region 320, which extends laterally toward the gate structure, does not exceed the boundary of the third isolation sidewall 630, which is close to the gate structure. That is, in the present embodiment, the boundary of the metal silicide layer 400 facing the gate structure does not exceed the boundary of the third step 110c close to the gate structure.

Specifically, the forming method of the metal silicide layer 400 includes, for example: firstly, forming a metal layer covering at least the bottom surface of the contact window 500a to cover the second doped region 320 exposed in the contact window 500 a; then, an annealing process is performed to react the metal in the metal layer and the silicon in the second doped region 320 to form a metal silicide layer 400; then, the unreacted metal layer is removed. The material of the metal silicide layer 400 includes, for example, cobalt silicide.

It should be noted that, in the process of preparing the metal silicide layer 400, since the surface of the second doped region 320 exposed in the contact window is sunken relative to the gate structure 200, a larger distance is provided between the surface of the second doped region 320 and the gate structure 200, and thus the problem of metal diffusion to the gate structure can be effectively solved.

In step S400, referring to fig. 5j in particular, a contact plug 500 is formed at a side of the gate structure 200, and a bottom of the contact plug 500 extends to the metal silicide layer 400. Specifically, the contact plug 500 is correspondingly filled in the contact window 500 a.

In summary, in the semiconductor structure as described above, by making the substrate at the side of the gate structure step-shaped to have a step, the top surface of the source/drain region is correspondingly adjusted to be step-shaped, so that the metal silicide layer can be formed on the mesa of the source/drain region located at the lowest step, and correspondingly the metal silicide layer is recessed in a deeper position of the substrate and located obliquely below the gate structure, which corresponds to increasing the distance between the metal silicide layer and the gate structure. Therefore, when metal diffusion exists, the metal particles are difficult to stride the N-level steps and are difficult to diffuse to the gate structure, so that the problem that the metal diffuses to the gate structure in the preparation process of the metal silicide layer and after the preparation of the metal silicide layer is finished is effectively solved.

It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.

It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.

It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.