阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 西口俊史 于 2019-08-08 设计创作，主要内容包括：实施方式的半导体装置具备：半导体部；第1电极,设置在上述半导体部的背面上；第2电极,设置在上述半导体部的正面侧；第3电极,设置在上述半导体部的正面侧；以及控制电极,配置在设于上述半导体部的正面侧的沟槽的内部,与上述第3电极电连接。上述控制电极配置在上述半导体部与上述第2电极之间,与上述半导体部及上述第2电极电绝缘。上述控制电极包括在沿着上述半导体部的上述正面的第1方向上延伸的第1部分、和在与上述第1方向交叉的第2方向上延伸的第2部分,在上述沟槽内不分岔而连续地延伸。(The semiconductor device of the embodiment includes: a semiconductor section; a 1 st electrode provided on a rear surface of the semiconductor section; a 2 nd electrode provided on the front surface side of the semiconductor section; a 3 rd electrode provided on the front surface side of the semiconductor section; and a control electrode disposed inside a trench provided on the front surface side of the semiconductor section and electrically connected to the 3 rd electrode. The control electrode is disposed between the semiconductor section and the 2 nd electrode, and is electrically insulated from the semiconductor section and the 2 nd electrode. The control electrode includes a 1 st portion extending in a 1 st direction along the front surface of the semiconductor portion and a 2 nd portion extending in a 2 nd direction intersecting the 1 st direction, and extends continuously in the trench without branching.)

1. A semiconductor device is characterized in that a semiconductor element,

the disclosed device is provided with:

a semiconductor section including a 1 st semiconductor layer of a 1 st conductivity type;

a 1 st electrode provided on a rear surface of the semiconductor section;

a 2 nd electrode provided on the front surface side of the semiconductor section;

a 3 rd electrode provided on the front surface side of the semiconductor section and electrically insulated from the semiconductor section and the 2 nd electrode; and

a control electrode disposed between the semiconductor section and the 2 nd electrode inside a trench provided on a front surface side of the semiconductor section and electrically connected to the 3 rd electrode;

the control electrode is electrically insulated from the semiconductor section via a 1 st insulating film and is electrically insulated from the 2 nd electrode via a 2 nd insulating film;

the semiconductor section further includes a 2 nd semiconductor layer of a 2 nd conductivity type and a 3 rd semiconductor layer of a 1 st conductivity type;

the 2 nd semiconductor layer is provided between the 1 st semiconductor layer and the 2 nd electrode, and faces the control electrode with the 1 st insulating film interposed therebetween;

the 3 rd semiconductor layer is selectively provided between the 2 nd semiconductor layer and the 2 nd electrode, and is electrically connected to the 2 nd electrode;

the control electrode includes a 1 st portion and a 2 nd portion extending continuously in the trench without branching and in a direction parallel to the front surface of the semiconductor portion, the 1 st portion extending in a 1 st direction, and the 2 nd portion extending in a 2 nd direction intersecting the 1 st direction.

2. The semiconductor device according to claim 1,

a plurality of control electrodes are arranged;

the 1 st portions of the plurality of control electrodes are arranged in a 3 rd direction parallel to the front surface of the semiconductor section and orthogonal to the 1 st direction, and the 2 nd portions of the plurality of control electrodes are arranged in a 4 th direction parallel to the front surface of the semiconductor section and orthogonal to the 2 nd direction.

3. The semiconductor device according to claim 2,

further provided with:

a 1 st control wiring extending in the 3 rd direction and electrically connected to the 3 rd electrode and a 1 st portion of the plurality of control electrodes; and

and a 2 nd control wiring extending in the 4 th direction and electrically connected to the 3 rd electrode and the 2 nd portion of the plurality of control electrodes.

4. The semiconductor device according to claim 3,

the 3 rd electrode is disposed at the center of the front surface of the semiconductor section.

5. The semiconductor device according to claim 3,

a 3 rd control wiring including a portion located above a connection portion between the 1 st portion of one control electrode and the 2 nd portion of the one control electrode among the plurality of control electrodes, the 3 rd control wiring extending along the front surface of the semiconductor section;

the 3 rd control wiring is electrically connected to the control electrode at the connection portion.

6. The semiconductor device according to claim 1,

a plurality of the control electrodes are provided in the 1 st part and the 2 nd part, respectively;

the plurality of 1 st portions and the plurality of 2 nd portions are integrally connected.

7. The semiconductor device according to claim 6,

the control electrode has a spiral shape extending parallel to the front surface of the semiconductor section.

8. The semiconductor device according to claim 6,

a plurality of control electrodes are arranged;

the plurality of control electrodes include a 1 st control electrode and a 2 nd control electrode arranged in a direction parallel to the front surface of the semiconductor section.

9. The semiconductor device according to claim 8,

the 1 st control electrode and the 2 nd control electrode each have a spiral shape extending parallel to the front surface of the semiconductor section.

10. The semiconductor device according to claim 9,

the 3 rd electrode is disposed on a central portion of the front surface of the semiconductor section.

11. The semiconductor device according to claim 9,

the 3 rd electrode is disposed on an outer edge portion of the front surface of the semiconductor section;

the 1 st control electrode and the 2 nd control electrode have a shape that is line-symmetrical with respect to the 3 rd electrode.

12. The semiconductor device according to claim 6,

the front surface of the semiconductor portion includes a 1 st region and a 2 nd region adjacent to the 1 st region;

said control electrode further comprising a plurality of No. 3 portions extending in said No. 2 direction and a plurality of No. 4 portions extending in said No. 1 direction;

the plurality of 1 st portions are arranged in the 1 st region and extend continuously through the plurality of 3 rd portions;

the plurality of 2 nd portions are arranged in the 2 nd region and extend continuously through the plurality of 4 th portions.

13. The semiconductor device according to any one of claims 1 to 12,

a field plate provided inside the trench and located between the control electrode and the 1 st semiconductor layer in a 5 th direction orthogonal to the front surface of the semiconductor section;

the field plate extends along the control electrode and is electrically connected to the 2 nd electrode.

Technical Field

The present invention relates to a semiconductor device.

Background

The power control semiconductor device is desired to have a low starting resistance in order to reduce power loss. For example, in a trench gate MOSFET, the density of trench gates in an active region where a start current flows is increased, thereby reducing the start resistance. However, in the manufacturing process, the wafer may be warped due to a difference in thermal expansion coefficient between the semiconductor and the polysilicon, the gate insulating film, the field plate insulating film, or the like provided in the trench gate, and the manufacturing efficiency may be lowered.

Disclosure of Invention

The invention provides a semiconductor device capable of reducing the warpage of a wafer in a manufacturing process.

A semiconductor device according to the present invention includes: a semiconductor section including a 1 st semiconductor layer of a 1 st conductivity type; a 1 st electrode provided on a rear surface of the semiconductor section; a 2 nd electrode provided on the front surface side of the semiconductor section; a 3 rd electrode provided on the front surface side of the semiconductor section and electrically insulated from the semiconductor section and the 2 nd electrode; and a control electrode disposed between the semiconductor section and the 2 nd electrode, inside a trench provided on a front surface side of the semiconductor section, and electrically connected to the 3 rd electrode. The control electrode is electrically insulated from the semiconductor section via a 1 st insulating film, and is electrically insulated from the 2 nd electrode via a 2 nd insulating film. The semiconductor section further includes a 2 nd semiconductor layer of a 2 nd conductivity type and a 3 rd semiconductor layer of a 1 st conductivity type; the 2 nd semiconductor layer is provided between the 1 st semiconductor layer and the 2 nd electrode, and faces the control electrode with the 1 st insulating film interposed therebetween. The 3 rd semiconductor layer is selectively provided between the 2 nd semiconductor layer and the 2 nd electrode, and is electrically connected to the 2 nd electrode. The control electrode includes a 1 st portion and a 2 nd portion extending continuously in the trench without branching and in a direction parallel to the front surface of the semiconductor portion, the 1 st portion extending in a 1 st direction, and the 2 nd portion extending in a 2 nd direction intersecting the 1 st direction.

Drawings

Fig. 1A and 1B are schematic views showing a semiconductor device according to an embodiment.

Fig. 2A and 2B are schematic views showing a semiconductor device according to a modification of the embodiment.

Fig. 3A and 3B are schematic views showing a semiconductor device according to another modification of the embodiment.

Fig. 4A and 4B are schematic views showing a semiconductor device according to still another modification of the embodiment.

Fig. 5A and 5B are schematic views showing a semiconductor device according to another modification of the embodiment.

Fig. 6A to 6C are schematic views showing a method of mounting a semiconductor device according to an embodiment.

Fig. 7A and 7B are schematic views showing a semiconductor device according to a comparative example.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals are given to the same portions in the drawings, and detailed description thereof will be omitted as appropriate, and different portions will be described. The drawings are schematic or conceptual, and the relationship between the thickness and the width of each portion, the ratio of the sizes of the portions, and the like are not necessarily the same as those in reality. Even when the same portions are indicated, the sizes and ratios of the portions may be indicated differently according to the drawings.

The arrangement and structure of each part will be described using the X, Y, and Z axes shown in the drawings. The X, Y and Z axes are orthogonal to each other and respectively represent the X, Y and Z directions. The Z direction may be described as an upper direction and the opposite direction may be described as a lower direction.

Fig. 1A and 1B are schematic views showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is, for example, a power MOSFET having a trench gate structure. The Semiconductor device 1 has, for example, a MOS (Metal Oxide Semiconductor) structure provided on the front surface side of the Semiconductor section 10. The semiconductor section 10 is, for example, silicon. Fig. 1A is a schematic plan view showing the arrangement of the gate electrode 20 and the gate pad 30 of the semiconductor device 1. Fig. 1B is a schematic view showing a cross section along the line a-a shown in fig. 1A.

As shown in fig. 1A, the gate electrode 20 includes, for example, a 1 st portion 20a and a 2 nd portion 20 b. The 1 st portion 20a extends in the 1 st direction (e.g., X direction) along the front surface of the semiconductor section 10. The 2 nd portion 20b is connected to the 1 st portion 20a, and extends in the 2 nd direction (for example, Y direction) along the front surface of the semiconductor section 10. The 1 st direction intersects the 2 nd direction within the front surface of the semiconductor section 10, for example.

The gate pads 30 are arranged at 1 of 4 corners along the outer edge of the front surface of the semiconductor section 10, for example. A gate pad 30 and a gate wiring 30 extending in the X-direction and the Y-direction along the outer edge of the front surface of the semiconductor section 10_PXAnd 30_PYAnd (4) connecting. Gate line 30_PYElectrically connected to the 1 st portion 20a of the gate electrode 20. Gate line 30_PXIs electrically connected to the 2 nd portion 20b of the gate electrode 20.

For example, a plurality of gate electrodes 20 are arranged. The 1 st portions 20a of the gate electrodes 20 are arranged in the Y direction and connected to the gate lines 30_PYAnd (6) electrically connecting. In addition, the 2 nd portions 20b of the plurality of gate electrodes 20 are arranged in the X direction and the gate lines 30_PXAnd (6) electrically connecting.

As shown in fig. 1B, the semiconductor device 1 further includes a drain electrode 40 (1 st electrode) and a source electrode 50 (2 nd electrode). The drain electrode 40 is provided on the back surface of the semiconductor section 10. The source electrode 50 is provided on the front surface side of the semiconductor section 10.

The semiconductor section 10 includes, for example, an n-type drift layer 11 (1 st semiconductor layer), an n-type drain layer 13, a p-type diffusion layer 15 (2 nd semiconductor layer), an n-type source layer 17 (3 rd semiconductor layer), and a p-type contact layer 19.

The n-type drain layer 13 is disposed between the n-type drift layer 11 and the drain electrode 40. The n-type drain layer 13 contains an n-type impurity at a higher concentration than the n-type impurity of the n-type drift layer 11. The drain electrode 40 is in contact with and electrically connected to the n-type drain layer 13.

The p-type diffusion layer 15 is disposed between the n-type drift layer 11 and the source electrode 50. The n-type source layer 17 is selectively provided between the p-type diffusion layer 15 and the source electrode 50. n-type source layer 17 contains n-type impurities at a higher concentration than n-type impurities in n-type drift layer 11, and is electrically connected to source electrode 50.

The p-type contact layer 19 is, for exampleIs disposed in the p-type diffusion layer 15. The p-type contact layer 19 contains a p-type impurity at a higher concentration than the p-type impurity of the p-type diffusion layer 15. The source electrode 50 extends to the contact portion 50 of the semiconductor portion 10 through the interlayer insulating film 33_CPElectrically connected to the p-type contact layer 19.

Contact part 50_CPExtends inside the contact trench CT having a depth reaching the p-type contact layer 19 from the front surface of the interlayer insulating film 33, and contacts the p-type contact layer 19. Further, the contact portion 50_CPAnd is electrically connected in contact with the n-type source layer 17 exposed on the inner wall of the contact trench CT.

As shown in fig. 1B, the gate electrode 20 is disposed inside a gate trench GT provided on the front surface side of the semiconductor section 10. Inside the gate trench GT, a field plate 25 electrically insulated from the gate electrode 20 is further disposed. The gate electrode 20 and the field plate 25 are electrically insulated from the semiconductor section 10 by an insulating film 27. Further, the gate electrode 20 is electrically insulated from the source electrode 50 by the interlayer insulating film 33. The insulating film 27 and the interlayer insulating film 33 are, for example, silicon oxide films.

The gate electrode 20 is disposed in the gate trench GT so as to face the p-type diffusion layer 15 with a part 27g of the insulating film 27 interposed therebetween. A part 27g of the insulating film 27 functions as a gate insulating film. The field plate 25 is located between the n-type drift layer 11 and the gate electrode 20 in the Z direction, for example. The field plate 25 extends inside the gate trench GT together with the gate electrode 20. The field plate 25 is electrically connected to the source electrode 50 at a portion not shown, for example.

As shown in fig. 1A, the gate electrode 20 according to the embodiment includes a 1 st portion 20a and a 2 nd portion 20b, and extends continuously inside the gate trench GT. For example, stress generated inside the wafer due to a difference between the linear thermal expansion coefficient of the semiconductor section 10 and the linear thermal expansion coefficient of the insulating film 27 provided inside the gate trench GT is relaxed by providing the 1 st portion 20a and the 2 nd portion 20 b. This can suppress the warpage of the wafer during the manufacturing process of the semiconductor device 1.

For example, in a structure including only either the 1 st portion 20a or the 2 nd portion 20b, the warpage of the wafer in the direction orthogonal to the gate electrode 20 becomes large. In contrast, if both of the 1 st portion 20a and the 2 nd portion 20b are provided, the area of the region where the respective portions are provided becomes small, and the stress is reduced. In the example shown in fig. 5B, the amount of warpage of the wafer can also be controlled by changing the ratio of the area of the region where the 1 st portion 20a is arranged to the area of the region where the 2 nd portion 20B is arranged.

With the trench gate structure in which the field plate 25 is arranged in the interior of the gate trench GT, the gate trench GT is provided deeper in the Z direction. Therefore, the volume of the insulating film 27 provided in the inside of the gate trench GT increases, and the deformation of the wafer during the manufacturing process becomes large. As a result, the warpage of the wafer becomes large. That is, according to the present embodiment, the gate electrode 20 effectively suppresses the warpage of the wafer in the manufacturing process of the semiconductor device 1 in which the gate trench GT is formed deep.

In addition, the semiconductor device 1 according to the present embodiment can reduce the starting resistance. For example, the semiconductor device 8 shown in fig. 7A includes a plurality of 1 st portions 20a and a plurality of 2 nd portions 20b provided in the semiconductor section 10. This can suppress the warpage of the wafer during the manufacturing process of the semiconductor device 8. However, the semiconductor device 8 is configured such that the 1 st portion 20a and the 2 nd portion 20b are separated and disposed in different regions. That is, a 1 st region GR1 including a plurality of 1 st sections 20a and a 2 nd region GR2 including a plurality of 2 nd sections 20b are provided. Therefore, a portion that does not contribute to the starting current is generated between the 1 st region GR1 and the 2 nd region GR 2.

In contrast, in the semiconductor device 1 according to the embodiment, the area contributing to the starting current can be increased by disposing the 1 st portion 20a and the 2 nd portion 20b of the gate electrode 20 so as to be connected to each other. That is, the semiconductor device 1 can reduce the starting resistance as compared with the semiconductor device 8.

In addition, with the semiconductor device 9 shown in fig. 7B, the plurality of 1 st portions 20a and the plurality of 2 nd portions 20B are arranged in a lattice shape intersecting each other. This can suppress the warpage of the wafer during the manufacturing process of the semiconductor device 9. However, in the semiconductor device 9, if the gate trench GT is made finer, the area of the semiconductor portion 10 located between the 1 st portions 20a and the 2 nd portions 20b is reduced, and the flow path between the gate electrodes 20 through which the current flows in the n-type drift layer 11 is narrowed. Therefore, even if the channel resistance is reduced by miniaturizing the gate electrode 20, the total on-resistance may not be sufficiently reduced. Further, it is difficult to form a contact structure for electrically connecting the p-type diffusion layer 15 and the source electrode 50.

In contrast, in the semiconductor device 1 according to the embodiment, the gate electrode 20 extends without branching inside the gate trench GT. This can alleviate the reduction in the area of the semiconductor portion 10 between the 1 st portions 20a and between the 2 nd portions 20b, which is caused by the miniaturization of the gate trench GT. That is, an increase in the on-resistance of n-type drift layer 11 can be suppressed. In addition, contact trenches CT are easily formed between the 1 st portions 20a and the 2 nd portions 20b, and a contact structure of the source electrode 50 with respect to the p-type diffusion layer 15 is easily formed.

Fig. 2A and 2B are schematic views showing a semiconductor device 2 according to a modification of the embodiment. FIG. 2A shows the gate electrode 20, the gate pad 30, and the gate line 30_PX、30_PYAnd 30_SSchematic top view of the arrangement of (a). Fig. 2B is a schematic sectional view along the CE direction shown in fig. 2A.

As shown in fig. 2A, the semiconductor device 2 is provided with a gate wiring 30 located above the connection portion of the 1 st portion 20a and the 2 nd portion 20b of the gate electrode 20_S. Gate line 30_SExtending from the gate pad 30 in the CE direction and located above the connection portion of the plurality of gate electrodes 20.

FIG. 2B is the contact portion 30 shown in FIG. 2A_CPCross-sectional view of (a). Gate line 30_SIs disposed above the semiconductor section 10. Gate line 30_SThe semiconductor section 10 is electrically insulated from the interlayer insulating film 33. And, the gate wiring 30_SVia the gate contact 30_GCIs electrically connected to the gate electrode 20. Gate contact 30_GCA gate wiring 30 in the interlayer insulating film 33_STo a depth reaching the gate electrode 20.

Gate contact 30_GCIs provided to reduce the parasitic resistance of the gate electrode 20. For example, at least 1 gate electrode 20, and a gate wiring 30_PXAnd a gate wiring30_PYThe gate contact 30 is provided when the parasitic resistance between the connection portions is larger than a predetermined value_GC. This can increase the response speed of the semiconductor device 2 to the gate bias.

Fig. 3A and 3B are schematic views showing a semiconductor device 3 according to a modification of the embodiment. FIG. 3A shows the gate electrode 20, the gate pad 30, and the gate line 30_PXAnd 30_PYSchematic top view of the arrangement of (a). FIG. 3B shows the gate pad 30 and the gate line 30_PX、30_PYAnd a schematic top view of the arrangement of the source electrode 50.

As shown in fig. 3A, the gate pad 30 is disposed in the center of the active region with respect to the semiconductor device 3. Gate line 30_PXExtending from the gate pad 30 in the + X direction and the-X direction. Gate line 30_PXElectrically connected to the gate pad 30. Gate line 30_PYExtending from the gate pad 30 in the + Y direction and the-Y direction. Gate line 30_PYElectrically connected to the gate pad 30.

The semiconductor device 3 has a plurality of gate electrodes 20. The gate electrode 20 includes a 1 st portion 20a and a 2 nd portion 20b, respectively. 1 st portion 20a and gate line 30_PYAnd an electrical connection extending in the X direction. 2 nd portion 20b and gate line 30_PXConnected, extending in the Y direction. The 1 st portions 20a and the 2 nd portions 20b of the plurality of gate electrodes 20 are arranged in the Y direction and the X direction, respectively.

For example, if the gate electrodes 20 arranged at the same position on the front surface of the semiconductor section 10 are compared, the slave and gate wirings 30 are connected_PXTo the gate wiring 30_PYThe length of the connection portion of (2), the length of the gate electrode 20 of the semiconductor device 3 being shorter than the length of the gate electrode 20 of the semiconductor device 1. That is, the semiconductor device 3 can reduce the parasitic resistance of the gate electrode 20 and increase the response speed to the gate bias.

As shown in fig. 3B, the source electrode 50 is not connected to the gate pad 30 and the gate line 30_PXAnd 30_PYThe overlapping mode is configured by dividing into 4 parts. The source electrode 50 is disposed on the front surface of the semiconductor section 10 so as to be separated therefrom, and is disposed in contact with the gate pad 30 and the gateWire 30_PXAnd 30_PYIs electrically insulated. The embodiment is not limited to this example, and for example, the source electrode 50 may be positioned on the gate line 30 with an interlayer insulating film interposed therebetween_PXAnd 30_PYAbove.

Fig. 4A to 5B are schematic views showing semiconductor devices 4 to 7 according to modified examples of the embodiment. Fig. 4A to 5B are schematic views showing the arrangement of the gate electrode 20 and the gate pad 30.

With the semiconductor device 4 shown in fig. 4A, the gate electrode 20 has a planar shape in which a plurality of 1 st portions 20a and a plurality of 2 nd portions 20b are integrally connected. The gate electrode 20 is formed in a spiral shape, for example, by the plurality of 1 st portions 20a and the plurality of 2 nd portions 20 b. The plurality of 1 st portions 20a are arranged in the Y direction, and the plurality of 2 nd portions 20b are arranged in the X direction. The gate pads 30 are arranged at 1 of 4 corners located on the outer edge of the front surface of the semiconductor section 10, and the gate electrodes 20 are electrically connected to the gate pads 30.

In the semiconductor device 5 shown in fig. 4B, the gate pad 30 is disposed in the center of the front surface of the semiconductor section 10, and 2 gate electrodes 20 are disposed on both sides of the gate pad 30. Each of the 2 gate electrodes 20 has a structure in which a plurality of 1 st portions 20a and a plurality of 2 nd portions 20b are integrally arranged in a spiral shape. The plurality of 1 st portions 20a are arranged in the Y direction, and the plurality of 2 nd portions 20b are arranged in the X direction. The gate electrode 20 is electrically connected to the gate pad 30 at the center of the semiconductor section 10. The 2 gate electrodes 20 may be symmetrically arranged with respect to the gate pad 30.

The semiconductor device 6 shown in fig. 5A has a structure in which 2 gate electrodes 20 are arranged in the Y direction. Each of the 2 gate electrodes 20 has a structure in which a plurality of 1 st portions 20a and a plurality of 2 nd portions 20b are integrally arranged in a spiral shape. The gate pad 30 is disposed on the outer edge of the front surface of the semiconductor section 10. The 2 gate electrodes 20 are electrically connected to the gate pad 30 at the outer edge of the semiconductor section 10. Further, the 2 gate electrodes 20 are arranged line-symmetrically with respect to the gate pad 30.

With the semiconductor device 7 shown in fig. 5B, the gate electrode 20 includes a plurality of 1 st portions 20a, a plurality of 2 nd portions 20B, a plurality of 3 rd portions 20c, and a plurality of 4 th portions 20 d. The gate electrode 20 has a structure in which a plurality of 1 st portions 20a and a plurality of 2 nd portions 20b are integrally connected to each other through a 3 rd portion 20c and a 4 th portion 20 d. The 3 rd portion 20c extends, for example, in a direction (e.g., Y direction) intersecting the 1 st portion 20 a. The 4 th portion 20d extends, for example, in a direction (for example, X direction) intersecting with the 2 nd portion 20 b. The gate electrode 20 is electrically connected to a gate pad 30 disposed at one of 4 corners along the outer edge of the front surface of the semiconductor section 10.

The 1 st portions 20a are arranged in the 1 st region GR1 and are connected to each other via the 3 rd portions 20 c. The plurality of 2 nd portions 20b are disposed in the 2 nd region GR2 and are connected to each other via the 4 th portion 20 d. The 1 st region GR1 and the 2 nd region GR2 are arranged in the Y direction on the front surface of the semiconductor section 10. The plurality of 1 st portions 20a are arranged in the Y direction, and the plurality of 2 nd portions are arranged in the X direction. The plurality of 3 rd portions 20c and the plurality of 4 th portions 20d also contribute to the reduction of warpage of the wafer.

The semiconductor devices 4 to 7 include the plurality of 1 st portions 20a and the plurality of 2 nd portions 20b, and thus warpage of a wafer during a manufacturing process thereof can be effectively suppressed. Further, by integrally connecting the plurality of 1 st portions 20a and the plurality of 2 nd portions 20b, the surface area of the semiconductor section 10 can be effectively used to reduce the starting current. In addition, the gate lines 30 can be provided appropriately for the semiconductor devices 4 to 7_SAnd a contact portion 30_CPTo reduce the parasitic resistance of the gate electrode 20.

Fig. 6A to 6C are schematic diagrams illustrating a method of mounting the semiconductor device 3 or the semiconductor device 5 (see fig. 4B) according to the embodiment. In the semiconductor device 3 and the semiconductor device 5, the gate pad 30 is disposed at the center of the front surface of the semiconductor section 10.

Fig. 6A is a schematic plan view showing the arrangement of the connection portions 60 and 70 arranged above the semiconductor section 10 of the semiconductor device 3. Fig. 6B is a schematic view showing a cross section along the line B-B shown in fig. 6A. Fig. 6C is a schematic view showing a cross section along the line C-C shown in fig. 6A. In fig. 6A, the source electrode 50 is omitted, and in fig. 6B and 6C, the semiconductor layer of the semiconductor section 10, the gate electrode 20, and the drain electrode 40 are omitted.

As shown in fig. 6A, for example, 2 connection portions 60 and 70 are arranged above the semiconductor section 10. The connection 60 is connected to ground potential, for example. The connection portion 70 is connected to a supply circuit for gate bias, for example.

As shown in fig. 6B, the connection portion 60 is connected to the source electrode 50. The drain electrode 40 (see fig. 1B) is connected to, for example, a drain bias supply circuit. Thereby, a predetermined voltage is supplied between the drain and the source.

As shown in fig. 6C, the connection portion 70 is connected to the gate pad 30 across the source electrode 50, for example. The connection portion 70 is disposed away upward from the source electrode 50. In this example, the connection portion 70 is connected to the gate pad 30 located at the center of the semiconductor section 10, and therefore the connection portions 60 are disposed on both sides thereof.

Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments may be implemented in other various forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.