阅读说明：本技术 冷焊接倒装芯片互连结构 (Cold-welded flip chip interconnection structure ) 是由 E·P·莱文多沃斯基 罗载雄 N·T·布龙 于 2020-01-20 设计创作，主要内容包括：一种量子装置包括形成在衬底(302,302A)上的第一组突出部(304)以及形成在量子位芯片(310)上的第二组突出部。量子装置还包括形成在中介件(306)上的一组凸块(308),该组凸块由在室温范围具有高于阈值延展性的材料形成,其中,该组凸块中的第一子组被配置为冷焊接至第一组突出部,并且该组凸块中的第二子组被配置为冷焊接至第二组突出部。(A quantum device includes a first set of projections (304) formed on a substrate (302, 302A) and a second set of projections formed on a qubit chip (310). The quantum device also includes a set of bumps (308) formed on the interposer (306), the set of bumps being formed of a material having a ductility above a threshold value in a room temperature range, wherein a first subset of the set of bumps is configured to be cold-welded to the first set of protrusions and a second subset of the set of bumps is configured to be cold-welded to the second set of protrusions.)

1. A quantum device, comprising:

a first set of protrusions formed on the substrate;

a second set of projections formed on the qubit chip; and

a set of bumps formed on the interposer, the set of bumps being formed of a material having a ductility above a threshold value over a room temperature range, wherein a first subset of the set of bumps is configured to be cold welded to the first set of protrusions and a second subset of the set of bumps is configured to be cold welded to the second set of protrusions.

2. The quantum device of claim 1, wherein the first set of protrusions has at least one member selected from the group consisting of gold and platinum.

3. The quantum device of claim 1, wherein the second set of protrusions has at least one member selected from the group consisting of gold and platinum.

4. The quantum device of claim 1, wherein the set of bumps has at least one member selected from the group consisting of indium, tin, lead, and bismuth.

5. The quantum device of claim 1, wherein the first set of protrusions have a conical shape.

6. The quantum device of claim 1, wherein the second set of protrusions have a pyramidal shape.

7. The quantum device of claim 1, wherein the set of bumps comprises a material that exhibits superconductivity in a cryogenic temperature range.

8. The quantum device of claim 1, wherein a plurality of the first set of tabs are configured to be cold welded to one of the set of tabs.

9. The quantum device of claim 1, wherein the first set of projections comprises a superconducting material coated with gold.

10. The quantum device of claim 1, wherein the second set of projections comprises a superconducting material coated with gold.

11. A method, comprising:

forming a first set of protrusions on a substrate;

forming a second set of projections on the qubit chip;

forming a set of bumps formed on the interposer, the set of bumps formed of a material having ductility above a threshold value in a room temperature range; and is

Cold welding a subset of the set of bumps to the first set of protrusions and cold welding a second subset of the set of bumps to the second set of protrusions.

12. The method of claim 9, wherein the first set of projections has at least one member selected from the group consisting of gold and platinum.

13. The method of claim 9, wherein the second set of projections has at least one member selected from the group consisting of gold and platinum.

14. The method of claim 9, wherein the set of bumps has at least one member selected from the group consisting of indium, tin, lead, and bismuth.

15. The method of claim 9, wherein the first set of projections have a conical shape.

16. The method of claim 9, wherein the second set of protrusions have a pyramidal shape.

17. The method of claim 9, wherein the set of bumps comprises a material that exhibits superconductivity in a cryogenic temperature range.

18. The method of claim 9, wherein a plurality of the first set of tabs are configured to be cold welded to one of the set of tabs.

19. The method of claim 9, wherein the first set of projections comprises a superconducting material coated with gold.

20. A circuit manufacturing system that performs operations of the method of any of claims 11 to 19.

Technical Field

The present invention generally relates to quantum computing devices.

Background

In the following, unless expressly distinguished when used, the "Q" prefix in a word or phrase indicates a reference to the word or phrase in a quantum computing context.

Molecular and subatomic particles follow the laws of quantum mechanics, a branch of physics exploring how the physical world works at the most fundamental level. At this level, the particles behave in a strange way, taking on more than one state at the same time, and interacting with other particles very far away. Quantum computing exploits these quantum phenomena to process information.

Computers we use today are called classic computers (also referred to herein as "conventional" computers or conventional nodes, or "CNs"). In the so-called Von Neumann architecture, conventional computers use conventional processors, semiconductor memories, and magnetic or solid-state storage devices fabricated with semiconductor materials and technologies. In particular, the processor in a conventional computer is a binary processor, i.e., operates on binary data represented by a string of characters including 1 and 0.

Quantum processors (q-processors) use the odd-numbered nature of an entangled qubit device (referred to herein compactly as a "qubit," a plurality of "qubits") to perform computational tasks. In the particular field of quantum mechanical operation, particles of a substance may exist in multiple states, such as an "on" state, an "off" state, or both an "on" and an "off" state. In the case where binary calculations using a semiconductor processor are limited to using only on and off states (equivalent to 1 and 0 in binary code), the quantum processor utilizes these quantum states of matter to output signals usable in data calculations.

Conventional computers encode information in bits. Each bit may take a value of 1 or 0. These 1's and 0's are physically implemented by an on/off switch that ultimately drives the computer function. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: stacking and entanglement. Overlapping means that each qubit can represent both a 1 and a 0 simultaneously. Entanglement means that qubits in a superposition can be related to each other in a non-classical way; that is, the state of one qubit (whether it is a 1 or a 0 or both) may depend on the state of the other qubit, and there is more information that can be confirmed about the two qubits when they are entangled than when they are processed separately.

Using both principles, qubits operate as more complex information processors, enabling quantum computers to function in a manner that allows them to solve difficult problems that are difficult to process using conventional computers. IBM has successfully constructed and demonstrated the operability of quantum processors using superconducting qubits (IBM is a registered trademark of International Business machines corporation in the United states and other countries.)

The superconducting qubit includes a josephson junction. Josephson junctions are formed by separating two thin film superconducting metal layers by a non-superconducting material (or by geometric contraction of the superconducting material). When the metal in the superconducting layers is made superconducting, for example by lowering the temperature of the metal to a certain cryogenic temperature, electron pairs can tunnel from one superconducting layer through the non-superconducting layer to the other. In a qubit, a josephson junction (which functions as a non-dissipative nonlinear inductor) is electrically coupled in parallel with one or more capacitive devices, forming a nonlinear microwave oscillator. The oscillator has a resonance/transition frequency determined by the values of the inductance and capacitance in the qubit circuit. Any reference to the term "qubit" is a reference to superconducting qubit circuits employing josephson junctions, unless explicitly distinguished when used.

In the superconducting state, the material first provides no resistance to the passage of current. When the resistance drops to zero, the current can circulate inside the material without any energy dissipation. Secondly, materials exhibit the meissner effect, i.e. as long as they are sufficiently weak, the external magnetic field does not penetrate the superconductor, but remains on its surface. When a material no longer exhibits one or both of these properties, the material is said to be no longer superconducting.

The critical temperature of a superconducting material is the temperature at which the material begins to exhibit superconducting properties. Superconducting materials exhibit very low or zero resistivity to the flow of current. The critical field is the highest magnetic field at which the material remains superconducting for a given temperature.

Superconductors are generally classified into one of two types. Type I superconductors exhibit a single transition at the critical field. When the critical field is reached, the type I superconductor transitions from a non-superconducting state to a superconducting state. A type II superconductor includes two critical fields and two transitions. At or below the lower critical field, the type II superconductor exhibits a superconducting state. Above the upper critical field, type II superconductors do not exhibit superconducting properties. Between the upper and lower critical fields, the type II superconductor exhibits a mixed state. In the mixed state, type II superconductors exhibit an incomplete meissner effect, i.e. the external magnetic field in the quantization packet at a specific location penetrates the superconductor material.

The meissner effect is due to the generation of a persistent current at the surface of the superconductor material. The persistent current is a permanent current that does not require an external power source. The persistent current generates opposing magnetic fields to counteract the external magnetic field throughout the bulk of the superconductor material. In the superconducting state, the persistent current does not decay with time due to the zero resistance property.

The information processed by the qubits is carried or transmitted in the form of microwave signals/photons in the microwave frequency range. The microwave signal is captured, processed and analyzed to interpret the quantum information encoded therein. A readout circuit is a circuit coupled with a qubit to capture, read and measure the quantum state of the qubit. The output of the sensing circuit is information that can be used by the q-processor to perform calculations.

Superconducting qubits have two computational states, - |0> and |1 >. The two states may be two energy states of an atom, such as the ground state (| g >) and the first excited state (| e >) of a superconducting artificial atom (a superconducting qubit). Other examples include spin-up and spin-down of the nuclear or electron spins, two locations of crystal defects, and two states of quantum dots. Because the system is of quantum nature, any (normalized) linear combination of these two computational states is allowed and is efficient.

In order for quantum computation using qubits to be reliable, the quantum circuits (e.g., the qubits themselves, readout circuits associated with the qubits, and other parts of the quantum processor) must not change the energy state of the qubit (such as by injecting or dissipating energy) or affect the relative phase between the |0> and |1> states of the qubit in any significant way. This operational constraint on any circuit operating with quantum information necessitates special considerations for fabricating semiconductor and superconducting structures used in such circuits.

Currently available quantum circuits are formed using materials that become superconducting at low temperatures (e.g., below 10K). External circuits connected to the quantum circuit typically operate at room temperature (approximately 270-300K) or higher. The connection between the external circuit and the q-circuit (e.g. the input line to the q-circuit or the output line from the q-circuit, or both) must therefore be thermally isolated from the environment of the external circuit.

To provide this thermal isolation, the lines connected to the q-circuit pass through a series of one or more dilution refrigerator stages (referred to herein compactly as "stages," a plurality of "stages"). Dilution refrigerators are heat exchange devices that cause a reduction in the temperature of a component compared to the temperature at which the component is introduced into the dilution refrigerator, maintain the component at a specified reduced temperature, or both. For example, a dilution refrigerator stage may reduce the temperature of the input line to the q-circuit, and another dilution refrigerator stage down the line in a series of dilution refrigerator stages may house the q-circuit.

The signal on the line through the stage may contain noise. Such noise may be in the microwave spectrum. For the reasons described herein, microwave frequency noise is undesirable when the lines and signals involve quantum computation using q-circuits.

Flip-chip assembly is a method of interconnecting an electronic device with external circuitry through metallic solder bumps deposited onto the pads of the electronic device. The pads on the electronic device are aligned with the mating pads on the external circuit.

The present invention recognizes certain disadvantages of currently available methods for quantum device assembly. For example, in currently available methods, solder paste is deposited onto the contact pads, and the entire circuit assembly is then heated to create a molten state of the solder paste. Heating of circuit components may damage the josephson junction and degrade the performance of the circuit. For example, in currently available methods, the metal deposits tend to oxidize, thereby affecting the mechanical and electrical properties of the connection. The de-oxidation of the metal deposit may damage the qubit. For example, the chemicals and methods used to remove the surface oxide may be destructive and even completely destroy the josephson junction. In addition, currently available methods are not effective in producing good electrical connections due to warpage of the substrate during the manufacturing process.

The present invention recognizes that the solder used to form the electrical connection may deform during quantum device assembly and cooling. Plastic deformation is the irreversible change in shape of a material under an applied force. The plastic deformation, known as creep, depends on the time and temperature to which the solder is exposed to stress during assembly. The present invention recognizes that there is a direct relationship between the temperature and the amount of deformation of the solder material. That is, the higher the temperature of the solder material, the more the solder deforms under the applied stress.

The present invention further recognizes that the deformation of solder during quantum device assembly affects the desired electrical connection, solder creep changes the gap height between the pads on the flip chip, solder creep changes the distance between the qubit and the signal on ground and the interposer, and performance degradation occurs due to solder creep between the signal on any substrate (such as a qubit chip, interposer, or organic package), ground, and qubit. The gap height is designed to produce the desired capacitance. The fluctuation in gap height due to solder creep affects the capacitance value and the performance of the electrical connection.

Disclosure of Invention

The embodiment of the invention provides a quantum computing device. The device includes: a first set of protrusions formed on the substrate; a second set of projections formed on the qubit chip; and a set of bumps formed on the interposer, the bumps being formed of a material having a ductility above a threshold value over a room temperature range, wherein a first subset of the set of bumps is configured to be cold welded to the first set of protrusions and a second subset of the set of bumps is configured to be cold welded to the second set of protrusions.

The first set of projections may have at least one member selected from the group consisting of gold and platinum. The second set of protrusions may have at least one member selected from the group consisting of gold and platinum.

The set of bumps may have at least one member selected from the group consisting of indium, tin, lead, and bismuth. The first set of projections may have a conical shape. The second set of projections may have a pyramidal shape.

The set of bumps may include a material that exhibits superconductivity in a cryogenic temperature range. The plurality of projections of the first set of projections may be configured to be cold welded to one of the set of bumps.

In an embodiment of the invention, a method comprises: forming a first set of protrusions on a substrate; forming a second set of projections on the qubit chip; forming a set of bumps formed on the interposer, the set of bumps formed of a material having a ductility above a threshold value in a room temperature range; and cold welding a subset of the set of bumps to the first set of protrusions and cold welding a second subset of the set of bumps to the second set of protrusions.

Drawings

Embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a network of data processing systems;

FIG. 2 is a block diagram of an embodiment of the present invention;

FIG. 3 is a block diagram of an embodiment of the present invention;

FIG. 4 is a block diagram of an example configuration in accordance with an illustrative embodiment;

FIG. 5 is a block diagram of an embodiment of the present invention;

FIG. 6 is a block diagram of an embodiment of the present invention;

FIG. 7 is a block diagram of an embodiment of the present invention;

FIG. 8 is a block diagram of an embodiment of the present invention; and the number of the first and second electrodes,

fig. 9 is a flow chart of a process according to an embodiment of the invention.

Detailed Description

Embodiments of the invention described herein generally address and solve the above-described needs in quantum device assembly.

Operations described herein as occurring with respect to a frequency or frequencies should be interpreted as signal occurrences with respect to the frequency or frequencies. All references to "signals" are references to microwave signals unless expressly distinguished at the time of use.

One embodiment of the present invention provides a configuration of a quantum computing device. Another embodiment of the invention provides a manufacturing method for a device such that the method can be implemented as a software application. An application implementing the manufacturing method may be configured to operate in conjunction with an existing manufacturing system, such as a lithography system or a circuit assembly system.

For clarity of description, and not to imply any limitations on it, embodiments of the invention are described using some example configurations. Many alterations, adaptations, and modifications of the described configurations to achieve the described purposes will be apparent to those skilled in the art in light of this disclosure, and such alterations, adaptations, and modifications are contemplated as being within the scope of the invention.

Further, a simplified diagram of example assembly components is used in the figures. In actual manufacturing or circuitry, there may be additional structures or components not shown or described herein, or structures or components other than those shown but for similar functions as described herein, without departing from the scope of the invention.

Furthermore, embodiments of the invention are described herein with reference to specific actual or hypothetical components, by way of example only. The described steps may be adapted to manufacture circuits using various components, which may be purposed or repurposed to provide the described functionality, and such adaptations are contemplated to be within the scope of the present invention.

Embodiments of the present invention are described, by way of example only, with respect to certain types of materials, electrical properties, steps, quantities, frequencies, circuits, components and applications. Any particular representation of these and other similar artifacts is not intended to limit the present invention. Any suitable representation of these and other similar artifacts may be selected within the scope of the present invention.

The examples in this disclosure are for clarity of description only and do not limit the invention. Any advantages listed herein are merely exemplary and are not intended to limit the present invention. Additional or different advantages may be realized. Moreover, particular embodiments of the invention may have some, all, or none of the above listed advantages.

FIG. 1 is a diagram of a data processing environment 100 in which embodiments of the present invention may be implemented. FIG. 1 is only an example and is not intended to assert or imply any limitation with regard to the environments in which different embodiments of the present invention may be implemented. The specific implementations may make many modifications to the depicted environments based on the following description.

Data processing environment 100 is a network of computers in which illustrative embodiments may be implemented. Data processing environment 100 includes a network 102. Network 102 is the medium used to provide communications links between various devices and computers connected together within data processing environment 100. Network 102 may include connections, such as wire, wireless communication links, or fiber optic cables.

A client or server is only an example role for certain data processing systems connected to network 102 and is not intended to exclude other configurations or roles of such data processing systems. Server 104 and server 106 couple to network 102 along with storage unit 108. The software application may execute on any computer in the data processing environment 100. Clients 110, 112, and 114 are also coupled to network 102. A data processing system, such as server 104 or 106 or client 110, 112, or 114, may contain data and may have software applications or software tools executing thereon.

The device 132 is an example of a mobile computing device. For example, the device 132 may take the form of a smartphone, tablet computer, laptop computer, fixed or portable form of the client 110, wearable computing device, or any other suitable device. Any software application described as executing in the other data processing system in fig. 1 may be configured to execute in the apparatus 132 in a similar manner. Any data or information stored or generated in the other data processing system in fig. 1 may be configured to be stored or generated in the device 132 in a similar manner.

Application 105 implements embodiments of the invention described herein. The fabrication system 107 is any suitable system for fabricating quantum devices. The application 105 provides instructions for flip-chip assembly of quantum devices to the system 107 in the manner described herein.

The hardware in FIG. 1 may vary depending on the implementation. Other internal hardware or peripheral devices, such as flash memory, equivalent non-volatile memory, or optical disk drives and the like, may be used in addition to or in place of the hardware depicted in FIG. 1. Also, the processes of embodiments of the present invention may be applied to a multiprocessor data processing system.

Fig. 2 is a block diagram of an example configuration 200. The application 105 interacts with the manufacturing system 107 to generate or manipulate the configuration 200 as described herein.

Configuration 200 includes a substrate 202. The substrate 202 includes a recess 202A disposed through the substrate 202. The substrate 202 includes a material having a predetermined thermal conductivity (above a threshold) in a low temperature range (about 77K to 0.01K). The substrate 202 is formed using a material that exhibits a Residual Resistance Ratio (RRR) of at least 100 and a thermal conductivity at 4 kelvin greater than 1W/(cm K) (a threshold level of thermal conductivity). RRR is the ratio of the resistivity of a material at room temperature and 0K. Since 0K cannot be reached in practice, an approximation at 4K is used. For example, the substrate 202 may be an organic substrate or a ceramic substrate for operation in a low temperature range. This example of substrate material is not intended to be limiting. Many other materials suitable for forming a substrate will be apparent to those of ordinary skill in the art in light of this disclosure, and are contemplated as within the scope of the present invention.

Embodiments of the present invention enable the manufacturing system 107 to create a set of protrusions 208 on the surface of the substrate 202. For example, embodiments of the invention may cause the manufacturing system to deposit the material 206, thereby forming the set of protrusions 208. In an embodiment of the present invention, the manufacturing system 107 includes a wire bonder to deposit the material 206 and form the protrusion 208. For example, the wire bonder may be pulled upward after forming the first half of the ball bond to deposit the remainder of the bump.

In an embodiment of the present invention, the protrusion 208 is a post. In another embodiment of the invention, the projections 208 are conical or pyramidal. For example, the protrusion 208 may have an approximately triangular, cylindrical, circular, or rectangular cross-section.

In an embodiment of the present invention, the protrusion 208 comprises a material 204 having a predetermined ductility (above a threshold) in a room temperature range (270 to 300K). In an embodiment of the present invention, the protrusion 208 is formed using a material exhibiting an elongation at break (a threshold level of ductility) of at least 20% over a room temperature range. Elongation at break is the ratio between the length of the material that increases after breaking in a tensile test and the initial length. For example, the protrusion 208 may be formed using gold, platinum, or a superconducting material coated with gold. In an embodiment, the protrusion 208 is formed using a material that is resistant to oxidation, chemical degradation of the surface of the material caused by oxygen. These examples of substrate materials, deposition devices, protrusion shapes, and protrusion materials are not intended to be limiting. Many other shapes, materials, and deposition devices suitable for forming the substrate and protrusions will occur to those of ordinary skill in the art in view of this disclosure, and are contemplated as being within the scope of the present invention.

Fig. 3 is a block diagram of an example configuration 300. The application 105 interacts with the manufacturing system 107 to generate or manipulate the configuration 300 as described herein.

Configuration 300 includes substrate 302, interposer 306, and qubit chip 310. Substrate 302 is an example of substrate 202 in fig. 2. Embodiments of the present invention enable manufacturing system 107 to deposit material on interposer 306 to form a set of bumps 308. For example, embodiments of the invention may cause manufacturing system 107 to solder the set of bumps 308 on interposer 306. As another example, the set of bumps 308 may be formed by electroplating, evaporation, ball mounting, paste printing, spraying, or Injection Molding Soldering (IMS).

In an embodiment of the present invention, the set of bumps 308 comprises a material having a predetermined ductility (above a threshold) in the room temperature range. In an embodiment of the present invention, the set of bumps 308 is formed using a material exhibiting an elongation at break of at least 20% over a room temperature range. For example, the set of bumps 308 are formed using at least one of indium, tin, lead, bismuth, and any combination thereof.

Embodiments of the present invention enable a manufacturing system to couple qubit chips 310 to interposer 306. In an embodiment of the present invention, the manufacturing system 107 cold-bonds a set of pads of the qubit chip 310 with a subset of the set of solder bumps 308 on the interposer 306. In an embodiment of the present invention, the manufacturing system 107 cold welds the second subset of the set of solder bumps 308 to the set of protrusions 304 formed on the substrate 302. The tab 304 is similar to the tab 208 of fig. 2.

In an embodiment of the present invention, each protrusion 304 is coupled to a corresponding solder bump 308. For example, each protrusion 304 may pierce a corresponding solder bump 308. Piercing the corresponding solder bump 308 enables contact between the outer surface of the protrusion 304 and the unoxidized inner surface of the solder bump 308. In another embodiment, a plurality of protrusions 304 are coupled to a single solder bump 308. Embodiments of the present invention enable the manufacturing system to cold solder the second subset of solder bumps 308 to the set of protrusions 304. Cold welding is a welding process in which coupling occurs without heating at the interface of two parts to be welded. In cold welding, no liquid or molten phase is present. After coupling, the qubit chip 310 is disposed in the recess 302A of the substrate. These examples of deposition methods and solder bump materials are not intended to be limiting. Many other materials and methods suitable for forming the set of bumps will be apparent to those of ordinary skill in the art in light of this disclosure, and are contemplated as within the scope of the present invention.

Fig. 4 is a block diagram of an example configuration 400. The application 105 interacts with the manufacturing system 107 to generate or manipulate the configuration 400 as described herein.

Configuration 400 includes qubit chip 402. Qubit chip 402 comprises a material having a predetermined thermal conductivity (above a threshold) in a low temperature range. In an embodiment of the invention, qubit chip 402 is formed using a material that exhibits a RRR of at least 100 and a thermal conductivity at 4 kelvin greater than 1W/(cm K) (the threshold level of thermal conductivity). For example, the qubit chip 402 may be formed using sapphire, silicon, quartz, gallium arsenide, fused silica, amorphous silicon, or diamond for operation in a low temperature range.

Embodiments of the present invention enable manufacturing system 107 to produce a set of protrusions 408 on the surface of qubit chip 402 by a manufacturing system that deposits material 406 in the same manner as material 206 is deposited to form protrusions 208. The protrusion 408 may be a post and may have a triangular, cylindrical, or rectangular cross-section.

In an embodiment of the present invention, the protrusion 408 comprises a material 404 similar to the material 204 of the protrusion 208. These examples of the protrusion material, qubit chip material, protrusion shape, and deposition method are not intended to be limiting. Many other materials and methods suitable for forming the substrate, qubit chip, and projections will occur to those of ordinary skill in the art in view of this disclosure, and are contemplated as being within the scope of the invention.

Fig. 5 is a block diagram of an example configuration 500. The application 105 interacts with the manufacturing system 107 to generate or manipulate the configuration 500 as described herein.

Configuration 500 includes substrate 502, interposer 506, and qubit chip 510. Substrate 502 is an example of substrate 202 in fig. 2. Embodiments of the present invention cause manufacturing system 107 to deposit material on interposer 506 to form a set of bumps 508 in a manner similar to the formation of bumps 308 on interposer 306.

In an embodiment of the present invention, the set of bumps 508 includes a material similar to the material of bumps 308.

Embodiments of the present invention enable the manufacturing system 107 to couple the qubit chip 510 to the interposer 506. In an embodiment of the invention, the manufacturing system 107 cold-welds a set of protrusions 512 of the qubit chip 510 with a subset of the set of solder bumps 508 on the interposer 506. In an embodiment of the present invention, each protrusion 512 is coupled to a corresponding solder bump 508. For example, each protrusion 512 may pierce a corresponding solder bump 508. Embodiments enable the manufacturing system to cold solder the first subset of solder bumps 508 to the set of protrusions 512. Cold welding is a welding process in which the interface of two parts to be welded is in the room temperature range. In cold welding, the interface is in a solid state.

Embodiments of the present invention enable the manufacturing system 107 to couple the interposer 506 to the substrate 502. In an embodiment of the present invention, the manufacturing system 107 cold welds the second subset of the set of solder bumps 508 to the set of protrusions 504 formed on the substrate 502. In an embodiment of the present invention, each protrusion 504 is coupled to a corresponding solder bump 508. For example, each protrusion 504 may pierce a corresponding solder bump 508. Embodiments of the present invention enable the manufacturing system 107 to cold solder the second subset of solder bumps 508 to the set of protrusions 504. The protrusion 504 is similar to the protrusion 208 in fig. 2. After coupling the substrate 502 and the interposer 506, the qubit chip 510 is disposed in the recess 502A of the substrate. These examples of deposition methods and solder bump materials are not intended to be limiting. Many other materials and deposition methods suitable for forming the set of bumps will be apparent to those of ordinary skill in the art in light of this disclosure, and are contemplated to be within the scope of the present invention.

Fig. 6 is a block diagram of an example configuration 600. The application 105 interacts with the manufacturing system 107 to generate or manipulate the configuration 600 as described herein.

Configuration 600 includes a substrate 602 and a qubit chip 604. The substrate 602 is an example of the substrate 202 in fig. 2. Qubit chip 604 is an example of qubit chip 402 in fig. 4. Embodiments of the present invention cause the manufacturing system 107 to deposit material on the substrate 606, thereby forming a set of bumps 606. For example, embodiments of the invention may cause the manufacturing system 107 to solder the set of bumps 606 to the substrate 602. As another example, the set of bumps 606 may be formed by electroplating, evaporation, ball mounting, paste printing, spraying, or Injection Molding Soldering (IMS).

In an embodiment of the present invention, the set of bumps 606 comprises a material having a predetermined ductility (above a threshold) in the room temperature range. In an embodiment of the present invention, the set of bumps 606 is formed using a material exhibiting an elongation at break of at least 20% over a room temperature range. For example, the set of bumps 606 is formed using at least one of indium, tin, lead, bismuth, and any combination thereof.

Embodiments of the present invention enable the manufacturing system 107 to couple the qubit chip 604 to the substrate 602. In an embodiment of the present invention, the manufacturing system 107 cold-solders a set of protrusions 608 of the qubit chip 604 with the set of solder bumps 606 on the substrate 602. In an embodiment of the present invention, each protrusion 608 is coupled to a corresponding solder bump 606. For example, each protrusion 608 may pierce a corresponding solder bump 606. Embodiments of the present invention enable the manufacturing system 107 to cold weld the set of solder bumps 606 with the set of protrusions 608. These examples of deposition methods and solder bump materials are not intended to be limiting. Many other materials and deposition methods suitable for forming the set of bumps will be apparent to those of ordinary skill in the art in light of this disclosure, and are contemplated to be within the scope of the present invention.

Fig. 7 is a block diagram of an example configuration 700. Configuration 700 is an example of a cold-welded connection between protrusion 304 and bump 308, protrusion 504 and bump 508, protrusion 512 and bump 508, or bumps 606 and 608, respectively, in fig. 4, 5, and 6. Configuration 700 includes a first substrate 702, a first pad 704, a protrusion 706, a bump 708, a second pad 710, and a second substrate 712.

The substrate 702 may be formed of the same material as the substrate 202.

The substrate 712 comprises a material having a predetermined thermal conductivity (above a threshold) in a low temperature range. In an embodiment of the present invention, substrate 712 is formed using a material similar to that of qubit chip 402.

In an embodiment of the present invention, the first and second pads 704 and 710 are formed using at least one of titanium, palladium, gold, silver, copper, or platinum for operation in a low temperature range. In an embodiment of the present invention, the first pad 704 and the second pad 710 are deposited as Under Bump Metallurgy (UBM) by using a sputtering, evaporation, or plating method.

The protrusion 706 is an example of the protrusion 208 in fig. 2. Bump 708 is an example of bump 408 in fig. 4. Embodiments of the present invention enable the manufacturing system 107 to couple the first substrate 702 to the second substrate 712. In an embodiment of the present invention, the manufacturing system 107 cold-solders the protrusions 706 of the first substrate 702 with the solder bumps 708 on the second substrate 712. For example, the protrusions 706 may pierce the corresponding solder bumps 708. Embodiments of the present invention enable the manufacturing system 107 to cold solder the solder bumps 708 to the protrusions 706.

In an embodiment of the present invention, bumps 708 are formed using a material similar to that used to form bumps 308.

In an embodiment of the present invention, the bump 708 is formed using a material that exhibits superconductivity in a low temperature range. In an embodiment of the present invention, the bump 708 contacts the first pad 704 and the second pad 710. In an embodiment of the present invention, the bump 708 provides a superconducting path between the first pad 704 and the second pad 710 in a cryogenic temperature range. These examples of substrate materials, bump materials, deposition methods, and pad materials are not intended to be limiting. Many other materials and deposition methods suitable for forming components of the device will be apparent to those of ordinary skill in the art in light of this disclosure, and are contemplated as within the scope of the present invention.

Fig. 8 is a block diagram of an example configuration. Configuration 800 is an example of a cold-welded connection between protrusion 304 and bump 308, protrusion 504 and bump 508, protrusion 512 and bump 508, or bump 606 and protrusion 608, respectively, in fig. 4, 5, and 6. Configuration 800 includes a first substrate 802, a first pad 804, a protrusion 806, a bump 808, a second pad 810, and a second substrate 812.

Substrate 802 is similar to substrate 702.

Substrate 812 is similar to substrate 712.

In an embodiment of the present invention, the first pad 804 and the second pad 810 are similar to the pads 704 and 710. These examples are not intended to be limiting. Many other materials suitable for forming the first layer will be apparent to those of ordinary skill in the art in light of this disclosure, and are contemplated as within the scope of the present invention.

The protrusion 806 is an example of the protrusion 208 in fig. 2. Bump 808 is an example of bump 308 in fig. 3. Embodiments of the present invention enable a manufacturing system to couple a first substrate 802 to a second substrate 812. In an embodiment of the present invention, the manufacturing system 107 cold-solders the protrusions 806 of the first substrate 802 with the solder bumps 808 on the second substrate 812. For example, the protrusions 806 may pierce the corresponding solder bumps 808. Embodiments of the present invention enable the manufacturing system to cold solder the solder bumps 808 with the protrusions 806.

In an embodiment of the present invention, bumps 808 are similar to bumps 308.

In an embodiment of the present invention, the capacitance of the electrical connection is determined by the distance between pads 804 and 810. For example, the capacitance is inversely proportional to the distance or gap height between pads 804 and 810. In an embodiment of the present invention, the protrusion 806 has a height corresponding to a desired capacitance of the electrical connection. In an embodiment of the present invention, the gap height is a function of the height of the projections 806 and the compressive force during cold welding. For example, the gap height may have an inverse relationship with the amount of compressive force during cold welding. As another example, the gap height may have a direct relationship with the height of the protrusion 806. These examples of substrate materials, bump materials, deposition methods, and pad materials are not intended to be limiting. Many other materials and deposition methods suitable for forming components of the device will be apparent to those of ordinary skill in the art in light of this disclosure, and are contemplated as within the scope of the present invention. In an embodiment of the invention, the height of the corresponding protrusion differs between a set of protrusions formed on the surface. For example, the height of the protrusions may be varied to accommodate warpage of the substrate.

With respect to fig. 9, this figure depicts a flow diagram of a quantum device assembly process. Process 900 may be implemented in application 105 to cold weld electrical connections as described with respect to fig. 2-8.

The application causes the manufacturing system to deposit a first set of stud bumps (protrusions) on the qubit chip (block 902); depositing a second set of pillar bumps (protrusions) on the substrate (block 904); and depositing a set of bumps, such as a set of solder bumps, on the interposer (block 906). The application causes the manufacturing system to form electrical connections between the qubit chip and the interposer (block 908), such as electrical connections between stud bumps on the cold-soldered qubit chip and solder bumps on the interposer. The application causes the manufacturing system to form electrical connections between the interposer and the substrate (block 910), such as between pillar bumps on the cold solder substrate and solder bumps on the interposer. The application causes the manufacturing system to form electrical connections between the qubit chip and the substrate (block 912), such as electrical connections between stud bumps on a cold-soldered qubit chip and solder bumps on the substrate. The application then ends the process 900. These examples of process steps and the order of process steps are not intended to be limiting. Numerous other steps and sequences of process steps suitable for quantum device assembly will occur to those of ordinary skill in the art in light of this disclosure, and are contemplated as within the scope of the present invention.

Various embodiments of the present invention are described herein with reference to the accompanying drawings. Alternate embodiments may be devised without departing from the scope of the invention. Although various connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are set forth in the following description and drawings, those skilled in the art will recognize that many of the positional relationships described herein are orientation-independent, while maintaining the described functionality even with changes in orientation. These connections and/or positional relationships may be direct or indirect unless otherwise specified, and the invention is not intended to be limited in this respect. Thus, coupling of entities may refer to direct or indirect coupling, and positional relationships between entities may be direct or indirect positional relationships. As an example of an indirect positional relationship, references in this specification to forming layer "a" over layer "B" include the case where one or more intervening layers (e.g., layer "C") are between layer "a" and layer "B" so long as the relevant properties and functions of layer "a" and layer "B" are not substantially changed by the intervening layer(s).

The following definitions and abbreviations are used to interpret the claims and description. As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," "contains" or "containing" or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

Additionally, the term "illustrative" is used herein to mean "serving as an example, instance, or illustration. Any embodiment or design described herein as "illustrative" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" should be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "coupled" can include both indirect "coupled" and direct "coupled".

References in the specification to "one embodiment," "an example embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

The terms "about," "substantially," "approximately," and variations thereof are intended to encompass the degree of error associated with measuring a particular quantity based on equipment available at the time of filing the present application. For example, "about" may include a range of ± 8% or 5%, or 2% of a given value.

The description of various embodiments of the present invention has been presented for purposes of illustration but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application, or technical improvements to the technology found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.