阅读说明：本技术 半导体复合装置及其所使用的封装基板 (Semiconductor composite device and package substrate used therefor ) 是由 姫田高志 北村达矢 榊千春 清野绅弥 藤田颂 山本笃史 古川刚史 西山健次 舟木达弥 于 2018-10-18 设计创作，主要内容包括：本发明的半导体复合装置(10)具备电压调节器(VR)(100)、封装基板(200)以及负载(300),将输入直流电压转换为不同的直流电压并供给至负载(300)。VR(100)包含半导体有源元件。封装基板(200)包含形成有电容器(230)的C层(210)、和形成有电感器(252)的L层(250)。在封装基板(200)形成在垂直于安装面的方向上贯通C层(210)以及L层(250)的多个通孔(260、262)。电容器(230)经由通孔(262)连接于负载(300)。电感器(252)经由通孔(262)连接于负载(300),并且经由通孔(260)连接于VR(100)。(A semiconductor composite device (10) is provided with a Voltage Regulator (VR) (100), a package substrate (200), and a load (300), and converts an input DC voltage into a different DC voltage and supplies the different DC voltage to the load (300). VR (100) includes semiconductor active elements. A package substrate (200) includes a C layer (210) having a capacitor (230) formed thereon and an L layer (250) having an inductor (252) formed thereon. A plurality of through holes (260, 262) penetrating the C layer (210) and the L layer (250) in a direction perpendicular to the mounting surface are formed in the package substrate (200). The capacitor (230) is connected to the load (300) via a via (262). The inductor (252) is connected to the load (300) via a via (262) and to the VR (100) via a via (260).)

1. A semiconductor composite device for converting an input DC voltage into a different DC voltage, comprising:

a voltage regulator including a semiconductor active element;

a load to which the converted direct-current voltage is supplied; and

a package substrate on which the load is mounted on a mounting surface,

the package substrate includes:

a first layer formed with a capacitor; and

a second layer formed with an inductor and different from the first layer,

a plurality of through holes are formed in the package substrate, the through holes penetrating the first layer and the second layer in a direction perpendicular to the mounting surface,

the capacitor is electrically connected to the load via a first via of the plurality of vias,

the inductor is electrically connected to the load via a second one of the plurality of vias and to the voltage regulator via a third one of the plurality of vias.

2. The semiconductor composite device according to claim 1,

the first through hole is in common with the second through hole.

3. The semiconductor composite device according to claim 1 or 2,

the inductor and the capacitor at least partially overlap each other when the package substrate is viewed from a direction perpendicular to the mounting surface.

4. The semiconductor composite device according to any one of claims 1 to 3,

the second layer is formed to include:

a metal wiring forming a coil; and

and a composite material surrounding the metal wiring and including a resin and a magnetic body.

5. The semiconductor composite device according to any one of claims 1 to 4,

the capacitor is an electrolytic capacitor.

6. The semiconductor composite device according to any one of claims 1 to 5,

the first layer comprises a first core substrate having glass cloth therein.

7. The semiconductor composite device according to claim 6,

a metal layer comprising copper is disposed on at least one surface of the first core substrate.

8. The semiconductor composite device according to claim 6,

a recess is formed on at least one surface of the first core base material.

9. The semiconductor composite device according to any one of claims 1 to 8,

the first layer comprises:

a first insulating member contacting the capacitor and arranged around the capacitor; and

a second insulating member arranged to surround the first insulating member,

a difference between a linear expansion coefficient of the capacitor and a linear expansion coefficient of the first insulating member is smaller than a difference between a linear expansion coefficient of the capacitor and a linear expansion coefficient of the second insulating member.

10. The semiconductor composite device according to any one of claims 1 to 9,

a chopper-type buck switching regulator is formed by the voltage regulator, the inductor, and the capacitor.

11. The semiconductor composite device according to claim 10,

the inductor and the capacitor function as an LC filter for smoothing an output of the voltage regulator.

12. The semiconductor composite device according to any one of claims 1 to 11,

the plurality of vias also includes at least one fourth via that is not connected to both the inductor and the capacitor.

13. The semiconductor composite device according to claim 12,

the fourth through hole is connected to an external ground wire.

14. The semiconductor composite device according to claim 12,

the fourth through hole is connected to an external signal line.

15. The semiconductor composite device according to claim 14,

the inner diameter of the fourth through hole is smaller than the inner diameters of the first through hole to the third through hole.

16. The semiconductor composite device according to claim 12,

the fourth through hole is connected to an external radiator.

17. The semiconductor composite device according to claim 12,

the number of the fourth through holes is a plurality of,

the package substrate further includes a via hole filled with an insulating material inside and formed to penetrate the first layer and the second layer,

the fourth through hole is formed in the through hole.

18. The semiconductor composite device according to any one of claims 12 to 17,

the fourth through hole is connected to the load directly below the load.

19. The semiconductor composite device according to any one of claims 1 to 18,

the mounting face is formed on a first face of the first layer,

the second layer is connected to a second side of the first layer opposite the first side.

20. The semiconductor composite device according to any one of claims 1 to 18,

the package substrate further includes a circuit layer formed with a plurality of wiring patterns,

the circuit layer is disposed on a first side of the first layer,

the second layer is disposed on a second face of the first layer opposite the first face,

the mounting surface is formed on a surface of the circuit layer opposite to the first layer side.

21. The semiconductor composite device according to claim 20,

the circuit layer includes a second core substrate.

22. The semiconductor composite device according to claim 20 or 21,

the voltage regulator is formed within the circuit layer.

23. The semiconductor composite apparatus according to claim 22,

the load overlaps the voltage regulator when the package substrate is viewed from a direction perpendicular to the mounting surface.

24. The semiconductor composite device according to any one of claims 19 to 23,

the package substrate further includes a terminal layer formed with a plurality of wiring patterns,

the terminal layer is disposed on a face of the second layer opposite the first layer.

25. The semiconductor composite device according to any one of claims 1 to 21,

the voltage regulator is mounted to the mounting surface.

26. A semiconductor composite device for converting an input DC voltage into a different DC voltage and supplying the different DC voltage to a load, the semiconductor composite device comprising:

a voltage regulator including a semiconductor active element; and

a package substrate configured to be able to mount the load on a mounting surface,

the package substrate includes:

a first layer formed with a capacitor;

a second layer having an inductor formed therein and different from the first layer; and

a connection terminal disposed on the mounting surface for electrical connection with the load,

a first through hole and a second through hole are formed in the package substrate, the first through hole and the second through hole penetrating the first layer and the second layer in a direction perpendicular to the mounting surface,

the capacitor is electrically connected to the load via the first via,

the inductor is electrically connected to the load via the first via and to the voltage regulator via the second via.

27. A semiconductor composite device which receives a DC voltage adjusted by a voltage regulator including a semiconductor active element, the semiconductor composite device comprising:

a load that operates using the DC voltage; and

a package substrate on which the load is mounted on a mounting surface,

the package substrate includes:

a first layer formed with a capacitor;

a second layer having an inductor formed therein and different from the first layer; and

a connection terminal disposed on the mounting surface for electrical connection with the voltage regulator,

a first through hole and a second through hole are formed in the package substrate, the first through hole and the second through hole penetrating the first layer and the second layer in a direction perpendicular to the mounting surface,

the capacitor is electrically connected to the load via the first via,

the inductor is electrically connected to the load via the first via and to the voltage regulator via the second via.

28. A package substrate for a semiconductor composite device for supplying a DC voltage adjusted by a voltage regulator including a semiconductor active element to a load, the package substrate comprising:

a first layer formed with a capacitor;

a second layer having an inductor formed therein and different from the first layer; and

a connection terminal disposed on the mounting surface of the package substrate for electrical connection with the voltage regulator and the load,

a first through hole and a second through hole are formed in the package substrate, the first through hole and the second through hole penetrating the first layer and the second layer in a direction perpendicular to the mounting surface,

the capacitor is electrically connected to the load via the first via,

the inductor is electrically connected to the load via the first via and to the voltage regulator via the second via.

29. The semiconductor composite device according to claim 1,

a metallization layer is formed on the inner surface of the plurality of through holes,

a metal wiring layer electrically connected to the metallization layer is formed on the surface of the package substrate,

in at least one via of the plurality of vias, a thickness of a connection portion of the metallization layer and the metal wiring layer is thicker than a thickness of the metal wiring layer.

30. The semiconductor composite device according to claim 1,

a metallization layer is formed on the inner surface of the plurality of through holes,

a metal wiring layer electrically connected to the metallization layer is formed on the surface of the package substrate,

in at least one via of the plurality of vias, a thickness of the metallization layer is thicker than a thickness of the metal wiring layer.

31. The semiconductor composite device according to claim 29 or 30,

an end of at least one of the plurality of through holes is chamfered.

32. The semiconductor composite device according to claim 1, or claim 26, or claim 27,

the package substrate further includes a third layer formed with other capacitors different from the capacitor,

a conductive member connected to an anode electrode of the capacitor is arranged on the mounting surface side with respect to the capacitor in the first layer,

a conductive member connected to the anode electrode of the other capacitor is arranged on the opposite side of the mounting surface with respect to the other capacitor in the second layer.

33. The semiconductor composite device according to claim 1, or claim 26, or claim 27,

the package substrate further includes a third layer formed with other capacitors different from the capacitor,

the second layer is disposed between the first layer and the third layer.

Technical Field

The present invention relates to a semiconductor composite device and a package substrate used for the same, and more particularly, to a structure of a semiconductor composite device used for a dc voltage conversion device.

Background

U.S. patent application publication No. 2011/0050334 (patent document 1) discloses a semiconductor device including a package substrate in which a part or all of a passive element (passive element) such as an inductor or a capacitor is embedded, and a voltage control device (hereinafter, also referred to as a "voltage regulator") including an active element (active element) such as a switching element. In the semiconductor device of patent document 1, a voltage regulator and a load to which a power supply voltage is to be supplied are mounted on a package substrate. The dc voltage adjusted by the voltage adjustment unit is smoothed by a passive element in the package substrate and supplied to the load.

Patent document 1: U.S. patent application publication No. 2011/0050334 specification

The semiconductor device having the voltage regulator as described above is applied to electronic devices such as a mobile phone and a smartphone. In recent years, electronic devices have been reduced in size and thickness, and along with this, reduction in size of semiconductor devices itself has been desired.

In the semiconductor device of patent document 1, the inductor and the capacitor are laid out and embedded in the same layer of the package substrate. In this case, if the area of the mounting surface of the package substrate is reduced for the purpose of downsizing the semiconductor device, it is considered that the inductance of the inductor and the capacitance of the capacitor formed in the package substrate cannot be sufficiently secured, and desired characteristics cannot be achieved.

Disclosure of Invention

The present disclosure has been made to solve the above-described problems, and an object thereof is to suppress a decrease in characteristics of a semiconductor composite device and to achieve miniaturization in a semiconductor composite device using a package substrate in which an inductor or a capacitor is embedded and a voltage regulator.

The semiconductor composite device according to the present disclosure has a function of converting an input dc voltage into a different dc voltage. The semiconductor composite device includes: a voltage regulator including a semiconductor active element; a load to which the converted direct-current voltage is supplied; and a package substrate on which a load is mounted on the mounting surface. The package substrate includes: a first layer formed with a capacitor; and a second layer formed with an inductor and different from the first layer. The package substrate is provided with a plurality of through holes penetrating through the first layer and the second layer in a direction perpendicular to the mounting surface. The capacitor is electrically connected to a load via a first via of the plurality of vias. The inductor is electrically connected to a load via a second one of the plurality of vias and to the voltage regulator via a third one of the plurality of vias.

Preferably, the first through hole and the second through hole are in common.

Preferably, the inductor and the capacitor at least partially overlap each other when the package substrate is viewed from a direction perpendicular to the mounting surface.

Preferably, the second layer is formed to include the following portions: a metal wiring forming a coil; and a composite material surrounding the metal wiring and including a resin and a magnetic body.

Preferably, the capacitor is an electrolytic capacitor.

Preferably, the step-down switching regulator is formed in a chopper type by a voltage regulator, an inductor, and a capacitor.

Preferably, the inductor and the capacitor function as an LC filter for smoothing the output of the voltage regulator.

Preferably, the plurality of vias further includes at least one fourth via that is not connected to both the inductor and the capacitor.

Preferably, the fourth through hole is connected to an external ground line.

Preferably, the fourth through hole is connected to an external signal line.

Preferably, the inner diameter of the fourth through hole is smaller than the inner diameters of the first to third through holes.

Preferably, the fourth through hole is connected to an external heat sink.

Preferably, the fourth through hole is provided in plurality. The package substrate further includes a via hole filled with an insulating material and formed to penetrate the first layer and the second layer. The fourth through hole is formed in the through hole.

Preferably, the fourth through-hole is connected to the load directly below the load.

Preferably, the mounting surface is formed on the first surface of the first layer. The second layer is attached to a second face of the first layer opposite the first face.

Preferably, the package substrate further includes a circuit layer on which a plurality of wiring patterns are formed. The circuit layer is disposed on the first side of the first layer. The second layer is disposed on a second side of the first layer opposite the first side. The mounting surface is formed on a surface of the circuit layer opposite to the first layer side.

Preferably, the circuit layer comprises a core substrate.

Preferably, the voltage regulator is formed within the circuit layer.

Preferably, the load overlaps the voltage regulator in the circuit layer when the package substrate is viewed from a direction perpendicular to the mounting surface.

Preferably, the package substrate further includes a terminal layer formed with a plurality of wiring patterns. The terminal layer is disposed in the second layer on a side opposite to the first layer.

Preferably, the voltage regulator is mounted on the mounting surface.

A semiconductor composite device according to another aspect of the present disclosure supplies an input dc voltage to a load by converting a dc voltage into a dc voltage different from the dc voltage. The semiconductor composite device includes: a voltage regulator including a semiconductor active element; and a package substrate configured to be able to mount a load on the mounting surface. The package substrate includes: a first layer formed with a capacitor; a second layer having an inductor formed therein and different from the first layer; and a connection terminal arranged on the mounting surface for electrical connection with a load.

The package substrate is provided with first and second through holes penetrating the first and second layers in a direction perpendicular to the mounting surface. The capacitor is electrically connected to the load via the first via. The inductor is electrically connected to a load via a first via and to the voltage regulator via a second via.

A semiconductor composite device according to another aspect of the present disclosure receives a dc voltage adjusted by a voltage regulator including a semiconductor active element. The semiconductor composite device includes: a load that operates using the dc voltage; and a package substrate on which a load is mounted on the mounting surface. The package substrate includes: a first layer formed with a capacitor; a second layer having an inductor formed therein and different from the first layer; and a connection terminal arranged on the mounting surface for electrically connecting with the voltage regulator. The package substrate is provided with a first through hole and a second through hole which penetrate through the first layer and the second layer in a direction perpendicular to the mounting surface. The capacitor is electrically connected to the load via the first via. The inductor is electrically connected to a load via a first via and to the voltage regulator via a second via.

A package substrate according to still another aspect of the present disclosure is used for a semiconductor composite device in which a dc voltage adjusted by a voltage regulator including a semiconductor active element is supplied to a load. The package substrate includes: a first layer formed with a capacitor; a second layer having an inductor formed therein and different from the first layer; and a connection terminal arranged on the mounting surface of the package substrate for electrically connecting the voltage regulator and the load. The package substrate is provided with first and second through holes penetrating the first and second layers in a direction perpendicular to the mounting surface. The capacitor is electrically connected to the load via the first via. The inductor is electrically connected to a load via a first via and to the voltage regulator via a second via.

In the semiconductor composite device according to the present disclosure, the first layer in which the capacitor is formed and the second layer in which the inductor is formed are stacked as different layers in the package substrate, and the capacitor and/or the inductor are electrically connected to the voltage regulator or the load via the through hole. Thus, when the semiconductor composite device is miniaturized, it is easier to secure capacitance and inductance compared to a case where the capacitor and the inductor are laid out in the same layer. Therefore, the semiconductor composite device can be miniaturized while suppressing the characteristic degradation thereof.

Drawings

Fig. 1 is a block diagram of a semiconductor composite device according to embodiment 1.

Fig. 2 is a plan view of the semiconductor composite device according to embodiment 1.

Fig. 3 is a cross-sectional view of the semiconductor composite device of fig. 2, as viewed in the direction of the line III-III.

Fig. 4 is a cross-sectional view of the semiconductor composite device of fig. 2, as viewed in the direction of the arrow along the line IV-IV.

Fig. 5 is a top view of a portion of the C layer of fig. 2.

Fig. 6 is a top view of a portion of the L layer of fig. 2.

Fig. 7 is a flowchart showing a manufacturing process of the semiconductor composite device.

Fig. 8 is a diagram for explaining the formation process (S100) of the C layer.

Fig. 9 is a diagram for explaining the L layer formation process (S110).

Fig. 10 is a diagram for explaining a bonding process (S120) of the C layer and the L layer.

Fig. 11 is a diagram for explaining the formation process (S130) of the through-hole.

Fig. 12 is a diagram for explaining the electrode pattern forming process (S140) and the machine mounting process (S150).

Fig. 13 is a cross-sectional view of a semiconductor composite device according to embodiment 2.

Fig. 14 is a cross-sectional view of a semiconductor composite device according to embodiment 3.

Fig. 15 is a cross-sectional view of a semiconductor composite device according to embodiment 4.

Fig. 16 is a cross-sectional view of a first example of the semiconductor composite device according to embodiment 5.

Fig. 17 is a cross-sectional view of a second example of the semiconductor composite device according to embodiment 5.

Fig. 18 is a cross-sectional view of a semiconductor composite device according to embodiment 6.

Fig. 19 is a plan view of the C layer of the semiconductor composite device according to embodiment 7.

Fig. 20 is a cross-sectional view of the semiconductor composite device of fig. 19, as viewed in the direction of the XIX-XIX ray arrows.

Fig. 21 is a cross-sectional view of a semiconductor composite device according to embodiment 8.

Fig. 22 is a flowchart illustrating a manufacturing process of the semiconductor composite device of fig. 21.

Fig. 23 is a first diagram for explaining details of a manufacturing process of the semiconductor composite device of fig. 21.

Fig. 24 is a second diagram for explaining details of a manufacturing process of the semiconductor composite device of fig. 21.

Fig. 25 is a third diagram for explaining details of a manufacturing process of the semiconductor composite device of fig. 21.

Fig. 26 is a fourth diagram for explaining details of a manufacturing process of the semiconductor composite device of fig. 21.

Fig. 27 is a view 5 for explaining details of a manufacturing process of the semiconductor composite device of fig. 21.

Fig. 28 is a cross-sectional view of a semiconductor composite device according to modification 1 of embodiment 8.

Fig. 29 is a flowchart illustrating a manufacturing process of the semiconductor composite device of fig. 28.

Fig. 30 is a cross-sectional view of a semiconductor composite device according to modification 2 of embodiment 8.

Fig. 31 is a cross-sectional view of a semiconductor composite device according to embodiment 9.

Fig. 32 is a flowchart illustrating a manufacturing process of the semiconductor composite device of fig. 31.

Fig. 33 is a first diagram for explaining details of a manufacturing process of the semiconductor composite device of fig. 31.

Fig. 34 is a second diagram for explaining details of a manufacturing process of the semiconductor composite device of fig. 31.

Fig. 35 is a third diagram for explaining details of a manufacturing process of the semiconductor composite device of fig. 31.

Fig. 36 is a diagram for explaining a first example of a plating process for a through hole in the semiconductor composite device according to embodiment 10.

Fig. 37 is a diagram for explaining a second example of the plating process for the through hole in the semiconductor composite device according to embodiment 10.

Fig. 38 is a diagram for explaining a modification of the through hole portion in the semiconductor composite device according to embodiment 10.

Fig. 39 is a plan view of the C layer in the semiconductor composite device according to embodiment 11.

Fig. 40 is a cross-sectional view of the layer C of fig. 39.

Fig. 41 is a view showing modification 1 of the core base material in fig. 39.

Fig. 42 is a view showing modification 2 of the core base material in fig. 39.

Fig. 43 is a view showing modification 3 of the core base material in fig. 39.

Fig. 44 is a cross-sectional view of the C layer in the semiconductor composite device according to embodiment 12.

Fig. 45 is a cross-sectional view of a semiconductor composite device according to embodiment 13.

Fig. 46 is a first example of a cross-sectional view of a semiconductor composite device according to embodiment 14.

Fig. 47 is a second example of a cross-sectional view of a semiconductor composite device according to embodiment 14.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding portions are denoted by the same reference numerals, and description thereof will not be repeated.

[ embodiment 1]

(constitution of device)

Fig. 1 is a block diagram of a semiconductor composite device 10 according to embodiment 1. Referring to fig. 1, a semiconductor composite device 10 includes a Voltage controller (Voltage Regulator: VR) 100, a package substrate 200, and a load 300. Here, the load 300 is, for example, a semiconductor Integrated Circuit (IC) such as a logic operation circuit or a memory circuit.

The voltage regulator 100 includes an active element (not shown) such as a semiconductor switching element, and adjusts a dc voltage supplied from the outside to a voltage level suitable for the load 300 by controlling a duty ratio (duty) of the active element.

The package substrate 200 has the voltage regulator 100 and the load 300 mounted on its surface, and constitutes the semiconductor composite device 10 as one package component. As described in detail later with reference to fig. 2, an inductor L1 and a capacitor CP1 are formed inside the package substrate 200.

The inductor L1 is connected between the input terminal IN and the output terminal OUT of the package substrate 200. Inductor L1 is connected to voltage regulator 100 at input terminal IN and to load 300 at output terminal OUT. The capacitor CP1 is connected between the output terminal OUT and the ground terminal GND. The chopper type step-down switching regulator is formed by the voltage regulator 100 and the inductor L1 and the capacitor CP1 in the package substrate 200. The inductor L1 and the capacitor CP1 function as a ripple filter of the step-down switching regulator. The switching regulator steps down, for example, a dc voltage of 5V input from the outside to 1V, and supplies the stepped-down voltage to the load 300.

Further, the package substrate 200 is mounted with electronic devices such as a decoupling capacitor for noise countermeasure, a choke inductor, a diode element for surge protection, and a resistance element for voltage division in addition to the voltage regulator 100 and the load 300.

Next, a detailed configuration of the semiconductor composite device 10 will be described with reference to fig. 2 to 6. Fig. 2 is a plan view of the semiconductor composite device 10 as viewed from the mounting surface of the package substrate 200. Fig. 3 is a sectional view taken in the direction of the arrow III-III in fig. 2, and fig. 4 is a sectional view taken in the direction of the arrow IV-IV in fig. 2. Fig. 5 is a top view of a portion of the C layer 210 constituting the capacitor CP1, and fig. 6 is a top view of a portion of the L layer 250 forming the inductor L1.

Referring to fig. 2, through-holes 260 corresponding to the input terminals IN, 262 corresponding to the output terminals OUT, and 264 corresponding to the ground terminals GND are formed at 3 corners of the mounting surface of the package substrate 200.

The through holes 260, 262, and 264 penetrate from the surface to the bottom surface in the thickness direction of the package substrate 200, and the inner surfaces of the through holes are metallized with a low-resistance metal such as copper (Cu), gold (Au), or silver (Ag). For example, electroless Cu plating or electrolytic Cu plating can be used for metallization in terms of ease of processing. The metallization of the through hole is not limited to the case of metallizing only the inner surface of the through hole, and may be filled with a metal, a composite material of a metal and a resin, or the like.

The voltage regulator 100 is disposed at a position overlapping the via 260, and the load 300 is disposed at a position overlapping the via 262. That is, the vias 260 and 262 are formed at positions directly below the voltage regulator 100 and the load 300, respectively. As described above, the voltage regulator 100 and the electronic device 350 other than the load 300 are mounted on the mounting surface of the package substrate 200.

Referring to fig. 3 to 6, the package substrate 200 includes a C layer 210 constituting the capacitor CP1, an L layer 250 forming the inductor L1, and resin layers 226, 227, and 228.

The resin layers 226, 227, and 228 are used as bonding materials for bonding the respective layers to each other, and are used as insulating layers for insulating the exposed surfaces of the C layer 210 and the L layer 250. The C layer 210 and the L layer 250 are joined by the resin layer 227. A resin layer 226 is formed on the surface of the C layer 210, and a resin layer 228 is formed on the bottom surface of the L layer 250. The resin layers 226, 227, and 228 are formed of an insulating material such as an epoxy resin or a composite material of an epoxy resin and an inorganic filler such as silica. In order to secure adhesion to the metallization layer of the through hole, a material mainly composed of an epoxy resin is preferably used as the resin layer. Alternatively, prepregs containing fibrous reinforcing materials such as glass cloth or carbon fibers may be used as the resin layers 226, 227, and 228. In particular, by using a prepreg having a small linear expansion coefficient such as glass cloth, warpage of the C layer 210 and the L layer 250 can be suppressed, and warpage of the entire package substrate 200 can be suppressed.

On the surface of resin layer 226, a circuit layer 205 including pads for mounting devices such as voltage regulator 100 and wiring for connecting them is formed. The machine mounted on the package substrate 200 is electrically connected to the pads or terminals of the circuit layer 205 via the solder bumps 120.

The circuit layer 205 is formed of a low-resistance metal material such as Cu, Au, or Ag. The circuit layer 205 is not limited to being formed only on the surface of the resin layer 226, and may be formed in a plurality of layers inside the resin layer 226, for example, as described later. The surface of the pad or the terminal formed on the mounting surface of the circuit layer 205 is subjected to surface treatment such as nickel/gold (Ni/Au), nickel/lead/gold (Ni/Pb/Au), or pre-solder treatment in order to facilitate mounting of the device. In order to prevent solder from flowing during surface mounting of the device, a solder resist layer may be formed on the outermost layer of the circuit layer 205.

The C layer 210 includes a capacitor portion 230 forming a capacitor CP1, a conductive portion 220 electrically connected to the through hole 262 of the output terminal OUT, a conductive portion 240 electrically connected to the through hole 264 of the ground terminal GND, and an insulating portion 225 provided around them. The capacitor part 230 includes an anode electrode 232 made of a core material of a valve-acting metal base, a porous layer 234 disposed on at least one main surface of the core material and having a dielectric layer and a solid electrolyte layer on a surface thereof, and a cathode electrode 236 provided on the solid electrolyte layer, and forms an electrolytic capacitor. The dielectric layer is formed on the surface of the porous layer of the valve-acting metal substrate. The dielectric layer formed on the surface of the porous layer is porous reflecting the surface state of the porous layer, and has a surface shape with fine irregularities. Preferably, the dielectric layer is formed of an oxide film of the valve metal. In the electrolytic capacitor of the present invention, examples of the solid electrolyte material constituting the solid electrolyte layer include conductive polymers such as polypyrroles, polythiophenes, and polyanilines. Among them, polythiophenes are preferred, and poly (3, 4-ethylenedioxythiophene) known as PEDOT is particularly preferred. The conductive polymer may contain a dopant such as polystyrene sulfonic acid (PSS). The solid electrolyte layer preferably includes an inner layer filling pores (recesses) of the dielectric layer and an outer layer covering the dielectric layer.

The conductive portions 220 and 240 are mainly made of a low-resistance metal such as Ag, Au, or Cu. The conductive adhesive material obtained by mixing the conductive filler with a resin may be used as the conductor part for the purpose of improving the interlayer adhesive force. The porous layer 234 is made of, for example, aluminum oxide (AlO)₂) Or tantalum oxide (Ta)₂O₅) And the like. Porous layer234 are formed by covering the surface of a metal (e.g., Al, Ta) serving as a porous base material of the anode electrode 232 with an oxide film. The cathode electrode 236 is formed of a low-resistance metal such as Ag, Au, or Cu.

The insulating portion 225 is made of a resin such as epoxy resin, phenol, or polyimide, or an inorganic filler such as silica or alumina and the resin.

The anode electrode 232 has a flat plate shape, and is disposed between 2 porous layers 234 having a flat plate shape. A cathode electrode 236 is formed on the surface of each porous layer 234 opposite to the anode electrode 232.

As shown in fig. 2 and 5, the porous layer 234 on the mounting surface side of the device is partially cut away and the anode electrode 232 is exposed, and the anode electrode 232 is electrically connected to the conductive portion 220 through the via hole 222 in the cut portion 235. In addition, the cathode electrode 236 is electrically connected to the conductive portion 240 through the via hole 242.

In addition, as the capacitor portion 230, a ceramic capacitor using barium titanate, or silicon nitride (SiN) or silicon dioxide (SiO) may be used₂) And Hydrogen Fluoride (HF), etc. However, from the viewpoint of forming a capacitor portion having a thinner and relatively large area and mechanical characteristics such as rigidity and flexibility of the package substrate, an electrolytic capacitor using a metal such as aluminum as a base material is preferable.

In the capacitor part 230, through-holes are formed in portions where the through-holes 260, 262, and 264 are formed, and the insulating material of the insulating part 225 is filled between the through-holes and the through-holes.

In embodiment 1, the thickness of each of the anode electrode 232 and the porous layer 234 is about 50 μm, the thickness of each of the conductive parts 220 and 240 is about 15 μm, and the thickness of the entire C layer 210 as the thickness of the insulating part 225 above and below the capacitor part 230 is about 200 μm.

As shown in fig. 6, the L layer 250 includes a coil portion 252 forming an inductor L1 and an insulating portion 254 formed by resin molding around the coil portion 252.

The coil portion 252 is a metal wiring formed by spirally patterning a core material (Cu foil) formed of Cu of about 100 μm by an electroforming method or a rolling method with a photoresist or the like, and then etching the core material. The coil portion 252 has one end electrically connected to the through hole 260 and the other end electrically connected to the through hole 262.

Further, aluminum (Al) may be used as the core material of the coil portion 252. In particular, when the capacitor unit 230 is formed of an electrolytic capacitor based on aluminum, if the core material of the coil unit 252 is formed of copper, the entire package substrate 200 may be warped due to a difference in linear expansion coefficient between aluminum and copper. In this case, the difference in linear expansion coefficient can be reduced by using aluminum as the core material of the coil portion 252, and warpage of the entire substrate can be suppressed.

The insulating portion 254 is formed of, for example, a resin such as epoxy resin, phenol, or polyimide, or a mixed material of these resins and an inorganic magnetic filler such as ferrite or silicon steel. In the case of a circuit for supplying dc power to the load 300 as in embodiment 1, it is preferable to use a filler of a metal-based magnetic material such as silicon steel having excellent dc superposition characteristics.

The inorganic magnetic filler may also be dispersed with fillers having different average particle diameters, for example, for the purpose of improving magnetic characteristics, or with a gradient in dispersion concentration for the purpose of preventing magnetic saturation. In addition, a filler in a flat shape or in a sheet shape may be used in order to impart directionality to the magnetic properties. When a metal material such as silicon steel is used as the inorganic magnetic filler, a surface insulating film may be applied around the filler through an inorganic insulating film, an organic insulating film, or the like in order to improve the insulating property.

In addition, for the purpose of reducing the difference in linear expansion coefficient with the coil portion 252, improving heat dissipation, insulation, and the like, an inorganic filler or an organic filler other than the magnetic material may be mixed.

The inductance can be adjusted by adjusting the thickness of the insulating portion 254. In the example of embodiment 1, the upper and lower insulating portions 254 of the coil portion 252 of 100 μm are each 100 μm, and the thickness of the entire L layer 250 is about 300 μm.

A terminal layer 270 for mounting the semiconductor composite device 10 on a mother substrate (not shown) is formed on the surface of the resin layer 228 provided on the bottom surface of the L layer 250. The terminal layer 270 includes the input terminal IN, the output terminal OUT, and the ground terminal GND. Similarly to the circuit layer 205 formed on the C layer 210, the terminal layer 270 may include a wiring constituting a circuit in addition to the terminal, or may be further composed of a plurality of layers.

The package substrate 200 is generally required to have a thickness of 2mm or less from the viewpoint of reduction in thickness of a system, heat dissipation of the load 300, and the like. In the example of embodiment 1, the upper circuit layer including the resin layer 226 and the circuit layer 205 is 50 μm, the C layer 210 is 200 μm, the resin layer 227 is 20 μm, the L layer is 300 μm, the bottom terminal layer including the resin layer 228 and the terminal layer 270 is 50 μm, and the thickness of the entire semiconductor composite device 10 is about 0.6 mm.

In the semiconductor composite device 10 having the above configuration, since the inductor L1 and the capacitor CP1 constituting the ripple filter are formed from different layers of the package substrate 200, the area available for forming the inductor and the capacitor can be increased as compared with a conventional configuration in which the inductor and the capacitor are formed in the same layer. This makes it easy to secure inductance and capacitance when the device is miniaturized. As shown in fig. 5 and 6, when the package substrate 200 is viewed from a plane perpendicular to the mounting surface of the package substrate 200, the capacitor portion 230 in the C layer 210 and the coil portion 252 in the L layer 250 are arranged so as to at least partially overlap in different layers. This enables further downsizing of the device.

In the configuration of embodiment 1, the connection between the voltage regulator 100 and the load 300 and the inductor L1 and the capacitor CP1 in the package substrate 200 and the connection between the inductor L1 and the capacitor CP1 are connected by using the through holes 260, 262, and 264 penetrating the package substrate 200 without using planar wiring on the substrate. This can shorten the connection distance, reduce the impedance of the wiring, reduce the power loss, and minimize the layout of the circuit surface on the substrate. Therefore, the restriction on the miniaturization of the device can be further reduced.

In the L layer 250 formed by the inductor L1, the coil portion 252 is molded with the insulating portion 254 including a magnetic material, so that the generated magnetic flux density can be increased, and the Q value of the inductor L1 can be increased. This can reduce the loss due to the inductor L1. In addition, since the magnetic coupling between the inductor L1 and the capacitor CP1 and between the inductor L1 and the active element of the voltage regulator 100 can be reduced by the magnetic material, noise propagation associated with the magnetic coupling can be suppressed. Therefore, the device characteristics can be further improved.

In the above description, the C layer is disposed on the L layer in the package substrate, but the order of the L layer and the C layer may be reversed if the electrical connection is maintained.

In addition, although the above description has been made on the example of the step-down switching regulator applied to the chopper type, the features of embodiment 1 can be applied to a semiconductor composite device in which a power transmission line including another step-up/step-down circuit is made into a system.

(manufacturing Process of device)

Next, a manufacturing process of the semiconductor composite device 10 according to embodiment 1 will be described with reference to fig. 7 to 12. Fig. 7 is a flowchart for explaining an outline of the manufacturing process, and fig. 8 to 12 are diagrams for explaining details of each step of the flowchart of fig. 7.

Referring to fig. 7, in S100 and S110, the C layer 210 and the L layer 250 are independently formed. Thereafter, in S120, the C layer 210 and the L layer 250 after formation are joined and integrated by using the resin layers 226, 227, and 228. Next, in S130, a through hole is formed in the integrated C layer 210 and L layer 250. Thereafter, a pattern of electrodes and wires is formed on the mounting surface (S140), and devices such as the voltage regulator 100 are mounted on the completed package substrate 200 (S150).

Fig. 8 is a diagram for explaining a process of forming the C layer 210 in S100. Referring to fig. 8 (a), first, both surfaces of aluminum to be the anode electrode 232 are processed to be porous, and an oxide film is applied to the surface thereof to form the porous layer 234. Then, a cured film of a conductive paste such as Cu paste is formed on the surface of the porous layer 234, thereby forming a cathode electrode 236.

At this time, as in the C layer 210 in fig. 3, a part of the porous layer 234 is cut by, for example, a dicing process until the aluminum of the anode electrode 232 is exposed, and the Cu paste is fired on the exposed aluminum. Thereby, the capacitor part 230 is formed.

Then, a through hole is formed in a portion where the through hole is to be formed by drilling, laser processing, or the like.

Next, as shown in fig. 8 (b), a resin such as an epoxy resin, a polyimide, or a phenol, or a mixed material of the resin and an inorganic filler is laminated to the capacitor part 230 and is further thermally cured, thereby sealing the capacitor part 230 and forming the insulating part 225. After the sealing treatment, the conductive layer 212 for forming the conductive portions 220 and 240 for connecting the through holes to the respective electrodes of the capacitor portion 230 is formed on the surface of the insulating portion 225 by plating or the like.

Then, the conductive layer 212 is processed by etching or the like to form conductive portions 220 and 240. Then, holes reaching the anode electrode 232 and the cathode electrode 236 are formed in the conductive portions 220 and 240 by laser processing or the like, and a conductive body such as Cu is filled therein, whereby the conductive portion 220 is electrically connected to the anode electrode 232, and the conductive portion 240 is electrically connected to the cathode electrode 236 (fig. 8 (c)). Thereby, the C layer 210 is formed.

Fig. 9 is a diagram for explaining a process of forming the L layer 250 in S110. Referring to fig. 9 (a), first, both surfaces of a Cu foil 252# to be a core are patterned with a photoresist or the like, and a photoresist opening portion is etched to form a coil portion 252 (fig. 9 (b)).

Then, an epoxy resin composite sheet in which a metal magnetic filler such as ferrite or silicon steel is dispersed is laminated on the surface of the coil portion 252 using a vacuum laminator or the like, and planarization and thermosetting treatment of the epoxy resin layer are performed by a hot press, thereby forming the insulating portion 254 ((c) of fig. 9).

Then, a through hole is formed in the portion to be provided with the through hole by drilling, laser processing, or the like, and the through hole is filled with an insulating resin 265 (fig. 9 (d)). Thereby, the L layer 250 is formed.

Fig. 10 is a diagram for explaining a bonding process of the C layer 210 and the L layer 250 in S120.

Referring to fig. 10 (a), resin layers 226, 227, and 228, each of which is formed by forming a resin such as an epoxy resin, polyimide, or phenol, or a mixed material of the resin and an inorganic filler in a sheet shape, are disposed on the upper, lower, and intermediate surfaces of the C layer 210 and the L layer 250 formed in S100 and S110. Then, these stacked layers are bonded and cured by vacuum pressure or the like to be integrated, thereby forming a package substrate 200 (fig. 10 (b)).

Fig. 11 is a diagram for explaining a process of forming the through hole in S130.

Referring to fig. 11 (a), after the package substrate 200 is formed by integrating the respective layers, a through hole is formed in a portion where the through hole is to be formed by drilling or laser processing. Then, the inside of the through hole and the surfaces of the resin layers 226 and 228 are metallized by electroless Cu plating or the like (fig. 11 (b)).

In this case, electrolytic Cu plating may be further performed to increase the thickness of the metal layer 269 on the surface of the resin layer, or to fill the via hole with Cu.

Fig. 12 is a diagram for explaining the processes corresponding to S140 and S150. Referring to fig. 12 (a), in S140, the metal layer 269 on the surface of the resin layer is patterned using a photoresist, and unnecessary Cu is removed by etching, thereby forming wirings, pads, and terminals on the surface of the resin layer, which form the circuit layer 205 and the terminal layer 270. In this case, in order to facilitate the mounting of the device, a surface treatment such as Ni/Au plating, Ni/Pb/Au plating, or pre-solder treatment is performed on the metal surface of the pad, the terminal, or the like. In addition, a solder resist layer may be formed on the outermost layer portion in order to prevent solder flow during surface mounting of the device.

In the package substrate 200 thus formed, the voltage regulator 100, the load 300, and other electronic devices 350 are mounted on the circuit layer 205 on the surface of the C layer 210, thereby forming the semiconductor composite device 10 according to embodiment 1 (fig. 12 (b)).

In this embodiment, the "C layer 210" and the "L layer 250" are examples of the "first layer" and the "second layer" in the present disclosure.

[ embodiment 2]

In embodiment 2, a description will be given of a configuration in which a ground line for a signal of a device mounted on a mounting surface is formed by a through hole, in addition to the configuration of the package substrate 200 shown in embodiment 1.

Fig. 13 is a cross-sectional view of a semiconductor composite device 10A according to embodiment 2. Fig. 13 corresponds to fig. 4 of embodiment 1, and shows a state in which the semiconductor composite device 10A is mounted on the mother substrate 400.

Referring to fig. 13, package substrate 200A included in semiconductor composite device 10A is provided with through hole 266, and through hole 266 is connected to a terminal of a signal ground line of load 300 when load 300 is mounted on the substrate. The through hole 266 penetrates through the terminal layer 270 on the bottom surface without being electrically connected to the capacitor portion 230 and the coil portion 252 included in the C layer 210 and the L layer 250. The terminal 410 connected to the ground line of the mother substrate 400 is electrically connected to the solder bump 380.

In this way, by connecting the ground line of the mounted device to the ground line of the mother board 400 via the through hole 266 at the shortest distance, the grounding can be strengthened and the resistance to noise can be improved. In addition, since the through hole is used, the layout on the substrate can be minimized, and the influence on miniaturization can be reduced.

In fig. 13, although the through hole of the ground line of the load 300 is described, the ground line of another mounting device may have the same configuration.

[ embodiment 3]

In embodiment 2, a configuration in which a ground line for a signal of a device mounted via a through hole is connected to a ground line of the mother board 400 has been described, but when a signal line between the device and the mother board 400 is required, the signal line may be connected using a through hole.

Fig. 14 is a cross-sectional view of a semiconductor composite device 10E according to embodiment 4. Referring to fig. 14, a package substrate 200E included in the semiconductor composite device 10E is provided with a through hole 267, and the through hole 267 is connected to a terminal of a signal line of the voltage regulator 100 or the load 300 arranged on the mounting surface. The through hole 267 penetrates through the terminal layer 270 on the bottom surface without being electrically connected to the capacitor portion 230 and the coil portion 252 included in the C layer 210 and the L layer 250, as in the through hole 266 for the ground line for the signal in embodiment 2. The through hole 267 is electrically connected to a signal line for connection to an I/O terminal of a device (not shown) formed on the mounting surface of the mother substrate 400 via the solder bump 380 and the terminal 410.

Since the current flowing through the through hole 267 is smaller than the current flowing through the power through holes 260, 262, and 264 connected to the capacitor unit 230 and the coil unit 252, the inner diameter of the through hole 267 can be smaller than the through holes 260, 262, and 264.

In this way, when signal lines for exchanging signals between the mounted device and the mother substrate 400 are required, they can be connected to the mother substrate 400 at the shortest distance by connecting them via the through holes 267. Further, by making the through hole for signal smaller than the through hole for power, the layout on the substrate can be minimized, and the influence on miniaturization can be reduced.

Note that, although the through hole 266 for the ground line described in embodiment 2 is described in addition to the through hole 267 for the signal line in fig. 14, the through hole 266 may be omitted and only the through hole 267 for the signal line may be provided.

[ embodiment 4]

In embodiment 4, a configuration having through holes of a heat sink connected to the outside for improving heat dissipation of each device mounted on a mounting surface will be described in addition to the configuration of the package substrate 200 described in embodiment 1.

Fig. 15 is a cross-sectional view of a semiconductor composite device 10B according to embodiment 4. Fig. 15 corresponds to fig. 4 of embodiment 1, and shows a state in which the semiconductor composite device 10B is mounted on the mother substrate 400.

Referring to fig. 15, the package substrate 200B includes at least one through hole 268 that is connected to a terminal of the load 300 and is not electrically connected to the capacitor portion 230 and the coil portion 252 included in the C layer 210 and the L layer 250. The through hole 268 is connected to a terminal of the load 300 directly below the load 300. The through hole 268 is connected to a heat sink 450 provided on the mother substrate 400 via a solder bump 380 on the bottom surface of the package substrate 200B.

The heat sink 450 is made of a metal having high thermal conductivity, such as Al or Cu. By connecting the mounting device such as the load 300 to the heat sink 450 through the through hole 268 in this manner, heat generated in the load 300 can be efficiently discharged to the outside. Further, the through hole 268 can dissipate heat generated in the inductor and the like in the package substrate 200B.

Further, a through hole 268 for connecting to the heat sink 450 may be provided also for a mounting device other than the load 300. The number of through holes 268 is not limited to the number shown in fig. 15, and may be determined according to the heat dissipation capacity required for the connected mounting device.

[ embodiment 5]

In embodiments 1 to 4, the description has been given of the configuration in which the package substrate includes 1C layer and 1L layer, respectively.

However, the area of the mounting surface may be limited due to a restriction in the size of the semiconductor composite device or the like. In such a case, the area of the electrode in the C layer in particular may not be sufficiently secured, and a desired capacitance may not be obtained.

Therefore, in embodiment 5, a configuration in which a desired capacitance is secured by providing a plurality of C layers in a package substrate will be described.

Fig. 16 is a cross-sectional view of a semiconductor composite device 10C according to embodiment 5. Fig. 16 corresponds to fig. 4 of embodiment 1. In the package substrate 200C of fig. 16, 2 layers of the C1 layer 210A and the C2 layer 210B are provided as layers constituting the capacitor CP1. The C1 layer 210A and the C2 layer 210B have substantially the same configuration as the C layer 210 of embodiment 1, and therefore, the details thereof are not repeated, but the C1 layer 210A and the C2 layer 210B share the same through hole and are electrically connected in parallel between the output terminal OUT and the ground terminal GND. This slightly increases the height of semiconductor composite device 10C, but the capacitance of capacitor CP1 can be increased without changing the mounting area of the package substrate.

In fig. 16, the C1 layer 210A and the C2 layer 210B are disposed on the L layer 250, but the order of the layers is not particularly limited as long as the electrical connection relationship is the same, and the L layer 250 may be disposed between the C1 layer 210A and the C2 layer 210B as shown in the package substrate 200CA of fig. 17, for example. Alternatively, the C1 layer 210A and the C2 layer 210B may be disposed below the L layer 250. In the configuration in which the L layer 250 is disposed between the C1 layer 210A and the C2 layer 210B as shown in fig. 17, the warpage of the entire package substrate can be suppressed because the structure is vertically symmetrical in the stacking direction.

In the example of fig. 16, a plurality of C layers are provided to increase the capacitance, but a plurality of L layers may be provided when the inductance needs to be increased.

[ embodiment 6]

In embodiment 5, a configuration in which a C layer or an L layer is multilayered to increase capacitance and/or inductance is described.

On the other hand, in the case where the dimension in the height direction of the semiconductor composite device is limited, there may be a case where multilayering cannot be performed as in embodiment 4.

In embodiment 6, the following configuration will be explained: in the case where it is necessary to increase the capacitance and/or inductance in a state where the dimensional restriction in the height direction is strict and the dimensional restriction in the plane direction is slightly relaxed, a plurality of C layers and L layers are planarly bonded to secure a desired capacitance and inductance.

Fig. 18 is a cross-sectional view of a package substrate 200D of a semiconductor composite device according to embodiment 6. In the package substrate 200D of fig. 18, the following configuration is adopted: 2 package substrates 200D-1 and 200D-2 corresponding to the package substrate 200 shown in embodiment 1 share a through hole connected to the ground terminal GND, and are bonded in the planar direction.

With such a configuration, although the mounting area of the package substrate is increased, the capacitance and inductance can be increased while maintaining the dimension in the height direction. Such a configuration is effective when the demand for height reduction is particularly severe.

[ embodiment 7]

Through holes 266 to 268 shown in fig. 13 to 15 may be provided for each device mounted on the package substrate. In the case of forming a through hole, in order to insulate the through hole from a conductor such as a coil, a capacitor, and a wiring pattern formed in a package substrate, the periphery of the through hole needs to be surrounded by an insulating material. Thus, when the through holes 266 to 268 are formed independently at each position of the package substrate, the portion occupied by the insulating material around the through holes increases. This may limit the area of the mounting surface of the package substrate, which may hinder miniaturization, or may prevent realization of desired capacitance and inductance.

In embodiment 7, the following configuration will be explained: through holes 266 to 268, as described in fig. 13 to 15, other than through holes 260, 262 and 264 through which a main current flows in the package substrate are arranged in proximity to each other and surrounded by a common insulating material.

Fig. 19 is a plan view of the C layer 210 of the semiconductor composite device 10F according to embodiment 7, and fig. 20 is a cross-sectional view of fig. 19 as viewed in the direction of the XIX-XIX ray arrows.

Referring to fig. 19 and 20, a via hole 223 filled with an insulating material is formed in a portion not overlapping with each electrode of the capacitor of the C layer 210 and the coil portion 252 of the L layer 250. Signal through holes 266 and 267 are formed in the via hole 223. Fig. 19 also shows an example in which through holes other than the through holes 266 and 267 are provided in the via hole 223.

By forming the signal through-holes for the mounting device in the common via holes filled with the insulating material in this manner, the proportion of the insulating material required for forming the through-holes 266 to 268 on the mounting surface can be reduced, and thus the factor that hinders the miniaturization can be reduced. Further, since the common via hole is only required to be subjected to the insulating process, the number of steps can be reduced as compared with the case where the insulating process is performed for each via hole.

[ embodiment 8]

In embodiments 1 to 7 described above, a configuration in which the circuit layer 205 for mounting the voltage regulator 100 and the load 300 and the terminal layer 270 for mounting the semiconductor composite device 10 on the mother substrate are formed as one layer on the front surface and the back surface of the package substrate 200 is described.

In embodiment 8, an example in which the circuit layer and/or the terminal layer are configured to have a multilayer structure will be described.

Fig. 21 is a cross-sectional view of a semiconductor composite device 10G according to embodiment 8. In the package substrate 200G of the semiconductor composite device 10G, the circuit layer 205A having a multilayer structure including a plurality of wiring patterns is disposed on the surface of the C layer 210 not facing the L layer 250, and the load 300 and other electronic devices 350 are mounted on the surface of the circuit layer 205A.

In addition, a terminal layer 270A having a multilayer structure including a plurality of wiring patterns is disposed on a surface of the L layer 250 not facing the C layer 210.

In the package substrate 200G of fig. 21, the through holes 262, 264, 266, 267 penetrate the C layer 210 and the L layer 250, but do not penetrate the circuit layer 205A and the terminal layer 270A. That is, the C layer 210 and the L layer 250 are joined to form the via holes 262, 264, 266, 267, and then the circuit layer 205A is formed on the upper surface of the C layer 210 and the terminal layer 270A is formed on the lower surface of the L layer.

By forming the circuit layer 205A and the terminal layer 270A in a multilayer structure in this way, it is possible to form wiring patterns for connection to a device mounted on the mounting surface (the surface of the circuit layer 205A) in layers inside the circuit layer 205A, thereby reducing the wiring patterns formed on the mounting surface. Therefore, the surface area of the mounting surface can be reduced within a range that does not hinder the capacitance of the capacitor portion 230 of the C layer 210 and the inductance of the coil portion 252 of the L layer 250, and therefore the semiconductor composite device can be downsized compared to the case where the circuit layer and the terminal layer are formed in a single layer.

A manufacturing process of the semiconductor composite device 10G according to embodiment 8 will be described with reference to fig. 22 to 27. Fig. 22 is a flowchart for explaining an outline of the manufacturing process, and fig. 23 to 27 are diagrams for explaining details of steps in the flowchart of fig. 22.

In the flowchart of fig. 22, steps S200 to S230, S240, and S250 correspond to steps S100 to S130, S140, and S150 in the flowchart shown in fig. 7, respectively, and substantially add step S235 to the flowchart of fig. 7 described in embodiment 1.

Referring to fig. 22, in S200 and S210, a C layer 210 and an L layer 250 are formed independently from each other (fig. 23 (a)). Thereafter, in S220, the formed C layer 210 and L layer 250 are joined and integrated by using the resin layers 226, 227, and 228 ((b) of fig. 23).

Next, in S230, a through hole is formed in the integrated C layer 210 and L layer 250. More specifically, as shown in fig. 24 (a), a through hole is formed by drilling, laser processing, or the like at a position where a through hole is formed in the C layer 210 and the L layer 250 after bonding. Then, the inside of the through hole is metallized by electroless Cu plating or the like to form a through hole (fig. 24 (b)).

Thereafter, in S235, the circuit layer 205A is formed on the resin layer 226, and the terminal layer 270A is formed on the resin layer 228. Specifically, first, the metal layer 269 on the surface of the resin layers 226 and 228 is patterned using a photoresist, and unnecessary Cu is removed by etching to form a wiring pattern (fig. 25 (a)). Then, a resin layer 229A and a metal layer 269A are disposed thereon ((b) of fig. 25).

Further, by patterning the metal layer 269A to form a wiring pattern ((a) of fig. 26), a resin layer 229B and a metal layer 269B are further arranged on the patterned metal layer 269A ((B) of fig. 26).

When the steps shown in fig. 25 and 26 are repeated to form a desired number of wiring layers, in S240, the metal layer 269B on the outermost surface is patterned and etched to form electrode patterns for mounting devices and connection to solder bumps of a mounting substrate, and wiring patterns for connecting these electrode patterns to each other. Thus, the circuit layer 205A and the terminal layer 270A are formed, and the package substrate 200G is completed (fig. 27 (a)).

Thereafter, in S250, the device such as voltage regulator 100 is mounted on completed package substrate 200G (fig. 27 (b)).

In the above description, an example was described in which both the circuit layer 205A and the terminal layer 270A have a multilayer structure, but only either the circuit layer 205A or the terminal layer 270A may have a multilayer structure. The circuit layer 205A and the terminal layer 270A may have different numbers of layers.

In this way, by using the circuit layer and/or the terminal layer having a multilayer structure on the front surface and the back surface of the package substrate, the wiring width and the inter-wiring pitch of the wiring between the devices to be mounted can be secured, and therefore, the surface area of the mounting surface can be reduced, and the demand for further miniaturization can be met.

(modification 1)

Fig. 28 is a cross-sectional view of a first modification (modification 1) of the semiconductor composite device having the circuit layer having the multilayer structure described in embodiment 8.

Referring to fig. 28, in a semiconductor composite device 10H according to modification 1, a core base material 280 including glass cloth is disposed in a circuit layer 205B having a multilayer structure of a package substrate 200H.

In the manufacturing process of the package substrate, since a compressive force is applied when the layers are bonded, the layers may be deformed by the influence of the compressive force, and may be cracked or the like. In particular, in the circuit layer, since a rigid metal member such as the electrodes 232 and 236 of the C layer 210 or the coil portion 252 of the L layer 250 is not included, deformation due to an external force is likely to occur. Thus, by disposing such a core base material 280 in the circuit layer, the strength of the circuit layer can be ensured.

The material of the core base 280 is not limited to glass cloth as long as it has insulation and rigidity. As a material of the core base 280, for example, a metal core including a metal member (for example, Cu) whose surface is subjected to an insulating treatment, or the like can be used.

Fig. 29 is a flowchart illustrating a manufacturing process of the semiconductor composite device 10H of fig. 28. Referring to fig. 29, in S300 and S310, the C layer 210 and the L layer 250 are independently formed. In embodiment 8, in S315, a portion of the circuit layer 205B including the core base material 280 is formed. Here, in S315, only the portion of the circuit layer 205B where the via hole is formed together with the C layer 210 and the L layer 250 is formed.

Thereafter, in S320, the C layer 210, the L layer 250, and a part of the circuit layer 205B, which are independently formed in S300, 310, 315, are joined using a resin layer. Then, in S330, a through hole is formed in the integrated C layer 210, L layer 250, and circuit layer.

After the via hole is formed, in S335, a resin layer and a metal layer are further disposed on the bonded circuit layer as necessary to form an additional wiring layer. Note that, although the package substrate 200H in fig. 28 shows an example in which the terminal layers are single-layered, the terminal layers may also have a multilayer structure as in fig. 21 in embodiment 8. In this case, in S335, an additional wiring layer is also formed in the terminal layer.

Thereafter, in S340, the metal layers on the surfaces of the circuit layer 205B and the terminal layer 270 are patterned to form an electrode pattern and a wiring pattern. Thereby, the package substrate 200H is completed. Then, in S350, the devices such as the voltage regulator 100 and the load 300 are mounted on the mounting surface of the completed package substrate 200H, whereby the semiconductor composite device 10H is completed.

(modification 2)

Fig. 30 is a cross-sectional view of a second modification (modification 2) of the semiconductor composite device having the circuit layer having the multilayer structure described in embodiment 8.

Referring to fig. 30, a semiconductor composite device 10J according to modification 2 has a configuration in which the semiconductor active element 105 of the voltage regulator 100 is embedded in a circuit layer 205C having a multilayer structure. The active element 105 is preferably disposed in a layer formed of the core base material 280 shown in modification example 1 in order to reduce the influence of deformation (warpage, cracking) due to an external force or the like.

In the manufacturing process, when the circuit layer including the core base material 280 is formed in step S315 of fig. 29 explained in modification 1, a part of the core base material 280 is removed, and the active element 105 is arranged in the removed part. In addition, from the viewpoint of miniaturization, the active element 105 is preferably arranged to overlap the load 300 when the package substrate 200J is viewed in plan from the normal direction of the mounting surface.

By embedding the active element 105 of the voltage regulator 100 in the circuit layer 205C in this manner, the distance from the voltage regulator 100 to the load 300 through the L layer 250 and the C layer 210 can be shortened, and therefore, the loss generated in the electrical path can be reduced.

In addition, not only the active element 105 but also the entire voltage regulator 100 may be embedded in the circuit layer 205C.

[ embodiment 9]

In embodiments 1 to 8, the structure in which the through-hole penetrates both the C layer 210 and the L layer 250 has been described.

In embodiment 9, an example of a structure including a through hole penetrating only one of the C layer 210 and the L layer 250 in addition to a through hole penetrating both the C layer 210 and the L layer 250 in the package substrate will be described.

Fig. 31 is a cross-sectional view of a semiconductor composite device 10K according to embodiment 9. A through hole 267A that penetrates the C layer 210 and a part of the circuit layer 205D but does not penetrate the L layer 250 is formed in the package substrate 200K of the semiconductor composite device 10K. Such a via hole is formed for the purpose of connecting to the C layer without affecting the L layer, for example, when a capacitor is required in a circuit of the voltage regulator 100 mounted on a circuit layer or in an input portion.

Next, a manufacturing process of the semiconductor composite device 10K according to embodiment 9 will be described with reference to fig. 32 to 35. Fig. 32 is a flowchart for explaining an outline of the manufacturing process, and fig. 33 to 35 are diagrams for explaining details of steps in the flowchart of fig. 32.

Referring to fig. 32, the C layer 210 is formed in S400, and the circuit layer 205E, which is a part of the circuit layer 205D, is formed in S410. Then, in S420, the C layer 210 and the circuit layer 205E formed in S400 and S410, respectively, are bonded using the resin layer 292. Further, a metal layer 269C is formed on the surface of the C layer 210 opposite to the surface facing the circuit layer 205E via a resin layer 291, and a metal layer 269C is formed on the surface of the circuit layer 205E opposite to the surface facing the C layer 210 via a resin layer 293 (fig. 33 (a)).

Thereafter, in S430, a via 267A is formed in the integrated C layer 210 and the circuit layer 205E. Specifically, a through hole is formed at a position where the through hole 267A is formed by drilling, laser processing, or the like (fig. 33 (b)). Then, the inside of the through hole is metallized by electroless Cu plating or the like, thereby forming a through hole 267A ((c) of fig. 33). In fig. 33 (C), the metal layer 269C on the surfaces of the resin layers 291 and 293 is etched to form a wiring pattern.

When the through hole 267A penetrating the C layer 210 and the circuit layer 205E is formed, the L layer 250 is formed separately in S440 (fig. 34 (a)), and the L layer 250 is bonded to the C layer 210 using the resin layer 227 in S450 (fig. 34 (b)). In addition, a metal layer 269 is disposed via the resin layer 228 on the face of the L layer 250 opposite to the face opposite to the C layer 210. A metal layer 269 is disposed on the surface of the circuit layer 205E via a resin layer 294.

Then, in S460, a through hole penetrating the integrated circuit layer 205E, C layer 210 and L layer 250 is formed, and in S470, the metal layer 269 on the surface is etched to form an electrode pattern or a wiring pattern (fig. 35 (a), (b)). Thereby, the package substrate 200K is completed. Further, although not shown in fig. 35, more wiring layers may be formed for the circuit layer. The terminal layer 270 may also have a multilayer structure.

Then, in S480, a device such as a load 300 is mounted on the mounting surface of the circuit layer 205D, thereby forming the semiconductor composite device 10K.

In the above example, the configuration in which the through hole 267A that penetrates the C layer 210 but does not penetrate the L layer 250 is formed was described, but a through hole that does not penetrate the C layer 210 but penetrates the L layer 250 may be formed in reverse depending on the circuit configuration. In this case, a process is performed in which a via hole is formed after the L layer 250 is formed, and then the via hole is further formed by bonding with the C layer 210.

[ embodiment 10]

(example 1)

In the semiconductor composite device, power from the voltage regulator is supplied to the load through the through hole of the package substrate. In order to further improve the efficiency of the semiconductor composite device, it is necessary to reduce the Equivalent Series Resistance (ESR) from the voltage regulator to the load. One method of reducing the ESR is to reduce the resistance value in the through hole.

The through-holes formed in the package substrate have their inner surfaces metallized with a conductive material such as a metal. The resistance value of the via hole can be reduced by increasing the thickness of the metallization layer in the via hole.

In order to reduce the resistance value of the through hole, it is desirable to fill the inner hole of the through hole with a metal such as Cu, but it is generally known that it is technically difficult to fill the metal in the bottomless through hole by plating, and it takes a long time to perform the plating until the metal is filled.

The metallization of the through hole is performed by plating treatment with Cu or the like as described above, but as described with reference to fig. 11 and the like, a metal layer (metal wiring layer) for forming a wiring on the surface of the package substrate is also formed at the same time when the through hole is metallized. Thus, when the thickness of the metallization layer of the through hole is increased, the thickness of the metal wiring layer formed on the surface of the package substrate is also increased.

On the other hand, in order to form minute wirings in the metal wiring layer, it is preferable to reduce the thickness of the metal wiring layer, and there is a concern that the ratio of the interval between the wirings and the wirings, that is, L/s (line and space), is deteriorated due to the increased thickness of the metal wiring layer.

Therefore, in embodiment 10, the thickness of the metallization layer of the through hole is increased, and the thickness of the metal wiring layer formed on the surface of the package substrate is decreased. This reduces the resistance value of the through hole, and can realize miniaturization of the metal wiring formed on the surface of the package substrate.

However, in this case, the metallization layer on the inner surface of the through hole and the metal wiring layer on the surface of the package substrate are connected to each other at the end (connection portion) of the through hole. If the conductive member has a different thickness at such a connection portion, there is a possibility that a failure such as disconnection may occur due to concentration of current density at the connection portion or concentration of thermal stress caused by a difference in linear expansion coefficient from the dielectric substrate.

Thus, in embodiment 10, the thickness of the connection portion where the metallization layer and the metal wiring layer are connected is further made thicker than the thickness of the metal wiring layer. This can suppress the occurrence of quality defects in the connection portion.

A plating process for a through hole in a semiconductor composite device according to embodiment 1 of embodiment 10 will be described with reference to fig. 36. Note that in fig. 36, and fig. 37 and 38 described later, only the through-hole portion will be described with a focus on, and therefore, the configuration other than the through-hole may be omitted.

Referring to fig. 36, when a through hole is formed in the package substrate 200 by drilling or the like as described in fig. 11 a and 24 a (fig. 36 a), the inside of the through hole and the surface of the package substrate 200 are metallized by electroless Cu plating or the like to form a metallized layer 290 and a metal wiring layer 295 (fig. 36 b). At this time, the thickness of the Cu plating layer is set to a thickness suitable for the thickness of the metallization layer 290 to be formed on the inner surface of the via 260. Therefore, in this stage, the metal wiring layer 295 formed on the surface of the package substrate 200 is formed to be thicker than a desired thickness.

After the Cu plating treatment, the space inside the through hole 260 is filled with a resin 296 by printing or the like (fig. 36 (c)). At this time, a part of the metal wiring layer 295 in the vicinity of the via hole 260 is also covered with the resin 296.

Thereafter, the metal wiring layer 295 is subjected to wet etching to reduce the thickness of the metal wiring layer 295 to a desired thickness (fig. 36 (d)). At this time, the thickness of the plating layer is maintained without etching the portion covered with the resin 296. Thus, the thickness of the metallization layer 290 is thicker than the thickness of the metal wiring layer 295.

After the etching treatment, unnecessary portions of the resin 296 are removed by a treatment such as polishing with a polishing roll (fig. 36 (e)).

By making the thickness of the metallization layer 290 thicker than the thickness of the metal wiring layer 295 in this way, the on-resistance of the via 260 can be reduced, and the workability of the metal wiring layer 295 can be improved.

In the metal wiring layer 295, the thickness of the plating layer is also maintained in the vicinity of the through hole 260 without etching by the resin 296. This can increase the thickness of the plating layer at the boundary portion (connection portion) between the metallization layer 290 and the metal wiring layer 295, and thus can suppress defects due to thermal stress and the like.

(example 2)

In embodiment 1, an example in which the plating layer is formed to a thickness suitable for the metallization layer in the first plating treatment, and then the thickness of the metal wiring layer is reduced by the etching treatment is described.

In contrast, in embodiment 2, an example will be described in which, in the first plating treatment, the plating layer is formed to have a thickness suitable for the metal wiring layer, and then the thickness of the metallization layer of the through hole is increased.

Fig. 37 is a diagram for explaining a plating process of a through hole in the semiconductor composite device according to example 2 of embodiment 10. Referring to fig. 37, when a through hole is formed in the package substrate 200 (fig. 37 a), the inside of the through hole and the surface of the package substrate 200 are metallized by electroless Cu plating or the like to form a metallized layer 290 and a metal wiring layer 295 (fig. 37 b). The thickness of the Cu plating layer is set to be suitable for the thickness of the metal wiring layer 295.

After the plating treatment, a resist mask 297 is formed on the surface of the metal wiring layer 295 by photolithography (fig. 37 (c)). Further, at this time, the resist mask 297 is not formed for the vicinity of the via 260 in the metal wiring layer 295.

Thereafter, plating treatment is additionally performed on the inner surface of the through hole 260 and the portion of the metal wiring layer 295 where the resist mask 297 is not formed by electrolytic Cu plating treatment (fig. 37 (d)). Thus, the thickness of the Cu plating layer is thicker in the portion where the resist mask 297 is not formed than in the portion where the resist mask 297 is formed. The metallization layer 290 in the via 260 may have a non-uniform thickness as long as it is thicker than the metal wiring layer 295, and for example, as shown in fig. 37 (d), the thickness of the central portion in the penetrating direction of the via 260 may be thicker than the thickness of the end portions.

When the additional plating process is completed, the resist mask 297 is removed by a method such as organic stripping. Thereafter, the inside of the through-hole 260 is filled with the resin 296 (fig. 37 (e)) and unnecessary portions of the resin 296 are removed by a treatment such as polishing with a polishing roll in the same manner as in example 1 ((f) of fig. 37).

In such a process, the thickness of the metallization layer 290 can be made thicker than the thickness of the metal wiring layer 295, and the thickness of the plating layer at the connection portion can be further increased.

(example 3)

In embodiments 1 and 2, the end of the through hole 260 is substantially perpendicular to the surface of the package substrate 200, but such a shape tends to easily concentrate current density and thermal stress.

Therefore, in example 3, the end portion of the through hole 260 is chamfered to make the angle gentle, thereby alleviating the concentration of the current density and the thermal stress.

Fig. 38 is a diagram for explaining a portion of a through hole according to example 3 of embodiment 10. Referring to fig. 38, in example 3, when forming a through hole in the package substrate 200, a portion of an end portion of the through hole is chamfered by sandblasting or reaming.

After that, through the same process as in embodiment 1 or embodiment 2, the metallization layer 290 of the via hole and the metal wiring layer 295 are formed. Fig. 38 shows an example of a case where the metal wiring layer 295 is thinned by etching, as in embodiment 1 of fig. 36.

With this, it is possible to reduce the resistance value of the via hole and alleviate the concentration of the current density or the thermal stress at the boundary portion between the via hole and the metal wiring layer.

In examples 1 to 3 of embodiment 10, the present invention can be applied to all through holes formed in the package substrate, or to a part of (at least one) through holes.

As described above, the package substrate of the semiconductor composite device according to the present embodiment has a structure in which the C layer formed by the capacitor and the L layer formed by the inductor are stacked. In such a laminated structure, if the linear expansion coefficient of the entire C layer is different from the linear expansion coefficient of the entire L layer, the package substrate may be warped due to a temperature change during a manufacturing process or the like. In each of the C-layer and the L-layer, even a single layer may warp depending on the structure of each layer.

In embodiments 11 to 14 below, a configuration for suppressing warpage of a package substrate will be described.

[ embodiment 11]

As described in embodiment 1, the anode electrode 232 and the porous layer 234 forming the capacitor part 230 in the C layer 210 are formed, for example, with aluminum (Al) as a main component. On the other hand, the coil portion 252 forming the inductor L1 in the L layer 250 is formed mainly of copper (Cu), for example.

In the manufacturing process of the package substrate, the C layer 210 and the L layer 250 are bonded by heating and pressing. In general, since aluminum has a larger linear expansion coefficient than copper, the C layer 210 mainly composed of aluminum has a larger shrinkage amount during cooling than the L layer 250 mainly composed of copper. Such a difference in shrinkage may cause warpage of the package substrate, cracking in the pressing process, and the like.

Therefore, in embodiment 11, warpage, cracking, and the like of the substrate are suppressed by arranging the core substrate having a smaller linear expansion coefficient than aluminum inside the C layer to reduce the shrinkage of the C layer.

Fig. 39 and 40 are a plan view and a cross-sectional view, respectively, of the C layer 210C in the semiconductor substrate according to embodiment 11. Referring to fig. 39 and 40, in the C layer 210C, the core base material 245 is arranged so as to surround the periphery of the capacitor portion 230 of the C layer 210 shown in fig. 5.

The core base 245 is made of a material in which glass cloth is contained in a resin such as epoxy resin, and has a smaller linear expansion coefficient than aluminum. The core substrate 245 preferably has a linear expansion coefficient close to that of copper, which is the main component of the L layer 250. By disposing such a core base material 245 inside the C layer 210C, the strength of the C layer 210C itself can be improved, and warpage, cracking, or the like of the package substrate in the manufacturing process can be suppressed by reducing the difference in linear expansion coefficient with the L layer 250.

The C layer 210C is formed by the following process in general. First, the inside of a flat plate-like core base material 245 having a substantially rectangular shape is removed to form a frame shape, and the capacitor portion 230 shown in fig. 8 (a) of embodiment 1 is arranged in the frame. Then, the core base 245 and the capacitor part 230 are collectively sealed with a resin (insulating part 225) such as an epoxy resin. Thereafter, the conductive portions 220 and 240 are formed by the processes shown in fig. 8 (b) and (C) according to embodiment mode 1, thereby forming the C layer 210C.

(modification of core base Material)

In fig. 39 and 40, an example of a case where the core base material has a shape in which both the front surface and the back surface are substantially flat is described. In embodiments 12 and 13 described below, the C layer may have a structure in which the coefficients of expansion are different between the front side and the back side of the C layer, as will be described later. In this case, even in the C-layer single body, warpage may occur in the manufacturing process.

In the following modification, a configuration in which the linear expansion coefficients of the front surface side and the back surface side of the C layer are adjusted by making the structures of the front surface and the back surface of the core base material different will be described.

(modification 1)

Fig. 41 is a view showing a first modification (modification 1) of the core base 254 of fig. 39. In modification 1, a metal layer containing copper is formed on the front and/or back surface of the core base 245, thereby adjusting the linear expansion coefficients of the front and back surfaces of the C layer. In the example of fig. 41, a metal layer 247 having a mesh-like pattern is formed on one surface (front surface) of a core base 245, and a metal layer 246 is formed on the entire other surface (back surface). In this way, the linear expansion coefficients of the front surface side and the back surface side of the C layer can be adjusted by adjusting the amounts of the metal layers in the front surface and the back surface of the core base 245.

In fig. 41, an example in which a metal layer is provided on both the front surface and the back surface of the core base 245 is described, but a metal layer may be provided only on one of the front surface and the back surface. That is, a metal layer may be provided on at least one of the front surface and the back surface of the core base 245. In addition, any shape can be used for the form of the metal layer, and for example, the metal layers on both surfaces may be formed in a mesh shape.

(modification 2)

Fig. 42 is a view showing a second modification (modification 2) of the core base material of fig. 39. In the core base material 245A according to modification 2, the linear expansion coefficients of the front surface side and the back surface side of the C layer are adjusted by forming the concave portion 248 in one surface of the core base material 245A. In fig. 42, the concave portion 248 is formed only on one surface of the core base 245A, but the concave portion 248 may be formed on both the front surface side and the back surface side. In this case, the linear expansion coefficients of the front side and the back side are adjusted by changing the shape or the number of the concave portions 248 between the front side and the back side.

(modification 3)

Fig. 43 is a view showing a third modification (modification 3) of the core base material of fig. 39. The core base 245B of modification 3 is a combination of the metal layer of modification 1 and the recess of modification 2. That is, the core base 245B has a structure in which the metal layer 247 is provided on one surface and the recess 248 is formed on the other surface.

[ embodiment 12]

Fig. 44 is a cross-sectional view of the C layer 210D in the semiconductor composite device according to embodiment 12. In the C layer 210D, the capacitor part 230 has a configuration covered with 2 different insulating materials.

Referring to fig. 44, for a portion contacting the capacitor portion 230, an insulating portion 249 (first insulating member) is arranged, and an insulating portion 225 (second insulating member) is arranged so as to surround the insulating portion 249. The insulating portion 249 is made of a resin such as epoxy resin, phenol, or polyimide, or an inorganic filler such as silica or alumina, as in the insulating portion 225, and has a linear expansion coefficient different from that of the insulating portion 225.

In detail, the material of the insulating portion 249 is selected so that the difference between the linear expansion coefficient of the capacitor portion 230 and the linear expansion coefficient of the insulating portion 249 is smaller than the difference between the linear expansion coefficient of the capacitor portion 230 and the linear expansion coefficient of the insulating portion 225. The linear expansion coefficient of the insulating portion 249 is preferably set to a value between the linear expansion coefficient of the capacitor portion 230 and the linear expansion coefficient of the insulating portion 225.

In this way, by arranging the insulating portion 249 having a smaller difference in linear expansion coefficient from the capacitor portion 230 around the capacitor portion 230, stress applied to the capacitor portion 230 at the time of heat treatment in the manufacturing process is relaxed, and warpage of the C layer 210D is suppressed. This can suppress deformation and cracking of the entire package substrate.

[ embodiment 13]

Fig. 45 is a cross-sectional view of a package substrate 200L of a semiconductor composite device 10L according to embodiment 13. The package substrate 200L has a configuration similar to the package substrate 200D described in embodiment 6, and 2 package substrates 200L-1 and 200L-2 share a through hole connected to the output terminal OUT and are joined in a planar direction.

In the cross-sectional view of fig. 45, layer C of package substrates 200L-1 and 200L-2 shows via hole 222 and conductive part 220 connected to anode electrode 232. In the layer C of the package substrate 200L-1, the via hole 222 and the conductive part 220 are arranged on the mounting surface side (surface side) with respect to the capacitor part 230. On the other hand, in the layer C of the package substrate 200L-2, the via hole 222 and the conductive portion 220 are arranged on the side opposite to the mounting surface (back surface side) with respect to the capacitor portion 230. In other words, the layer C of the package substrate 200L-1 and the layer C of the package substrate 200L-2 are arranged so as to be reversed in the stacking direction.

In each of the C layers of the package substrates 200L-1 and 200L-2, the conductive members (the conductive portions 220 and the via holes 222) connected to the anode electrodes 232 are formed only on one surface side of the C layer, and thus the structure is asymmetrical in the stacking direction. Therefore, the coefficient of expansion is different between the front side and the back side of the C layer, and warping may occur in the substrate due to a temperature change during the manufacturing process.

In the package substrate 200L according to embodiment 13, the C layers are arranged to be inverted from each other in the stacking direction in the adjacent 2 package substrates 200L-1 and 200L-2. Thus, the warping direction of the package substrate 200L-1 and the warping direction of the package substrate 200L-2 are opposite to each other, and therefore, the deformation of the entire C layer is suppressed. Therefore, by adopting the C-layer structure as shown in fig. 45, warpage of the package substrate 200L can be suppressed.

[ embodiment 14]

Fig. 46 is a cross-sectional view of a package substrate 200M of a semiconductor composite device 10M according to embodiment 14. In the package substrate 200M, the C1 layer 210E and the C2 layer 210F are provided as the capacitor CP1, similarly to the package substrate 100C described in embodiment 5. In the package substrate 200M, layers of C1, 210E, C2, 210F, L and 250 are stacked in this order from the mounting surface side.

In the cross-sectional view of fig. 46, the via hole 222 and the conductive portion 220 of the anode electrode 232 connected to the C1 layer 210E and the C2 layer 210F are shown. In the C1 layer 210E, the via hole 222 and the conductive part 220 are arranged on the mounting surface side with respect to the capacitor part 230. On the other hand, in the C2 layer 210F, the via hole 222 and the conductive portion 220 are arranged on the side opposite to the mounting surface with respect to the capacitor portion 230. In other words, the C1 layer 210E and the C2 layer 210F are arranged so as to have a constitution in which they are reversed in the stacking direction.

As described in embodiment 13, in the C layer, the front side and the back side of the C layer have different coefficients of expansion, and the substrate may be warped due to a temperature change during the manufacturing process.

In the package substrate 200M according to embodiment 14, the capacitor CP1 is formed by 2C layers 210E and 210F, and the 2C layers are arranged so as to be inverted from each other in the stacking direction. Thus, the warp direction in the C layer 210E and the warp direction in the C layer 210F are opposite to each other, and therefore, the deformation of the C layer as a whole is suppressed. Therefore, by adopting the C-layer structure as shown in fig. 45, warpage of the package substrate 200M can be suppressed.

As shown in fig. 47, the C1 layer 210E and the C2 layer 210F may be stacked in reverse order.

In embodiment 14, the C1 layer 210E corresponds to the "first layer" in the present disclosure, the L layer 250 corresponds to the "second layer" in the present disclosure, and the C layer 210F corresponds to the "third layer" in the present disclosure.

In the above description of the embodiments, the configuration in which the semiconductor composite device includes the voltage regulator, the package substrate, and the load has been described, but the present invention can be applied to a semiconductor composite device including only the voltage regulator and the package substrate, and a semiconductor composite device including only the package substrate and the load, as long as the configuration of the package substrate according to the present embodiment is included.

In the above description, the arrangement of the C layer 210 and the L layer 250 has been described in the configuration in which the C layer 210 is arranged on the side closer to the mounting surface on which a load or the like is mounted, but the L layer 250 may be arranged on the side closer to the mounting surface than the C layer 210.

Each of the "through holes 266 to 268" in the present embodiment is an example of the "fourth through hole" in the present disclosure.

The embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive. The scope of the present disclosure is indicated by the claims, rather than by the description of the embodiments described above, and all changes that come within the meaning and range of equivalency of the claims are intended to be embraced therein.

Description of reference numerals:

10. 10A to 10H, 10J to 10N, 10 CA.; a voltage regulator; an active element; 120. 380.. solder bumps; 200. 200A-200H, 200J-200N, 200CA.. 205. 205A-205 e. 210. Layers 210A-210F.. C; l layers; a conductive layer; 220. a conductive portion; 222. 223, 242. 225. 249, 254. 226-229, 229A, 229B, 291-294. A capacitor portion; an anode electrode; a porous layer; a cut-out portion; a cathode electrode; 245. 245A, 245B, 280.. core substrate; 246. 247, 269A to 269c.. metal layer; a coil portion; a Cu foil; 260. 262, 264, 266, 267A, 268. 265. 296.. resin; 270. a terminal layer; a metallization layer; 295. A resist mask; a load; an electronic device; 400.. a mother substrate; a terminal; a heat sink; a capacitor; a ground terminal; IN... input terminal; an inductor; an output terminal.