阅读说明：本技术 用于垂直传输场效应晶体管的替换金属栅极工艺 (Replacement metal gate process for vertical pass field effect transistors ) 是由 李忠贤 杨振荣 鲍如强 H.贾甘纳坦 于 2018-12-31 设计创作，主要内容包括：一种形成半导体结构的方法,包括：形成设置在衬底的顶表面之上的多个鳍；以及使用替换金属栅极(RMG)工艺从该多个鳍形成一个或多个垂直传输场效应晶体管(VTFET)。围绕VTFET中的给定VTFET的至少一个鳍的栅极包括设置在栅极接触金属层之上的栅极自对准接触(SAC)帽盖层,栅极接触金属层被设置成与至少一个鳍的端部相邻。(A method of forming a semiconductor structure, comprising: forming a plurality of fins disposed over a top surface of a substrate; and forming one or more Vertical Transfer Field Effect Transistors (VTFETs) from the plurality of fins using a Replacement Metal Gate (RMG) process. A gate surrounding at least one fin of a given VTFET of the VTFETs includes a gate self-aligned contact (SAC) cap layer disposed over a gate contact metal layer disposed adjacent to an end of the at least one fin.)

1. A method of forming a semiconductor structure, comprising:

forming a plurality of fins disposed over a top surface of a substrate; and is

Forming one or more Vertical Transfer Field Effect Transistors (VTFETs) from the plurality of fins using a Replacement Metal Gate (RMG) process;

wherein a gate surrounding at least one fin of a given VTFET includes a gate self-aligned contact (SAC) cap layer disposed over a gate contact metal layer disposed adjacent to an end of the at least one fin.

2. The method of claim 1, wherein forming the one or more VTFETs comprises:

forming a bottom source/drain region disposed above the top surface of the substrate and surrounding the plurality of fins; and is

Forming bottom spacers disposed over the bottom source/drain regions.

3. The method of claim 2, wherein forming the one or more VTFETs further comprises:

forming an oxide layer disposed over the bottom spacers and sidewalls of the plurality of fins;

forming a dummy gate disposed over the oxide layer;

recessing the dummy gate below a top surface of the plurality of fins;

removing the exposed portion of the oxide layer; and is

Forming a top spacer disposed over the dummy gate and the plurality of fins.

4. The method of claim 3, wherein forming the one or more VTFETs further comprises:

forming a top junction in an upper portion of the plurality of fins;

forming an oxide layer disposed on the top spacer;

forming a liner disposed on the oxide layer; and is

An interlevel dielectric layer is formed disposed over the liner.

5. The method of claim 4, wherein forming the one or more VTFETs comprises:

forming a top source/drain opening in the inter-level dielectric layer to expose a top surface of the top junction of each of the plurality of fins;

forming a top source/drain region disposed over the top junction;

forming a top source/drain contact metal layer disposed over the top source/drain region;

recessing the top source/drain contact metal layer below a top surface of the interlevel dielectric; and is

A top source/drain SAC cap layer is formed disposed over the recessed top source/drain contact metal layer.

6. The method of claim 5, wherein forming the one or more VTFETs further comprises:

forming a gate opening in the inter-level dielectric layer to expose a portion of the top spacer disposed over the dummy gate;

depositing a liner on sidewalls of an opening of the inter-level dielectric layer;

etching the exposed portion of the top spacer to expose a portion of the dummy gate;

removing the dummy gate;

performing the replacement metal gate process to form a gate dielectric surrounding the one or more fins and to form a metal gate conductor surrounding the gate dielectric;

filling the gate contact metal layer in a remaining portion of the gate opening in the interlevel dielectric layer;

recessing the gate contact metal layer below the top surface of the interlevel dielectric layer; and is

A gate SAC cap layer is formed disposed over the recessed gate contact metal layer.

7. The method of claim 6, wherein forming the one or more VTFETs further comprises:

forming a bottom source/drain opening in the interlevel dielectric layer to expose a portion of a top surface of the bottom source/drain region;

filling a bottom source/drain contact metal layer in the bottom source/drain opening disposed over the exposed portion of the top surface of the bottom source/drain region;

recessing the bottom source/drain contact metal layer below a top surface of the interlevel dielectric layer; and is

A bottom source/drain SAC cap layer is formed disposed over the recessed bottom source/drain contact layer.

8. The method of claim 7, wherein forming the one or more VTFETs further comprises:

forming additional pads disposed over the inter-level dielectric, the top source/drain SAC cap layer, the gate SAC cap layer, and the bottom source/drain SAC cap layer;

forming an additional interlevel dielectric disposed over the additional liner;

forming vias in the additional liner, the additional inter-level dielectric, the top source/drain SAC cap layer, the gate SAC cap layer, and the bottom source/drain SAC cap layer to expose portions of top surfaces of the top source/drain contact metal layer, the gate contact metal layer, and the bottom source/drain contact metal layer; and is

Forming a top source/drain contact, a gate contact, and a bottom source/drain contact in the via.

9. The method of claim 3, wherein forming the one or more VTFETs further comprises: forming at least one shallow trench isolation region in the substrate and the bottom source/drain region between a first subset of the plurality of fins and at least a second subset of the plurality of fins, wherein recessing the dummy gate comprises:

recessing a first portion of the dummy gate around the first subset of the plurality of fins to a first depth; and is

Recessing a second portion of the dummy gate around the second subset of the plurality of fins to a second depth that is greater than the first depth;

wherein the first subset of the plurality of fins forms a VTFET having a first channel length; and is

Wherein the second subset of the plurality of fins forms a VTFET having a second channel length that is less than the first channel length.

10. The method of claim 9, wherein recessing the first portion of the dummy gate and recessing the second portion of the dummy gate comprises:

patterning a mask layer over the dummy gate to expose a top surface of the dummy gate disposed over the at least one shallow trench isolation region;

removing the exposed portion of the dummy gate to expose a portion of the bottom spacer disposed over the at least one shallow trench isolation region; and is

A liner is formed on exposed sidewalls of the dummy gate.

11. The method of claim 3, wherein the dummy gate comprises a shared dummy gate surrounding pairs of the plurality of fins, each pair of the plurality of fins comprising:

a first fin forming a channel for one of a p-type field effect transistor (PFET) of a given Complementary Metal Oxide Semiconductor (CMOS) device and an n-type field effect transistor (NFET) of the given CMOS device; and is

A second fin forming a channel for the other of the PFET and the NFET of the given CMOS device.

12. The method of claim 11, wherein forming the one or more VTFETs further comprises:

patterning a gate opening in an interlevel dielectric layer over a top spacer disposed over the shared dummy gate;

removing a portion of the inter-level dielectric layer to expose a portion of the top surface of the top spacer;

forming a liner on exposed sidewalls of the interlevel dielectric layer in the gate opening; and is

Removing the shared dummy gate.

13. The method of claim 12, wherein forming the one or more VTFETs further comprises:

forming a gate dielectric surrounding the first fin and the second fin;

forming a first gate conductor layer surrounding the gate dielectric, the top surface of the substrate, and the liner disposed on the exposed sidewalls of the inter-level dielectric layer;

blocking a first portion of the gate opening and the first gate conductor layer surrounding the first fin with an organic polymer layer;

removing the first gate conductor layer surrounding the second fin exposed by the organic polymer layer;

removing the organic polymer layer; and is

A second gate conductor layer is formed surrounding the gate dielectric surrounding the second fin.

14. The method of claim 13, further comprising:

filling the gate contact metal layer in the gate opening contacting the first gate conductor layer and the second gate conductor layer;

recessing the gate contact metal layer below a top surface of the interlevel dielectric; and is

A gate SAC cap layer is formed disposed over the recessed gate contact metal layer.

15. A semiconductor structure, comprising:

a substrate; and is

A plurality of fins disposed over a top surface of the substrate, the plurality of fins comprising channels for one or more Vertical Transfer Field Effect Transistors (VTFETs) formed using a Replacement Metal Gate (RMG) process;

wherein a given VTFET of the VTFETs includes a gate surrounding at least one fin of the plurality of fins, the gate of the given VTFET including a gate self-aligned contact (SAC) cap layer disposed over a gate contact metal layer disposed adjacent to an end of the at least one fin.

16. The semiconductor structure of claim 15, further comprising:

a bottom source/drain region disposed above the top surface of the substrate around the plurality of fins;

a bottom spacer disposed over the bottom source/drain region;

the gate surrounding the plurality of fins;

a top spacer disposed over the gate;

a top source/drain region disposed on a portion of the top spacer disposed over each fin of the plurality of fins;

a top source/drain contact metal layer disposed over the top source/drain region;

a top source/drain SAC cap layer disposed over the top source/drain metal contact layer;

a bottom source/drain contact metal layer disposed over a portion of the bottom source/drain region; and is

A bottom source/drain SAC cap layer disposed over the bottom source/drain metal contact layer.

17. The semiconductor structure of claim 16, wherein at least two fins of the plurality of fins have different heights.

18. The semiconductor structure of claim 16, wherein the gate of the given VTFET comprises a shared gate surrounding pairs of the plurality of fins, each pair of the plurality of fins comprising:

a first fin forming a channel for one of a p-type field effect transistor (PFET) of a given Complementary Metal Oxide Semiconductor (CMOS) device and an n-type field effect transistor (NFET) of the given CMOS device; and is

A second fin forming a channel for the other of the PFET and the NFET of the given CMOS device.

19. The semiconductor structure of claim 18, wherein the shared gate comprises a first gate conductor surrounding the first fin and a second gate conductor surrounding the second fin, the gate contact metal layer contacting the first and second gate conductors.

20. An integrated circuit comprising the semiconductor structure of any one of claims 15 to 19.

Background

The present invention relates to semiconductors, and more particularly to techniques for forming semiconductor structures. Semiconductor and integrated circuit chips have become ubiquitous in many products, particularly because of their continued reduction in cost and size. There is a continuing desire to reduce the size of structural features and/or to provide a greater number of structural features for a given chip size. In general, miniaturization allows increased performance at lower power levels and lower cost. Current technology is at or near the atomic scale of certain micro devices such as logic gates, Field Effect Transistors (FETs), and capacitors.

Disclosure of Invention

Embodiments of the invention provide techniques for Replacement Metal Gate (RMG) processes for Vertical Transfer Field Effect Transistors (VTFETs).

In one embodiment of the present invention, a method of forming a semiconductor structure comprises: forming a plurality of fins of the inventive arrangement over a top surface of a substrate; and forming one or more VTFETs from the plurality of fins using an RMG process. A gate surrounding at least one fin of a given VTFET of the VTFETs includes a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer disposed adjacent to an end of the at least one fin.

In another embodiment of the present invention, a semiconductor structure includes a substrate and a plurality of fins disposed over a top surface of the substrate, the plurality of fins including a channel for one or more VTFETs formed using an RMG process. A given VTFET of the VTFETs includes a gate surrounding at least one fin of the plurality of fins, the gate of the given VTFET including a gate SAC cap layer disposed over a gate contact metal layer disposed adjacent an end of the at least one fin.

In another embodiment of the invention, an integrated circuit includes one or more VTFETs including a substrate and a plurality of fins disposed above a top surface of the substrate, the plurality of fins including a channel for the one or more VTFETs formed using an RMG process. A given VTFET of the VTFETs includes a gate surrounding at least one fin of the plurality of fins, the gate of the given VTFET including a gate SAC cap layer disposed over a gate contact metal layer disposed adjacent an end of the at least one fin.

Drawings

Fig. 1 illustrates a side cross-sectional view of a semiconductor structure having a plurality of fins disposed over a substrate, in accordance with an embodiment of the present invention.

Fig. 2 illustrates a side cross-sectional view of the semiconductor structure of fig. 1 after forming bottom source/drain regions and bottom spacers (spacers) in accordance with an embodiment of the present invention.

Fig. 3 illustrates a side cross-sectional view of the semiconductor structure of fig. 2 after forming a dummy gate in accordance with an embodiment of the present invention.

Fig. 4 illustrates a side cross-sectional view of the semiconductor structure of fig. 3 after a recess of the dummy gate in accordance with an embodiment of the present invention.

Fig. 5 illustrates a side cross-sectional view of the semiconductor structure of fig. 4 after forming top spacers, in accordance with an embodiment of the present invention.

FIG. 6 illustrates a side cross-sectional view of the semiconductor structure of FIG. 5 after forming and activating a top junction, in accordance with an embodiment of the present invention.

Fig. 7 illustrates a side cross-sectional view of the semiconductor structure of fig. 6 after filling the isolation layer, in accordance with an embodiment of the present invention.

Fig. 8 illustrates a side cross-sectional view of the semiconductor structure of fig. 7 after forming additional spacers and an interlevel dielectric (interlevel dielectric) in accordance with an embodiment of the present invention.

FIG. 9 illustrates a side cross-sectional view of the semiconductor structure of FIG. 8 after opening to expose the top of the junction for forming the top source/drain contacts in accordance with an embodiment of the present invention.

FIG. 10 illustrates a side cross-sectional view of the semiconductor structure of FIG. 9 after forming top source/drains, in accordance with an embodiment of the present invention.

FIG. 11 illustrates a side cross-sectional view of the semiconductor structure of FIG. 10 after filling a metal layer over the top source/drain regions in accordance with an embodiment of the present invention.

FIG. 12 illustrates a side cross-sectional view of the semiconductor structure of FIG. 11 after a metal layer is recessed and a top source/drain self-aligned contact cap layer is formed, in accordance with an embodiment of the present invention.

FIG. 13 illustrates another side cross-sectional view of the semiconductor structure of FIG. 11 after forming a top source/drain self-aligned contact cap layer in accordance with an embodiment of the present invention.

Fig. 14 illustrates a side cross-sectional view of the semiconductor structure of fig. 12 and 13 after masking to open the dummy gate, in accordance with an embodiment of the present invention.

FIG. 15 illustrates a side cross-sectional view of the semiconductor structure of FIG. 14 after forming a liner on sidewalls of the gate opening in accordance with an embodiment of the present invention.

Fig. 16 illustrates a side cross-sectional view of the semiconductor structure of fig. 15 after removal of the dummy gate, in accordance with an embodiment of the present invention.

FIG. 17 illustrates a side cross-sectional view of the semiconductor structure of FIG. 16 after a replacement metal gate process, in accordance with an embodiment of the present invention.

Fig. 18 illustrates a side cross-sectional view of the semiconductor structure of fig. 17 after filling the gate opening with metal, in accordance with an embodiment of the present invention.

FIG. 19 illustrates a side cross-sectional view of the semiconductor structure of FIG. 18 after recess of metal in the gate opening and formation of a gate self-aligned contact cap layer, in accordance with an embodiment of the present invention.

FIG. 20 illustrates a side cross-sectional view of the semiconductor structure of FIG. 19 after masking to open the bottom source/drain regions, in accordance with an embodiment of the present invention.

FIG. 21 illustrates a side cross-sectional view of the semiconductor structure of FIG. 20 after filling the openings to the bottom source/drain regions with metal and forming a bottom source/drain self-aligned contact cap layer, in accordance with an embodiment of the present invention.

FIG. 22 illustrates a side cross-sectional view of the semiconductor structure of FIG. 21 after forming a liner and an interlevel dielectric, in accordance with an embodiment of the present invention.

Fig. 23 illustrates a side cross-sectional view of the semiconductor structure of fig. 22 after forming a via (via) for access contact in accordance with an embodiment of the present invention.

FIG. 24 illustrates a top view of the semiconductor structure of FIG. 23, in accordance with an embodiment of the present invention.

Fig. 25 illustrates a side cross-sectional view of a semiconductor structure including a fin in a long channel region and a short channel region, in accordance with an embodiment of the present invention.

Fig. 26 illustrates a side cross-sectional view of the semiconductor structure of fig. 25 after dummy gate patterning in accordance with an embodiment of the present invention.

FIG. 27 illustrates a side cross-sectional view of the semiconductor structure of FIG. 26 after forming a liner in accordance with an embodiment of the present invention.

Fig. 28 illustrates a side cross-sectional view of the semiconductor structure of fig. 27 after recess of the dummy gate, in accordance with an embodiment of the present invention.

Fig. 29 illustrates a side cross-sectional view of the semiconductor structure of fig. 28 after forming top spacers, in accordance with an embodiment of the present invention.

FIG. 30 illustrates a side cross-sectional view of the semiconductor structure of FIG. 29 after forming a top junction, in accordance with an embodiment of the present invention.

Fig. 31 illustrates a side cross-sectional view of the semiconductor structure of fig. 30 after filling with an isolation layer and forming additional spacers and an interlevel dielectric, in accordance with an embodiment of the present invention.

FIG. 32 illustrates a side cross-sectional view of the semiconductor structure of FIG. 31 after opening to expose the top of the junction for forming the top source/drain contacts in accordance with an embodiment of the present invention.

FIG. 33 illustrates a side cross-sectional view of the semiconductor structure of FIG. 32 after forming top source/drain regions and filling with a metal layer, in accordance with an embodiment of the present invention.

FIG. 34 illustrates a side cross-sectional view of the semiconductor structure of FIG. 33 after the metal layer is recessed and a top source/drain region self-aligned contact cap layer is formed, in accordance with an embodiment of the present invention.

Figure 35 illustrates a side cross-sectional view of a semiconductor structure with a shared dummy gate in accordance with an embodiment of the present invention.

Fig. 36 illustrates a side cross-sectional view of the semiconductor structure of fig. 35 after opening the shared dummy gate in accordance with an embodiment of the present invention.

FIG. 37 illustrates a side cross-sectional view of the semiconductor structure of FIG. 36 after forming a liner in accordance with an embodiment of the present invention.

Fig. 38 illustrates a side cross-sectional view of the semiconductor structure of fig. 37 after removal of the shared dummy gate, in accordance with an embodiment of the present invention.

Fig. 39 illustrates a side cross-sectional view of the semiconductor structure of fig. 38 after forming a work function metal for a p-type field effect transistor, in accordance with an embodiment of the present invention.

Fig. 40 illustrates a side cross-sectional view of the semiconductor structure of fig. 39 after patterning a p-type workfunction metal, in accordance with an embodiment of the present invention.

Fig. 41 illustrates a side cross-sectional view of the semiconductor structure of fig. 40 after forming a work function metal for an n-type field effect transistor, in accordance with an embodiment of the present invention.

FIG. 42 illustrates a side cross-sectional view of the semiconductor structure of FIG. 41 after filling with a metal, in accordance with an embodiment of the present invention.

FIG. 43 illustrates a side cross-sectional view of the semiconductor structure of FIG. 42 after recess of metal and formation of a gate self-aligned contact cap layer, in accordance with an embodiment of the present invention.

FIG. 44 illustrates a side cross-sectional view of the semiconductor structure of FIG. 43 after forming a via for accessing a contact in accordance with an embodiment of the present invention.

FIG. 45 illustrates a top view of the semiconductor structure of FIG. 44, in accordance with an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present invention may be described herein in the context of exemplary methods for replacement metal gate processes for vertical pass field effect transistors, and exemplary devices, systems, and devices formed using such methods. It should be understood, however, that embodiments of the present invention are not limited to the example methods, apparatus, systems and devices, but are instead more generally applicable to other suitable methods, apparatus, systems and devices.

A Field Effect Transistor (FET) is a transistor having a source, a gate and a drain and having an effect that depends on the flow of carriers (electrons or holes) along a channel extending between the source and the drain. The current through the channel between the source and drain can be controlled by the lateral electric field under the gate.

FETs are widely used for switching, amplification, filtering and other tasks. The FET includes a Metal Oxide Semiconductor (MOS) FET (MOSFET). Complementary mos (cmos) devices are widely used, in which both n-type and p-type transistors (NFETs and PFETs) are used to fabricate logic and other circuits. The source and drain regions of a FET are typically formed by adding dopants to a target region of the semiconductor body on either side of a channel over which the gate is formed. The gate includes a gate dielectric over the channel and a gate conductor over the gate dielectric. The gate dielectric is an insulator material that prevents large leakage currents from flowing into the channel when a voltage is applied to the gate conductor, while allowing the applied gate voltage to generate a lateral electric field in the channel.

The increasing demand for high density and performance of integrated circuit devices requires the development of new structural and design features, including shrinking gate lengths and other size reductions or scaling of the devices. However, continued scaling is reaching the limits of conventional fabrication techniques.

The vertical FET process flow has severe constraints on the thermal budget for downstream processing steps, such as top source/drain epitaxial growth and dopant activation annealing processes, because the high-k metal gate (HKMG) module is formed earlier in the process. The channel length (lgate) is highly dependent on the metal gate recess process, which results in large chip variations in the lgate. High temperature processes (e.g., greater than 550 degrees celsius (c)) for top source/drain modules cause threshold voltage (Vt) shift, increase in inversion thickness (Tinv), and degradation in leakage current metric (Toxgl) due to diffusion of oxygen and metal into the channel. Thus, a Replacement Metal Gate (RMG) process flow for vertical transfer fets (vtfets) is needed.

Embodiments of the invention provide techniques for forming VTFET devices with RMG processes that eliminate the limitations of the thermal budget of the gate stack. The RMG process disclosed herein provides precise L-gate definition and self-aligned top junctions. In addition to providing techniques for forming VTFETs with RMG processes, embodiments allow for the formation of VTFETs with multiple channel lengths, self-aligned gate cap formation to avoid gate-to-source/drain region shorts, and CMOS patterning with negligible n/p boundary shifts.

An exemplary process for forming VTFETs, including VTFET and CMOS VTFET devices having multiple channel lengths, using an RMG process will now be described with reference to fig. 1-45.

Fig. 1 illustrates a side cross-sectional view 100 of a semiconductor structure including a substrate 102 having a plurality of fins 101 formed in the substrate 102. As shown, each of the fins 101 is covered by a hard mask 104. The fins 101 may be formed using Sidewall Image Transfer (SIT) or other suitable techniques, such as photolithography and etching including Reactive Ion Etching (RIE) and the like. Each of the fins 101 may have a width or horizontal thickness (in direction X-X ") in the range of 5 nanometers (nm) to 10nm, although other widths above or below this range may be used as desired for a particular application. Each of the fins 101 may have a height or vertical thickness (in direction Y-Y ") ranging from 30nm to 150nm, although other heights above or below this range may be used as desired for a particular application. The spacing between adjacent ones of the fins 101 may be in the range of 20nm to 100nm, but other spacings may be used as desired for a particular application.

In some embodiments of the present invention, substrate 102 comprises a semiconductor substrate formed of silicon (Si), although other suitable materials may be used. For example, the substrate 102 may include any suitable substrate structure, such as a bulk semiconductor. The substrate 102 may comprise a silicon-containing material. Illustrative examples of suitable Si-containing materials for substrate 102 may include, but are not limited to, Si, silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), and multilayers thereof. Although silicon is the semiconductor material primarily used in wafer fabrication, alternative semiconductor materials may be used as additional layers, such as, but not limited to, germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), SiGe, cadmium telluride (CdTe), zinc selenide (ZnSe), and the like. The fin 101 is formed by patterning the substrate 102 as described above, and thus the fin 101 may be formed of the same material as the substrate 102.

The substrate 102 may have a width or horizontal thickness (X-X ") that is selected as desired based on the number of fins 101 or other features to be formed thereon. The substrate 102 may have a height or vertical thickness (in the direction Y-Y ") in the range of 20nm to 500nm, although other heights above or below this range may also be used as desired for a particular application.

The hard mask 104 may be initially formed over the top surface of the entire substrate, followed by patterning using SIT or other suitable techniques, wherein the fin 101 is formed by etching the portion of the substrate exposed by the patterned hard mask 104. The hard mask 104 may be formed of silicon nitride (SiN), but other suitable materials may be used, such as silicon oxide (SiOX), silicon dioxide (SiO2), and silicon oxynitride (SiON). The hard mask 104 may have a height or vertical thickness (in the direction Y-Y ") in the range of 20nm to 100nm, although other heights above or below this range may also be used as desired for a particular application.

Fig. 2 shows a side cross-sectional view 200 of the semiconductor structure of fig. 1 after forming a bottom source/drain region 106 around the fin 101 over the top surface of the substrate 102 and forming a bottom spacer 108 around the fin 101 over the bottom source/drain region 106.

The bottom source/drain regions 106 may be appropriately doped, for example, using ion implantation, gas phase doping, plasma immersion ion implantation, cluster doping, implant doping, liquid phase doping, solid phase doping, and the like. The n-type dopant may be selected from the group of phosphorus (P), arsenic (As), and antimony (Sb), and the P-type dopant may be selected from the group of boron (B), boron fluoride (BF2), gallium (Ga), indium (In), and thallium (T1). The bottom source/drain regions 106 may be formed by an epitaxial growth process. In some embodiments, the epitaxial process includes in-situ doping (incorporation of dopants into the epitaxial material during epitaxy). The epitaxial material may be grown from gaseous or liquid precursors. Epitaxial materials may be grown using Vapor Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), Liquid Phase Epitaxy (LPE), Rapid Thermal Chemical Vapor Deposition (RTCVD), metalorganic chemical vapor deposition (MOCVD), ultra-high vacuum chemical vapor deposition (UHVCVD), Low Pressure Chemical Vapor Deposition (LPCVD), limited reaction processing cvd (lrpcvd), or other suitable processes. Epitaxial silicon, silicon germanium (SiGe), germanium (Ge), and/or carbon doped silicon (Si: C) silicon may be doped (in-situ doping) during deposition by adding dopants, such as n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor. The dopant concentration in the source/drain may range from 1x1019cm-3 to 3x1021cm-3, or preferably between 2x1020cm-3 to 3x1021 cm-3.

The bottom source/drain region 106 may have a height or vertical thickness (in the direction Y-Y ") in the range of 10nm to 50nm, although other heights above or below this range may also be used as desired for a particular application.

Bottom spacers 108 are formed over bottom source/drain regions 106 using a non-conformal deposition and etch-back process (e.g., Physical Vapor Deposition (PVD), High Density Plasma (HDP) deposition, etc.). The bottom spacer 108 may be formed of SiO2, SiN, silicon carbide oxide (SiCO), silicon carbide boron nitride (SiBCN), or the like, although other suitable materials may be used. The bottom spacers 108 may have a height or vertical thickness (in direction Y-Y ") in the range of 3nm to 10nm, although other heights above or below this range may also be used as desired for a particular application.

Fig. 3 illustrates a side cross-sectional view 300 of the semiconductor structure of fig. 2 after dummy gate formation. The dummy gate formation includes forming an oxide 110 over the top surface of the bottom spacers 108 and on the sidewalls of the fin 101 and the hard mask 104. The oxide 110 may be formed by a conformal deposition process, such as Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD). The oxide 110 may be formed of SiO2, SiON, etc., although other suitable materials may be used. The oxide 110 may have a uniform thickness in the range of 2nm to 6nm, but other thicknesses above or below this range may be used as desired for a particular application.

A dummy gate 112 is formed over the oxide 110 using a process such as CVD or ALD. The dummy gate 112 may be formed of amorphous silicon (a-Si), amorphous silicon germanium (a-SiGe), SiO2, titanium oxide (TiO2), or another suitable material.

Fig. 4 illustrates a side cross-sectional view 400 of the semiconductor structure of fig. 3 after recessing of the dummy gate 112 and removal of the exposed portions of the oxide 110 on the sidewalls of the fin 101 and the hard mask 104 disposed over the fin 101. The dummy gate 112 and oxide 110 may be recessed using a process such as wet etching, RIE, or the like. The dummy gate 112 and oxide 110 may be recessed by a depth (in direction Y-Y ") in the range of 5nm to 20nm, although other depths may be used as long as at least a portion of the sidewalls of the fin 101 under the hard mask 104 is exposed.

Fig. 5 illustrates a side cross-sectional view 500 of the semiconductor structure of fig. 4 after removing the hard mask 104 and forming the top spacers 114. The hard mask 104 may be removed using a selective dry or wet etch process. The top spacers 114 may be formed using conformal deposition, such as an ALD or CVD process. The top spacers 114 may be formed of SiN, SiO2, or other suitable materials such as SiON, SiOC, SiBCN, or the like. The top spacer 114 may have a uniform thickness in the range of 3nm to 10nm, although other thicknesses above or below this range may also be used as desired for a particular application.

Fig. 6 illustrates a side cross-sectional view 600 of the semiconductor structure of fig. 5 after forming and activating the top junction 116. Ion implantation, plasma doping, or another suitable process is used to form a top junction 116 (e.g., a heavily doped region) at the top of the fin 101. The top junction 116 may use a dopant including an n-type dopant selected from the group of phosphorus (P), arsenic (As), and antimony (Sb) and a P-type dopant selected from the group of boron (B), boron fluoride (BF2), gallium (Ga), indium (In), and thallium (T1). The height of the top junction 116 extends in the region of the fin below the bottom surface of the top spacer 114. The top junction 116 may have a height or vertical thickness (in the direction Y-Y ") in the range of 5nm to 20nm, although other heights above or below this range may also be used as desired for a particular application.

Fig. 7 illustrates a side cross-sectional view 700 of the semiconductor structure of fig. 6 after filling with an isolation or interlevel dielectric (ILD) layer 118. The isolation layer 118 may be formed of SiO2 or another suitable material (such as SiOC, SiON, etc.). The isolation layer 118 may be formed by filling with an isolation material, followed by planarization to the top surface of the top spacers 114 using chemical mechanical polishing or planarization (CMP).

Fig. 8 illustrates a side cross-sectional view 800 of the semiconductor structure of fig. 7 after forming spacers 120 and ILD layer 122. The spacers 120 may be formed of SiN, although other suitable materials such as SiO2, SiON, SiBCN, SiCO, etc. may also be used. The spacers 120 may have a height or vertical thickness (in the direction Y-Y ") in the range of 5nm to 15nm, although other heights above or below this range may be used as desired for a particular application. The spacers 120 may be formed using a conformal deposition process, such as ALD or CVD.

ILD122 may be formed of SiO2, but other suitable materials such as SiON, SiCO, etc. may also be used. ILD122 may be formed using a CVD or ALD process. The ILD122 may have a height or vertical thickness (in the direction Y-Y ") in the range of 30nm to 150nm, although other heights above or below this range may be used as desired for a particular application.

Fig. 9 illustrates a side cross-sectional view 900 of the semiconductor structure of fig. 8 after opening to expose the top of the junction 116 for forming top source/drain contacts. A masking layer 124 is patterned over the top surface of ILD122 using photolithography and etching or other suitable techniques. The mask layer 124 may be formed of a suitable combination of organic materials, SiO2, titanium oxide (TiOx), but other suitable materials may be used. The mask layer 124 may have a height or vertical thickness (in the direction Y-Y ") in the range of 30nm to 150nm, although other heights above or below this range may be used as desired for a particular application.

The mask layer 124 is patterned to provide an opening over the top of the fin 101. The top of the opening over fin 101 is wider than fin 101, such as having a width 901 in the range of 20nm to 80nm, with width 901 narrowing to a width that substantially matches the width of fin 101 as the distance from the top surface of fin 101 decreases. The openings in the ILD122 may be formed by directional RIE or other suitable processing.

Fig. 10 illustrates a side cross-sectional view 1000 of the semiconductor structure of fig. 9 after top source/drain formation. The mask layer 124 is removed using a process such as plasma ashing/removal. To assist the epitaxial growth, a lateral etch of the material of spacers 114 and 120 may optionally be performed. After the optional lateral etch, a top source/drain region 126 is epitaxially grown over the junction 116 (and in the areas exposed by the optional lateral etch of spacers 114 and 120). The top source/drain region 126 may have a height or vertical thickness in the range of 10nm to 50nm (in the direction Y-Y "), although other heights above or below this range may be used as desired for a particular application. The top source/drain regions 126 may be formed of a similar material as the bottom source/drain regions 106.

Fig. 11 illustrates a side cross-sectional view 1100 of the semiconductor structure of fig. 10 after filling with a metal to form a metal layer 128 over the top source/drain region 126. The metal layer 128 (also referred to as a top source/drain contact metal layer) may be formed of tungsten (W), but other suitable materials such as titanium (Ti), cobalt (Co), etc. may also be used. Metal layer 108 may be formed by filling with a metal material and then planarizing using CMP or another suitable technique to make the top surface of metal layer 128 substantially coplanar with the top surface of ILD 122.

Fig. 12 shows a side cross-sectional view 1200 of the semiconductor structure of fig. 11 after recessing of metal layer 128 and forming a self-aligned contact (SAC) cap layer 130 (also referred to as a top source/drain SAC cap layer) over the top surface of metal layer 128. A wet or dry etch process may be used to recess the metal layer 128. SAC cap layer 130 may be formed using an ALD or CVD process. The metal layer 128 may be recessed to a depth in the range of 5nm to 20nm, although other depths outside this range may be used as desired for a particular application. SAC cap layer 130 may have a height or thickness (in direction Y-Y ") that matches the depth of the recess of metal layer 128 such that SAC cap layer 130 has a top surface that matches the top surface of ILD 122.

FIG. 13 illustrates another side cross-sectional view 1300 of the semiconductor structure of FIG. 11 after forming a SAC cap layer 130. The side cross-sectional view 1200 of fig. 12 (and the side cross-sectional views of fig. 1-11) is taken perpendicular to the fin 101, while the side cross-sectional view 1300 is taken parallel to the fin 101. One of the fins 101 is shown in dashed outline in side cross-sectional view 1300, indicating that it is "behind" dummy gate 112 in this view. The side cross-sectional view 1300 also shows a Shallow Trench Isolation (STI) region 103 formed as shown. STI regions 103 may be formed of similar materials as insulating layer 118 and ILD 122.

Fig. 14 illustrates a side cross-sectional view 1400 of the semiconductor structure of fig. 12 and 13 after masking to open the dummy gate 112. Similar to side cross-sectional view 1300, side cross-sectional view 1400 is taken parallel to fin 101. A mask layer 132 is patterned over the top surfaces of ILD122 and SAC cap layer 130. Mask layer 132 may be formed with similar materials and dimensions as mask layer 124. The SAC cap layer 130 ensures that there will be no short between the top source/drain region 126 and the gate. The mask layer 132 may be patterned as shown to open the dummy gate 112 because the SAC cap layer 130 over the top source/drain regions 126 is not incorporated due to the definition of the epitaxial layer. The opening exposing dummy gate 112 may have a width 1401 of 75nm or more generally in the range of 30nm to 100nm, although other widths outside this range may be used as desired for a particular application.

Fig. 15 shows a side cross-sectional view 1500 of the semiconductor structure of fig. 14 after deposition of a liner 134 on the sidewalls of the gate opening and after a directional etch to expose the top surface of dummy gate 112 in the gate opening. The liner 134 may be formed of a material similar to that of the bottom and top spacers 108, 114 (e.g., SiN), although other suitable materials may be used. The liner 134 may have a thickness in the range of 3nm to 10nm, although other thicknesses outside this range may be used as desired for a particular application. The directional etch exposing the top surface of the dummy gate 112 may be a directional RIE.

Fig. 16 illustrates a side cross-sectional view 1600 of the semiconductor structure of fig. 15 after removal of the dummy gate 112. The mask layer 132 is removed prior to removing the dummy gate 112. The dummy gate 112 may be removed using a vapor etch, a wet etch, or other suitable process to selectively remove the dummy gate 112 on the oxide layer 110, which protects the fin 101 during removal of the dummy gate 112. Prior to the Replacement Metal Gate (RMG) process described in further detail below, the oxide layer 110 covering the fin 101 is removed, for example using a diluted HF etch. After removing the dummy gate 112 and the oxide layer 110 covering the fins 101, the fins 101 are seen behind the dummy gate 112, as shown.

Fig. 17 illustrates a side cross-sectional view 1700 of the semiconductor structure of fig. 16 after an RMG process, wherein a gate dielectric (not shown) is formed around the fin 101, followed by the formation of the gate conductor 136.

The gate dielectric may be formed of a high-k dielectric material, although other suitable materials may be used. Examples of high-k materials include, but are not limited to, metal oxides such as hafnium oxide (HfO2), hafnium silicon oxide (Hf-Si-O), hafnium silicon oxynitride (HfSiON), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl03), zirconium oxide (ZrO2), zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide, and lead zinc niobate. The high-k material may further include dopants such as lanthanum (La), aluminum (a1), and magnesium (Mg). The gate dielectric may have a uniform thickness in the range of 2nm to 5nm, but other thicknesses above or below this range may be used as desired for a particular application.

The gate conductor 136 may be formed of any suitable conductive material, including, but not limited to, metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), zirconium (Zr), cobalt (Co), copper (Cu), aluminum (a1), lead (Pb), platinum (Pt), TiN (Sn), silver (Ag), gold (Au), etc.), conductive metal compound materials (e.g., tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaCX), titanium carbide (TiC), titanium aluminum carbide, tungsten silicide (WSi2), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silicide, nickel silicide, etc.), or any suitable combination of these and other suitable materials. The conductive material may further comprise a dopant incorporated during or after deposition. In some embodiments, the gate conductor includes a workfunction metal (WFM) layer for setting the threshold voltage of the vertical transistor to a desired value. The WFM may be: nitrides, including but not limited to titanium nitride (TiN), titanium aluminum nitride (TiAlN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN); carbides, including but not limited to titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), hafnium carbide (HfC); and combinations thereof.

The gate conductor 136 fills the area around the fin 101, as shown, and the thickness on the sidewalls of the spacers and around the gate opening is in the range of 3nm to 10nm, although other thicknesses outside this range may also be used as desired for a particular application.

The gate dielectric and gate conductor 136 are formed using an RMG process, as described above. The gate dielectric film and the gate conductor 136 may be formed by a suitable deposition process such as CVD, Plasma Enhanced Chemical Vapor Deposition (PECVD), ALD, evaporation, PVD, chemical solution deposition, or other similar processes. The thickness of the gate dielectric and gate conductor 136 may vary depending on the deposition process and the composition and amount of gate dielectric material used.

Fig. 18 illustrates a side cross-sectional view 1800 of the semiconductor structure of fig. 17 after filling the gate opening as shown with a metal layer 138 (also referred to as a gate contact metal layer). Metal layer 138 may be planarized using CMP or other suitable process to have a surface that is substantially coplanar with the top surface of ILD 122. Metal layer 138 may be formed of a material similar to that of metal layer 128.

FIG. 19 shows a side cross-sectional view 1900 of the semiconductor structure of FIG. 18 after recessing of metal layer 138 and formation of a SAC cap layer 140 (also referred to as a gate SAC cap layer). SAC cap layer 140 may be formed of similar materials and have similar thicknesses as SAC cap layer 130. Metal layer 138 may be recessed using a process similar to that used for the recess of metal layer 128.

Fig. 20 illustrates a side cross-sectional view 2000 of the semiconductor structure of fig. 19 after patterning the mask layer 142 and forming openings to the bottom source/drain regions 106. Mask layer 142 may be formed with materials and dimensions similar to those described above with respect to mask layer 124. The opening to the bottom source/drain region 106 may be formed by directional RIE or other suitable process.

Fig. 21 shows a side cross-sectional view 2100 of the semiconductor structure of fig. 20 after filling the opening to the bottom source/drain region 106 with a metal layer 144 (also referred to as a bottom source/drain contact metal layer). Fig. 21 also shows the recessing of metal layer 144 and the formation of SAC cap layer 146 (also referred to as a bottom source/drain cap layer). Metal layer 144 may be formed of a similar material and using a similar process as metal layers 128 and 138. SAC cap layer 146 may be formed of similar materials and similar dimensions using processes similar to those described with respect to the formation of SAC cap layers 130 and 140.

Fig. 22 illustrates a side cross-sectional view 2200 of the semiconductor structure of fig. 21 after forming spacers 148 and ILD 150. The spacer 148 may be formed of a similar material as the top spacer 114 and the SAC cap layers 130, 140, and 146. The spacers 148 have a height or vertical thickness (in the direction Y-Y ") that may be in the range of 5nm to 20nm, although other thicknesses outside this range may also be used as desired for a particular application. ILD 150 may be formed of a similar material as ILD 122. ILD 150 has a height or vertical thickness (in direction Y-Y ") in the range of 30nm to 150nm, other thicknesses outside this range may also be used as desired for a particular application.

FIG. 23 shows a side cross-sectional view 2300 of the semiconductor structure of FIG. 22 after forming vias 152, 154, and 156, vias 152, 154, and 156 providing access (via metal layers 128, 138, and 144, respectively) to contacts to bottom source/drain region 106, top source/drain region 126, and gate conductor 136, respectively. Vias 152, 154, and 156 may be formed using a conformal deposition process, such as CVD or ALD, and vias 152, 154, and 156 may each have a width or horizontal thickness (in direction X-X ") at their top surface in the range of 20nm to 100nm, although other widths outside this range may be used as desired for a particular application. It should also be understood that vias 152, 154, and 156 may have different widths.

Fig. 24 illustrates a top view 2400 of the semiconductor structure of fig. 23. It should be noted that top view 2400 is presented to illustrate the location of vias 152, 154, and 156 relative to fin 101, and thus the different details of the underlying layers are omitted for clarity of illustration. The bottom source/drain contact vias 152 may have a thickness (in the direction Y-Y') of 30nm or more generally in the range of 20nm to 100nm, although other suitable thicknesses may be used as desired for a particular application. Each of the fins 101 may have a length (in direction Y-Y ") of 45nm, or more generally in the range of 10nm to 200nm, although other suitable lengths may be used as desired for a particular application. As shown, the top source/drain contact 154 may have a length matching the length of the fin 101, but this is not required. The gate contact via 156 may have a thickness (in the direction Y-Y ") of 20nm, or more generally in the range of 15nm to 100nm, although other suitable thicknesses may be used as desired for a particular application.

Top view 2400 shows mask regions 2401, 2403 and 2405 of the semiconductor structure. Mask region 2401 shows where bottom source/drains 106 are formed. Mask region 2403 shows where the gate is formed. The mask region 2405 shows where an opening is formed that exposes the dummy gate 112.

The RMG scheme for vertical transistors requires removal of the dummy gate through the gate contact opening 156 and deposition of the gate dielectric and gate conductor. Because there is a high risk of gate-to-source/drain region shorts due to process variations of lithography and etching, the gate contact opening should be placed away from the top source/drain region. The distance between the fin 101 and the gate contact opening 156 is typically in the range of 20nm to 100nm, which makes it difficult to remove the dummy gate and deposit the gate dielectric and gate conductor. However, in exemplary embodiments, the SAC cap layer formed on top of the openings to the top and bottom source/drain regions advantageously enables RMG processes without size limitations and gate-to-top source/drain shorts.

As described above, the side cross-sectional views of fig. 1-12 are taken perpendicular to the length of fin 101 (such as along line a-a in top view 2400 of fig. 24). The side cross-sectional views of fig. 13-23 are taken parallel to the length of fin 101 (such as along line B-B in top view 2400 of fig. 24).

In some embodiments, the RMG process may be used to form a plurality of different channel lengths for VTFETs formed on a common substrate. Fig. 25-34 illustrate an example of such a process for forming a plurality of different channel lengths.

Fig. 25 illustrates a side cross-sectional view 2500 of a semiconductor structure similar to that shown in fig. 3, wherein similarly labeled elements are formed of similar materials, have similar dimensions, and have similar processing. However, in the semiconductor structure shown in FIG. 25, the fins are arranged in different regions 2501-1 and 2501-2, with STI region 2503 (formed of a similar material as STI region 103) formed between the fins in different regions 2501-1 and 2501-2. The STI region 2503 may be formed after the bottom source/drain region 106 is formed. In an example process described below with respect to fig. 25-34, the fins in region 2501-1 are used to form "long" channel devices, while the fins in region 2501-2 are used to form "short" channel devices.

Fig. 26 illustrates a side cross-sectional view 2600 of the semiconductor structure of fig. 25 after patterning a mask layer 2505 over a top surface thereof and etching to pattern or remove portions of dummy gates 112 exposed by mask layer 2505. The mask layer 2505 may be formed of materials similar to those described above with respect to the mask layer 124 and having dimensions similar to those described above with respect to the mask layer 124. The opening 2601 may have a width in the range of 20nm to 150nm, but other suitable widths above or below this range may be used as long as the portion of dummy gate 112 material is sufficient to retain the fin in the surrounding regions 2501-1 and 2501-2 closest to the opening 2601. The dummy gate 112 exposed by the mask layer 2505 may be removed using directional RIE or other suitable process.

Fig. 27 shows a side cross-sectional view 2700 of the semiconductor structure of fig. 26 after forming a pad 2507. The liner 2507 may be formed of a material similar to the bottom spacer 108 (e.g., SiN). The pad 2507 may have a width or thickness (in the direction X-X ") in the range of 5nm to 20nm, although other suitable widths above or below this range may be used as desired for a particular application. The liner 2508 may be formed by any suitable deposition followed by RIE.

Fig. 28 illustrates a side cross-sectional view 2800 of the semiconductor structure of fig. 27 after the recess of the dummy gate 112. The recess of the dummy gate 112 may use a process similar to that described above with respect to fig. 4, but in the example of fig. 28, the dummy gate 112 in the long channel region (e.g., 2501-1) is recessed a first depth 2801, and the dummy gate 112 in the short channel region (e.g., 2501-2) is recessed a second depth 2803, where the second depth 2803 is greater than the first depth 2801. In some embodiments, first depth 2801 may be in the range of 15nm to 100nm and second depth 2803 in the range of 25nm to 110nm, although other depths outside these ranges may be used to form different channel lengths as desired. It should be understood that although fig. 25-34 illustrate examples in which two different channel lengths are formed, embodiments are not limited thereto. Instead, any number of different channel lengths may be formed as desired using techniques similar to those described with reference to fig. 25-34.

Recessing the dummy gate 112 to different depths 2801 and 2803 may involve first recessing the dummy gate 112 to a depth 2801 in both the long and short channel regions, followed by masking or protecting the dummy gate 112 in the long channel region, followed by additional recessing of the dummy gate 112 in the short channel region. Alternatively, the recess of the dummy gate 112 in the long channel region may be performed while protecting the dummy gate 112 in the short channel region, followed by the recess of the dummy gate 112 in the short channel region while protecting the dummy gate 112 in the long channel region (or vice versa).

Fig. 29 shows a side cross-sectional view 2900 of the semiconductor structure of fig. 28 after forming top spacers 2514, which top spacers 2514 may be formed with similar materials, similar dimensions, and similar processing as the top spacers 114. Prior to forming the top spacers 2514, the hard mask 104 over each fin is removed and the oxide 110 is recessed to have a top surface that is substantially coplanar with the surrounding dummy gate 112. The spacer 2507 is also removed prior to forming the top spacer 2514.

Fig. 30 shows a side cross-sectional view 3000 of the semiconductor structure of fig. 29 after forming a top junction 2516. The formation of the top junction 2516 may use a process similar to that described above with respect to the formation of the top junction 116. As shown in fig. 30, the top junction 2516 in the short channel region is "longer" or has a greater vertical thickness relative to the top junction 2516 in the long channel region. The top junctions 2516 in both the long and short channel regions extend below the surface of the surrounding dummy gate 112 to a depth in the range of 2nm to 10nm, although other suitable depths outside this range may be used as desired for a particular application. However, the top junction 2516 should overlap the gate conductor, otherwise transistor performance may degrade due to the undoped region.

Fig. 31 shows a side cross-sectional view 3100 of the semiconductor structure of fig. 30 after forming an isolation layer 2518, spacers 2520, and ILD 2522. Isolation layer 2518, spacers 2520, and ILD 2522 may be formed of similar materials, with similar dimensions, and using similar processes to those described above with respect to isolation layer 118, spacers 120, and ILD122, respectively.

Fig. 32 shows a side cross-sectional view 3200 of the semiconductor structure of fig. 31 after opening to expose the top junction 2516 by using a patterned masking layer 2524. The mask layer 2524 may be patterned in a manner similar to that described above with respect to the mask layer 124. The opening exposing the top junction 2516 may be formed using a process similar to that described above with respect to fig. 9.

Fig. 33 shows a side cross-sectional view 3300 of the semiconductor structure of fig. 32 after forming a top source/drain region 2526 and a metal layer 2528 over the top source/drain region 2526. The top source/drain region 2526 may be formed of similar materials, with similar dimensions, and using similar processes to those described above with respect to the top source/drain region 126. However, fig. 33 shows an embodiment in which the optional lateral etch of fig. 10 is not performed. However, in other embodiments, the optional lateral etch described above with respect to fig. 10 may also be used to form the top source/drain regions 2526. The metal layer 2528 may be formed of similar materials, sized similarly, and using similar processes to those described above with respect to metal layer 128.

FIG. 34 illustrates a side cross-sectional view 3400 of the semiconductor structure of FIG. 33 after recessing metal layer 2528 and forming a SAC cap layer 2530 (also referred to herein as a top source/drain SAC cap layer). The recess of metal layer 2528 and the formation of SAC cap layer 2530 may use similar processing as described above with respect to fig. 12. SAC cap layer 2530 can be formed of similar materials and in similar dimensions as SAC cap layer 130.

Similar to fig. 1-12, fig. 25-34 are cross-sectional views taken perpendicular to the fin (e.g., along line a-a in top view 2400 of fig. 24). The semiconductor structure of fig. 34 may be subjected to further processing similar to the RMG described above with respect to fig. 13-23.

The RMG techniques described herein may also be used to form CMOS devices or for CMOS patterning. The RMG process for CMOS patterning will now be described with respect to fig. 35-45.

Fig. 35 illustrates a side cross-sectional view 3500 of a semiconductor structure having a shared dummy gate 3512. The semiconductor structure of fig. 35 includes a substrate 3502, STI regions 3503, bottom source/drain regions 3506-1 and 3506-2 (collectively bottom source/drain regions 3506), bottom spacers 3508, top spacers 3510, ILD 3522, top source/drain regions 3526-1 and 3526-2 (collectively top source/drain regions 3526), a metal layer 3528, and a SAC cap layer 3530, which may be formed of similar materials, of similar dimensions, and using similar processing as described above with respect to substrate 102, STI regions 103, bottom source/drain regions 106, bottom spacers 108, top spacers 110, ILD122, top source/drain regions 126, metal layer 128, and SAC cap layer 130, respectively. However, FIG. 35 shows a CMOS arrangement with a first fin 3501-1 forming an NFET and a second fin 3502-2 forming a PFET. Fins 3501-1 and 3501-2 (collectively, fins 3501) are shown in dashed outline because they are "behind" shared dummy gate 3512 in side cross-sectional view 3500.

The bottom source/drain region 3506-1 and the top source/drain region 3526-1 of the NFET may be doped with n-type dopants, and the bottom source/drain region 3506-2 and the top source/drain region 3526-2 are doped with p-type dopants. The distance 3505 between the fins 3501-1 and 3501-2 may be 75nm, or more generally in the range of 30nm to 100nm, but other distances outside this range may be used as desired, as long as there is sufficient space for forming the shared gate contact using the processes described below.

Fig. 36 illustrates a side cross-sectional view 3600 of the semiconductor structure of fig. 35 after opening the shared dummy gate 3512 using a patterned masking layer 3532. Openings to the shared dummy gate 3512 may be formed using a process similar to that described above with respect to fig. 14. Mask layer 3532 may be formed of similar materials and of similar dimensions as mask layer 132.

Fig. 37 shows a side cross-sectional view 3700 of the semiconductor structure of fig. 36 after forming a liner 3534 using a process similar to that described above with respect to fig. 15. Gasket 3534 may be formed of similar materials and similar dimensions as gasket 134.

Fig. 38 illustrates a side cross-sectional view 3800 of the semiconductor structure of fig. 37 after removal of the shared dummy gate 3512. The shared dummy gate 3512 may be removed using a process similar to that described above with respect to the removal of the dummy gate 112.

Fig. 39 shows a side cross-sectional view 3900 of the semiconductor structure of fig. 38 after deposition of a gate dielectric (not shown) and a PFET WFM3536-2 (more generally, a PFET gate conductor 3536-2). Initially, as shown, PFET WFM3536-2 is formed around fin 3501-1 of the NFET device, but is removed during subsequent processing described below. PFET WFM3536-2 may be formed of nitrides, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), or carbides, including but not limited to titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), although other suitable materials may be used. PFET WFM3536-2 may be formed using a conformal deposition process, such as ALD or CVD.

Fig. 40 shows a side cross-sectional view 4000 of the semiconductor structure of fig. 39 after patterning PFET WFM 3536-2. PFET WFM3536-2 is patterned by blocking the PFET area (e.g., PFET WFM3536-2 surrounding fin 3501-2), while PFET WFM3536-2 in the NFET area (e.g., the portion of PFET WFM3536-2 surrounding fin 3501-1) is removed using wet chemical etching (e.g., SC1) or other suitable process. An Organic Polymer Layer (OPL)3537 may be used to block PFET WFM3536-2 in the PFET region. When PFET WFM3536-2 is removed in the NFET region, gate dielectric 3534 surrounding fin 3501-1 is visible (gate dielectric 3534 similarly surrounds fin 3501-2, but is not visible in side cross-sectional view 4000). Although the PFET region is blocked by OPL3537 during removal of PFET WFM3536-2 from the NFET region, there is some lateral undercut 4001 removal of PFET WFM3536-2 in the PFET region, as shown. However, the lateral undercut 4001 is small, which advantageously corresponds to a very small n-to-p boundary shift during the patterning of the gate metal.

Fig. 41 shows a side cross-sectional view 4100 of the semiconductor structure of fig. 40 after forming NFET WFM3536-1 (and more generally NFET gate conductor 3536-1). NFET WFM3536-1 may be formed using a conformal deposition process, such as ALD or CVD. NFETWFM3536-1 may be formed from nitrides, such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), carbides, including but not limited to titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), and combinations thereof, although other suitable materials may be used. It should be understood that while fig. 39-41 illustrate forming NFET WFM3536-1 after forming PFET WFM3536-2, in other embodiments, NFET WFM3536-1 may be formed using a similar process prior to forming PFET WFM3536-2 (e.g., first forming NFET WFM3536-1 followed by blocking the NFET region while removing NFET WFM3536-1 from the PFET region).

Fig. 42 shows a side cross-sectional view 4200 of the semiconductor structure of fig. 41 after filling with metal layer 3538, metal layer 3538 may be formed using similar materials and using similar processing as metal layer 138.

FIG. 43 illustrates a side cross-sectional view 4300 of the semiconductor structure of FIG. 42 after formation of a recess of metal layer 3538 (and recesses of NFET WFM3536-1 and PFET WFM 3536-2) and a SAC cap layer 3540 (also referred to as a gate SAC cap layer or a shared gate SAC cap layer). The recess of metal layer 3538 (as well as the recesses of NFET WFM3536-1 and PFET WFM 3536-2) and the formation of SAC cap layer 3540 may use similar processes as described above with respect to the recess of metal layer 138 and the formation of SAC cap layer 140. SAC cap layer 3540 can be formed of similar materials and similar dimensions as SAC cap layer 140.

FIG. 44 illustrates a side cross-sectional view 4400 of the semiconductor structure of FIG. 43 after forming vias 3554-1 and 3554-2 that access contacts of top source/drain regions 3526-1 and 3526-2, respectively, and via 3556 that accesses a shared gate contact. Vias 3554-1 and 3554-2 (collectively referred to as vias 3554) and via 3556 may be formed of similar materials, with similar dimensions, and using similar processing as described above with respect to the formation of vias 154 and 156. Although not shown in FIG. 44, vias 3552-1 and 3552-2 are also formed to bottom source/drain regions 3506-1 and 3506-2 (as shown in FIG. 45, a similar process is employed as described with respect to the formation of via 152).

Fig. 45 shows a top view 4500 of the semiconductor structure of fig. 44. It should be noted that top view 4500 is presented to show the location of vias 3552-1, 3552-2, 3554-1, 3554-2, and 3556 relative to fins 3501-1 and 3501-2, and thus the underlying different details are omitted for clarity of illustration. The bottom source/drain contact vias 3552-1 and 3552-2 may have dimensions similar to the dimensions of the bottom source/drain contacts 152. Each fin 3501 may have a length similar to the length (in direction Y-Y ") of fin 101. As shown, top source/drain contacts 3554-1 and 3554-2 may have a length that matches the length of fin 3501, but this is not required. The gate contact via 3556 may have a thickness similar to the thickness of the gate contact 156.

Top view 4500 shows mask regions 4501, 4503, and 4505 similar to mask regions 2401, 2403, and 2405. The side cross-sectional views of fig. 35-44 are taken running on a pair of fins 3501-1 and 3501-2, such as along line B-B in top view 4500 of fig. 45.

In some embodiments of the present invention, a method of forming a semiconductor structure comprises: forming a plurality of fins disposed over a top surface of a substrate; and forming one or more VTFETs from the plurality of fins using an RMG process. The gate surrounding at least one fin of a given one of the VTFETs includes a gate SAC cap layer disposed over a gate contact metal layer disposed adjacent to an end of the at least one fin.

Forming one or more VTFETs may include: forming a bottom source/drain region disposed above a top surface of the substrate and surrounding the plurality of fins; and forming bottom spacers disposed over the bottom source/drain regions.

Forming one or more VTFETs may further include: forming an oxide layer disposed over the bottom spacers and sidewalls of the plurality of fins; forming a dummy gate disposed over the oxide layer; recessing the dummy gate below a top surface of the plurality of fins; removing the exposed portion of the oxide layer; and forming a top spacer disposed over the dummy gate and the plurality of fins.

Forming one or more VTFETs may further include forming a top junction in an upper portion of the plurality of fins, forming an oxide layer disposed over the top spacers, forming a liner disposed over the oxide layer, and forming an inter-level dielectric layer disposed over the liner.

Forming the one or more VTFETs may further include forming a top source/drain opening in the inter-level dielectric layer to expose a top surface of the top junction of each of the plurality of fins, forming a top source/drain region disposed above the top junction, forming a top source/drain contact metal layer disposed above the top source/drain region, recessing the top source/drain contact metal layer below the top surface of the inter-level dielectric, and forming a top source/drain SAC cap layer disposed above the recessed top source/drain contact metal layer.

Forming one or more VTFETs may further include forming a gate opening in the inter-level dielectric layer to expose a portion of the top spacers disposed over the dummy gate, depositing a liner on sidewalls of the opening of the inter-level dielectric layer, etching the exposed portion of the top spacer to expose a portion of the dummy gate, removing the dummy gate, performing the replacement metal gate process to form a gate dielectric surrounding the one or more fins and to form a metal gate conductor surrounding the gate dielectric, filling the gate contact metal layer in a remaining portion of the gate opening in the interlevel dielectric layer, recessing the gate contact metal layer below the top surface of the interlevel dielectric layer, and forming a gate SAC cap layer disposed over the recessed gate contact metal layer.

Forming the one or more VTFETs may further include forming a bottom source/drain opening in the inter-level dielectric layer to expose a portion of a top surface of the bottom source/drain region, filling a bottom source/drain contact metal layer in the bottom source/drain opening disposed above the exposed portion of the top surface of the bottom source/drain region, recessing the bottom source/drain contact metal layer below the top surface of the inter-level dielectric layer, and forming a bottom source/drain SAC cap layer disposed above the recessed bottom source/drain contact layer.

Forming the one or more VTFETs may further include forming additional spacers disposed over the inter-level dielectric, the top source/drain SAC cap layer, the gate SAC cap layer, and the bottom source/drain SAC cap layer, forming additional inter-level dielectrics disposed over the additional spacers, forming vias in the additional spacers, the additional inter-level dielectrics, the top source/drain SAC cap layer, the gate SAC cap layer, and the bottom source/drain SAC cap layer to expose portions of the top surfaces of the top source/drain contact metal layer, the gate contact metal layer, and the bottom source/drain contact metal layer, and forming top source/drain contacts, gate contacts, and bottom source/drain contacts in the vias.

Forming one or more VTFETs may further include: forming at least one shallow trench isolation region in the substrate and the bottom source/drain region between a first subset of the plurality of fins and at least a second subset of the plurality of fins, wherein recessing the dummy gate includes recessing a first portion of the dummy gate around the first subset of the plurality of fins to a first depth and recessing a second portion of the dummy gate around the second subset of the plurality of fins to a second depth greater than the first depth. A first subset of the plurality of fins forms a VTFET having a first channel length and a second subset of the plurality of fins forms a VTFET having a second channel length less than the first channel length.

Recessing the first portion of the dummy gate and recessing the second portion of the dummy gate may include: patterning a mask layer over the dummy gate to expose a top surface of the dummy gate disposed over the at least one shallow trench isolation region; removing the exposed portion of the dummy gate to expose a portion of the bottom spacer disposed over the at least one shallow trench isolation region; and forming a liner on the exposed side wall of the dummy gate.

The dummy gate may include a shared dummy gate surrounding pairs of the plurality of fins, each pair of the plurality of fins including a first fin forming a channel for one of a PFET of a given CMOS device and an NFET of the given CMOS device, and a second fin forming a channel for the other of the PFET and the NFET of the given CMOS device.

Forming one or more VTFETs may further include: patterning a gate opening in an interlevel dielectric layer disposed over the top spacer above the shared dummy gate; removing a portion of the inter-level dielectric layer to expose a portion of a top surface of the top spacer; forming a liner on exposed sidewalls of the inter-level dielectric layer in the gate opening; and removing the shared dummy gate.

Forming one or more VTFETs may further include: forming a gate dielectric surrounding the first fin and the second fin, forming a first gate conductor layer surrounding the gate dielectric, a top surface of the substrate, and the liner disposed on exposed sidewalls of the inter-level dielectric layer, blocking a first portion of the gate opening and the first gate conductor layer surrounding the first fin with an organic polymer layer, removing the first gate conductor layer surrounding the second fin exposed by the organic polymer layer, removing the organic polymer layer, and forming a second gate conductor layer surrounding the gate dielectric surrounding the second fin.

The method may also include filling a gate contact metal layer in a gate opening that contacts the first gate conductor layer and the second gate conductor layer, recessing the gate contact metal layer below a top surface of the interlevel dielectric, and forming a gate SAC cap layer disposed over the recessed gate contact metal layer.

In some embodiments of the invention, a semiconductor structure includes a substrate and a plurality of fins disposed above a top surface of the substrate, the plurality of fins including a channel for one or more VTFETs formed using an RMG process. A given VTFET of the VTFETs includes a gate surrounding at least one fin of the plurality of fins, the gate of the given VTFET including a gate SAC cap layer disposed over a gate contact metal layer disposed adjacent an end of the at least one fin.

The semiconductor structure may further include a bottom source/drain region disposed above a top surface of the substrate surrounding the plurality of fins, a bottom spacer disposed above the bottom source/drain region, the gate surrounding the plurality of fins, a top spacer disposed above the gate, a top source/drain region disposed above a portion of the top spacer disposed above each of the plurality of fins, a top source/drain contact metal layer disposed above the top source/drain region, a top source/drain SAC cap layer disposed above the top source/drain metal contact layer, a bottom source/drain contact metal layer disposed above a portion of the bottom source/drain region, and a bottom source/drain SAC cap layer disposed over the bottom source/drain metal contact layer.

In some embodiments, at least two fins of the plurality of fins have different heights.

In some embodiments, the gate of a given VTFET includes a shared gate surrounding pairs of the plurality of fins, each pair of the plurality of fins including a first fin forming a channel for one of the PFET and the NFET of the given CMOS device and a second fin forming a channel for the other of the PFET and the NFET of the given CMOS device.

In some embodiments of the present invention, the shared gate includes a first gate conductor surrounding the first fin and a second gate conductor surrounding the second fin, and the gate contact metal layer contacts the first gate conductor and the second gate conductor.

In some embodiments of the invention, an integrated circuit includes one or more VTFETs including a substrate and a plurality of fins disposed over a top surface of the substrate, the plurality of fins including a channel for the one or more VTFETs formed using an RMG process. A given VTFET of the VTFETs includes a gate surrounding at least one fin of the plurality of fins, the gate of the given VTFET including a gate SAC cap layer disposed over a gate contact metal layer disposed adjacent an end of the at least one fin.

It should be appreciated that the different materials, processing methods (e.g., etch types, deposition types, etc.), and dimensions provided in the discussion above are presented by way of example only. Various other suitable materials, processing methods, and dimensions may be used as desired.

The semiconductor device and method of forming the same according to the above-described techniques may be used in different applications, hardware and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, sensors, sensing devices, personal computers, communication networks, electronic commerce systems, portable communication devices (e.g., cellular and smart phones), solid-state media storage devices, functional circuits, and the like. Systems and hardware comprising semiconductor devices are contemplated embodiments of the present invention. Given the teachings provided herein, one of ordinary skill in the related art will be able to contemplate other implementations and applications of embodiments of the present invention.

The different structures described above may be implemented in an integrated circuit. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (i.e., as a single wafer having multiple unpackaged chips), as a die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier with leads that are affixed to a motherboard or other higher level carrier) or in a multi-chip package (such as a ceramic carrier with one or both of surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

The description of the different embodiments of the present invention has been presented for purposes of illustration but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The terminology used herein was chosen to best explain the principles of the embodiments of the invention, the practical application or technical improvements found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments of the invention disclosed herein.