阅读说明：本技术 P型mosfet及其制造方法 (P-type MOSFET and manufacturing method thereof ) 是由 李中华 于 2020-05-28 设计创作，主要内容包括：本发明公开了一种P型MOSFET,沟道区由被栅极结构覆盖的N阱组成,N阱包括由第一至第三注入区组成的叠加区且叠加区经过退火处理；第一至三注入区的注入杂质分别为磷、氙和砷；第三注入区的掺杂浓度用于调节阈值电压,第三注入区的离子注入工艺在第二注入区的离子注入工艺完成之后进行,第二注入区在半导体衬底中形成非晶化层以使第三注入区砷注入均匀。本发明还公开了一种P型MOSFET的制造方法。本发明能降低阈值电压的局部波动,提高器件性能和产品良率。(The invention discloses a P-type MOSFET.A channel region consists of an N well covered by a grid structure, the N well comprises an overlapping region consisting of a first injection region, a second injection region and a third injection region, and the overlapping region is subjected to annealing treatment; the implanted impurities of the first to third implantation regions are phosphorus, xenon and arsenic respectively; the doping concentration of the third implantation region is used for adjusting the threshold voltage, the ion implantation process of the third implantation region is performed after the ion implantation process of the second implantation region is completed, and the second implantation region forms an amorphization layer in the semiconductor substrate so that the arsenic implantation of the third implantation region is uniform. The invention also discloses a manufacturing method of the P-type MOSFET. The invention can reduce the local fluctuation of the threshold voltage and improve the performance of the device and the yield of products.)

1. A P-type MOSFET, comprising: the channel region consists of an N well covered by a grid structure, the N well comprises an overlapping region consisting of a first injection region, a second injection region and a third injection region which are formed in a semiconductor substrate, and the overlapping region is subjected to annealing treatment;

the implanted impurity of the first implantation region is phosphorus;

the implanted impurities of the second implantation area are xenon;

the implanted impurity of the third implantation area is arsenic;

the junction depth of the first injection region is greater than that of the second injection region, and the junction depth of the first injection region is greater than that of the third injection region;

the doping concentration of the third implantation region is used for adjusting the threshold voltage, the ion implantation process of the third implantation region is performed after the ion implantation process of the second implantation region is completed, before the ion implantation of the third implantation region, the second implantation region forms an amorphization layer in the semiconductor substrate, and the amorphization layer enables the third implantation region to form uniform arsenic implantation so as to reduce the fluctuation of the threshold voltage.

2. The P-type MOSFET of claim 1 wherein: the semiconductor substrate includes a silicon substrate.

3. The P-type MOSFET of claim 1 wherein: a field oxide layer is formed on the semiconductor substrate, an active region is isolated by the field oxide layer, and a P-type MOSFET is formed in the active region.

4. The P-type MOSFET of claim 1 wherein: an N-type deep well is formed on the semiconductor substrate, and the N-type deep well is formed in the N-type deep well.

5. The P-type MOSFET of claim 2 wherein: and forming a drain region and a source region in the semiconductor substrate at two sides of the gate structure.

6. The P-type MOSFET of claim 2 wherein: the grid structure comprises a layer of superposed grid dielectric layer and a grid conducting material layer.

7. The P-type MOSFET of claim 6 wherein: the gate dielectric layer is made of silicon oxide, silicon oxynitride or a high-dielectric-constant material;

the grid electrode conducting material layer is a polysilicon grid or a metal grid.

8. The P-type MOSFET of claim 7 wherein: the high dielectric constant material includes hafnium oxide.

9. The P-type MOSFET of claim 1 wherein:

the implantation energy of the ion implantation of the first implantation region is 100 KeV-300 KeV, and the implantation dose is 1 × 10¹³cm^-2～1×10¹⁴cm^-2；

The ion implantation energy of the second implantation region is 1 KeV-100 KeV, and the implantation dosage is 1 × 10¹⁴cm^-2～1×10¹⁶cm^-2；

The implantation energy of the ion implantation of the third implantation region is 1 KeV-80 KeV, and the implantation dosage is 1 × 10¹²cm^-2～1*10¹⁴cm^-2。

10. The P-type MOSFET of claim 9 wherein: the temperature of the superposed region after annealing treatment is 1000-1300 ℃.

11. A method for manufacturing a P-type MOSFET is characterized by comprising the following steps:

step one, providing a semiconductor substrate, defining an active region on the semiconductor substrate, and forming an N-type deep well, wherein the N-type deep well is formed through an ion implantation and annealing process, and ions of the N-type deep well are implanted through a cushion layer oxide layer;

removing the cushion oxide layer and forming a sacrificial oxide layer before ion implantation of the N trap;

step three, carrying out ion implantation of the N trap, comprising the following sub-steps:

carrying out first phosphorus ion implantation to form a first implantation area;

carrying out xenon ion implantation for the second time to form a second implantation area;

performing a third arsenic ion implantation to form a third implantation area;

the first injection region, the second injection region and the third injection region form an overlapping region, and the overlapping region is positioned in the N-type deep well;

the junction depth of the first injection region is greater than that of the second injection region, and the junction depth of the first injection region is greater than that of the third injection region;

the doping concentration of the third implantation region is used for adjusting the threshold voltage, before the third arsenic ion implantation, the second xenon ion implantation forms an amorphization layer in the semiconductor substrate, and the amorphization layer enables the third arsenic ion implantation to be uniform so as to reduce the fluctuation of the threshold voltage;

annealing the superposition region to form the N well;

fifthly, removing the sacrificial oxide layer;

sixthly, forming a grid structure on the semiconductor substrate;

seventhly, performing source-drain injection in the N wells at two sides of the grid structure to form a source region and a drain region; the channel region is composed of the N well covered by the gate structure, and is located between the source region and the drain region.

12. The method of fabricating a P-type MOSFET of claim 11 wherein: the semiconductor substrate includes a silicon substrate.

13. The method of fabricating a P-type MOSFET of claim 11 wherein: the step of defining the active region comprises:

forming a field oxide layer on the semiconductor substrate, isolating an active region by the field oxide layer, and forming a P-type MOSFET in the active region.

14. The method of fabricating a P-type MOSFET of claim 11 wherein: removing the cushion oxide layer by adopting a wet etching or plasma etching process;

and fifthly, removing the sacrificial oxide layer by adopting a wet etching or plasma etching process.

15. The method of fabricating a P-type MOSFET of claim 11 wherein: growing the sacrificial oxide layer by adopting a wet oxygen oxidation process, wherein the temperature of the wet oxygen oxidation process of the sacrificial oxide layer is 1000-1300 ℃; the thickness of the sacrificial oxide layer is

16. The method of fabricating a P-type MOSFET of claim 12 wherein: the grid structure comprises a layer of superposed grid dielectric layer and a grid conducting material layer.

17. The method of fabricating a P-type MOSFET of claim 16 wherein: the gate dielectric layer is made of silicon oxide, silicon oxynitride or a high-dielectric-constant material; the high dielectric constant material includes hafnium oxide.

The grid electrode conducting material layer is a polysilicon grid or a metal grid.

18. The method of fabricating a P-type MOSFET of claim 11 further comprising:

and step eight, forming metal silicide, an interlayer film, a contact hole, a through hole and a front metal layer.

19. The method of fabricating a P-type MOSFET of claim 11 wherein:

the implantation energy of the first phosphorus ion implantation is 100 KeV-300 KeV, and the implantation dosage is 1 × 10¹³cm^-2～1×10¹⁴cm^-2；

The implantation energy of the second xenon ion implantation is 1 KeV-100 KeV, and the implantation dose is 1 × 10¹⁴cm^-2～1×10¹⁶cm^-2；

The implantation energy of the third arsenic ion implantation is 1 KeV-80 KeV, and the implantation dosage is 1 × 10¹²cm^-2～1*10¹⁴cm^-2。

20. The method of fabricating a P-type MOSFET of claim 19 further comprising: the annealing treatment temperature of the superposition area in the fourth step is 1000-1300 ℃.

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a P-type MOSFET. The invention also relates to a manufacturing method of the P-type MOSFET.

Background

P-type MOSFETs, i.e., PMOS, are typically formed in an N-type Deep well (DNW), and the channel region is formed using the N-well. The ion implantation process of the N-type deep well is generally placed before the ion implantation process of the N-type deep well. The ion implantation process of the N-type deep trap has large implantation energy and deep implantation depth. It is usually necessary to form a pad oxide layer on the surface of a semiconductor substrate such as a silicon substrate before ion implantation of the N-type deep well, and the ion implantation of the N-type deep well penetrates through the pad oxide layer.

However, after the ion implantation process of the N-type deep well, the compactness of the pad oxide layer is damaged. This may adversely affect the ion implantation process of the subsequent N-well.

As the technology nodes of semiconductor devices are continuously reduced, the junction depths of the doped regions become shallow, which makes higher and higher demands on the process of forming the N-well of the channel region. In the prior art, an N-well is usually implemented by implanting a layer of phosphorus ions, and the depth fluctuation of phosphorus ion implantation is large, which has a large influence on the threshold voltage of a device.

Disclosure of Invention

The invention aims to provide a P-type MOSFET, which can reduce local fluctuation of threshold voltage and improve device performance and product yield. Therefore, the invention also provides a manufacturing method of the P-type MOSFET.

In order to solve the above technical problem, the channel region of the P-type MOSFET provided by the present invention is composed of an N-well covered by a gate structure, the N-well includes an overlap region composed of a first implantation region, a second implantation region, and a third implantation region formed in a semiconductor substrate, and the overlap region is annealed.

The implanted impurity of the first implantation region is phosphorus.

The implanted impurity of the second implantation region is xenon.

The implanted impurity of the third implantation area is arsenic.

The junction depth of the first injection region is greater than that of the second injection region, and the junction depth of the first injection region is greater than that of the third injection region.

The doping concentration of the third implantation region is used for adjusting the threshold voltage, the ion implantation process of the third implantation region is performed after the ion implantation process of the second implantation region is completed, before the ion implantation of the third implantation region, the second implantation region forms an amorphization layer in the semiconductor substrate, and the amorphization layer enables the third implantation region to form uniform arsenic implantation so as to reduce the fluctuation of the threshold voltage.

In a further refinement, the semiconductor substrate comprises a silicon substrate.

In a further improvement, a field oxide layer is formed on the semiconductor substrate, an active region is isolated by the field oxide layer, and a P-type MOSFET is formed in the active region.

In a further improvement, an N-type deep well is formed on the semiconductor substrate, and the N-well is formed in the N-type deep well.

In a further improvement, a drain region and a source region are formed in the semiconductor substrate on both sides of the gate structure.

In a further improvement, the gate structure comprises a layer of stacked gate dielectric layer and gate conductive material layer.

In a further improvement, the material of the gate dielectric layer comprises silicon oxide, silicon oxynitride or a high dielectric constant material.

The grid electrode conducting material layer is a polysilicon grid or a metal grid.

In a further refinement, the high dielectric constant material comprises hafnium oxide.

In a further improvement, the ion implantation energy of the first implantation region is 100 KeV-300 KeV, and the implantation dosage is 1 × 10¹³cm^-2～1×10¹⁴cm^-2；

The ion implantation energy of the second implantation region is 1 KeV-100 KeV, and the implantation dosage is 1 × 10¹⁴cm^-2～1×10¹⁶cm^-2；

The implantation energy of the ion implantation of the third implantation region is 1 KeV-80 KeV, and the implantation dosage is 1 × 10¹²cm^-2～1*10¹⁴cm^-2。

The further improvement is that the temperature of the superposed region after annealing treatment is 1000-1300 ℃.

In order to solve the above technical problem, the method for manufacturing a P-type MOSFET provided by the present invention comprises the following steps:

step one, providing a semiconductor substrate, defining an active region on the semiconductor substrate, and forming an N-type deep well, wherein the N-type deep well is formed through an ion implantation and annealing process, and ions of the N-type deep well are implanted to penetrate through a cushion layer oxide layer.

And step two, removing the cushion layer oxide layer and forming a sacrificial oxide layer before ion implantation of the N trap.

Step three, carrying out ion implantation of the N trap, comprising the following sub-steps:

a first phosphorus ion implantation is performed to form a first implanted region.

A second xenon ion implantation is performed to form a second implanted region.

And performing third arsenic ion implantation to form a third implantation area.

And the overlapping region is formed by the first injection region, the second injection region and the third injection region and is positioned in the N-type deep well.

The junction depth of the first injection region is greater than that of the second injection region, and the junction depth of the first injection region is greater than that of the third injection region.

And the doping concentration of the third implantation region is used for adjusting the threshold voltage, before the third arsenic ion implantation, the second xenon ion implantation forms an amorphization layer in the semiconductor substrate, and the amorphization layer enables the third arsenic ion implantation to be uniform so as to reduce the fluctuation of the threshold voltage.

And fourthly, annealing the superposed region to form the N well.

And fifthly, removing the sacrificial oxide layer.

And step six, forming a grid structure on the semiconductor substrate.

Seventhly, performing source-drain injection in the N wells at two sides of the grid structure to form a source region and a drain region; the channel region is composed of the N well covered by the gate structure, and is located between the source region and the drain region.

In a further refinement, the semiconductor substrate comprises a silicon substrate.

In a further refinement, the step of defining the active region comprises:

forming a field oxide layer on the semiconductor substrate, isolating an active region by the field oxide layer, and forming a P-type MOSFET in the active region.

In the second step, the cushion oxide layer is removed by wet etching or plasma etching;

and fifthly, removing the sacrificial oxide layer by adopting a wet etching or plasma etching process.

The further improvement is that in the second step, the sacrificial oxide layer is grown by adopting a wet oxygen oxidation process, and the temperature of the wet oxygen oxidation process of the sacrificial oxide layer is 1000-1300 ℃; the thickness of the sacrificial oxide layer is

In a further improvement, the gate structure comprises a layer of stacked gate dielectric layer and gate conductive material layer.

In a further improvement, the gate dielectric layer is made of silicon oxide, silicon oxynitride or a high-dielectric-constant material; the high dielectric constant material includes hafnium oxide.

The grid electrode conducting material layer is a polysilicon grid or a metal grid.

The further improvement is that the method also comprises the following steps:

and step eight, forming metal silicide, an interlayer film, a contact hole, a through hole and a front metal layer.

In a further improvement, the implantation energy of the first phosphorus ion implantation is 100 KeV-300 KeV, and the implantation dosage is 1 × 10¹³cm^-2～1×10¹⁴cm^-2；

The implantation energy of the second xenon ion implantation is 1 KeV-100 KeV, and the implantation dose is 1 × 10¹⁴cm^-2～1×10¹⁶cm^-2；

The implantation energy of the third arsenic ion implantation is 1 KeV-80 KeV, and the implantation dosage is 1 × 10¹²cm^-2～1*10¹⁴cm^-2。

The further improvement is that the annealing treatment temperature of the superposition area in the fourth step is 1000-1300 ℃.

The invention has made the special arrangement to the structure used for forming the N trap of the channel region, the N trap is no longer made up of single doped structure, but divide into the overlapping area formed by first to three injection regions and form after annealing, the invention has made the special arrangement to the doped structure of the first to three injection regions and realized different functional structures separately, wherein:

the first injection region is doped with phosphorus, and the injection depth of the first injection region is deeper, so that the isolation between the source and the drain can be well realized.

The second injection area is doped with xenon, and the ion injection process of xenon doping can amorphize the surface of the semiconductor substrate, so that compared with the non-purification realized by silicon injection in the prior art, the amorphization effect realized by xenon injection is better, and finally, the uniform arsenic doping of the third injection area can be improved.

The third injection region is doped with arsenic, the arsenic doping is located on the outermost surface of the channel region and can well adjust the threshold voltage of the device, and an amorphous layer is formed before the arsenic-doped ions are injected, so that the uniformity of the arsenic doping is easily improved, the local fluctuation of the threshold voltage can be reduced, and the product yield can be improved.

Therefore, after the doping structure of the N well is specially arranged, the local fluctuation of the threshold voltage can be reduced, and the performance of the device and the yield of products are improved.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIGS. 1A-1L are schematic views of device structures at various steps of a method of fabricating a P-type MOSFET in accordance with an embodiment of the present invention;

FIG. 2A is a first photograph of an interface between amorphous silicon and crystalline silicon formed by amorphization using Si implantation in a conventional method;

FIG. 2B is a second photograph of an interface between amorphous silicon and crystalline silicon formed by amorphization using Xe implantation in the method according to the embodiment of the present invention;

FIG. 2C is a photograph showing a third interface between amorphous silicon and crystalline silicon formed by amorphization using Si implantation in the conventional method;

FIG. 2D is a photograph of a fourth interface between amorphous silicon and crystalline silicon formed by amorphization using Xe implantation in the method according to the embodiment of the present invention.

Detailed Description

Referring to fig. 1K and 1L, the structure of the channel region of the P-type MOSFET according to the embodiment of the present invention is shown, the channel region is composed of an N-well 8 covered by a gate structure, the N-well 8 includes an overlap region 7 composed of a first implantation region 4, a second implantation region 5, and a third implantation region 6 formed in a semiconductor substrate 101, and the overlap region 7 is annealed, that is, the overlap region 7 is annealed to form the N-well 8. Referring to fig. 1A, fig. 1K only illustrates the structure of an N-type deep well 2 formed in the semiconductor substrate 101.

In the embodiment of the present invention, the semiconductor substrate 101 includes a silicon substrate.

Preferably, a field oxide layer 1 is formed on the semiconductor substrate 101, and an active region is isolated by the field oxide layer 1, that is, the semiconductor substrate 101 in the region surrounded by the field oxide layer 1 serves as the active region. A P-type MOSFET is formed in the active region.

An N-type deep well 2 is formed on the semiconductor substrate 101, and the N-well 8 is formed in the N-type deep well 2. In fig. 1J, the semiconductor substrate 101 at the bottom of the N-type deep well 2 is not shown.

The implanted impurity of the first implanted region 4 is phosphorus.

Preferably, the ion implantation energy of the first implantation region 4 is 100KeV to 300KeV, and the implantation dose is 1 × 10¹³cm^-2～1×10¹⁴cm^-2；

The implanted impurity of the second implantation region 5 is xenon.

Preferably, the first stepThe implantation energy of the ion implantation of the two implantation regions 5 is 1 KeV-100 KeV, and the implantation dose is 1 × 10¹⁴cm^-2～1×10¹⁶cm^-2；

The implanted impurity of the third implantation region 6 is arsenic.

Preferably, the ion implantation energy of the third implantation region 6 is 1KeV to 80KeV, and the implantation dose is 1 × 10¹²cm^-2～1*10¹⁴cm^-2。

The temperature of the superposition area 7 after annealing treatment is 1000-1300 ℃.

As shown in fig. 1J, the ion implantation processes of the first implantation region 4, the second implantation region 5 and the third implantation region 6 corresponding to the N-well 8 of the embodiment of the invention all penetrate through the sacrificial oxide layer 3; the sacrificial oxide layer 3 is removed after the annealing of the overlap region 7 is completed, as shown in fig. 1L. In the embodiment of the present invention, the ion implantation of the first implantation region 4 is performed first, and the sacrificial oxide layer 3 is required to grow before the ion implantation of the first implantation region 4 is performed, so as to ensure the compactness of the sacrificial oxide layer 3, thereby ensuring the uniformity of each ion implantation of the N-well 8, and thus improving the quality of the N-well 8.

The junction depth of the first implanted region 4 is greater than the junction depth of the second implanted region 5, and the junction depth of the first implanted region 4 is also greater than the junction depth of the third implanted region 6.

The doping concentration of the third implantation region 6 is used for adjusting the threshold voltage, the ion implantation process of the third implantation region 6 is performed after the ion implantation process of the second implantation region 5 is completed, before the ion implantation of the third implantation region 6, the second implantation region 5 forms an amorphization layer in the semiconductor substrate 101, and the amorphization layer enables the third implantation region 6 to form uniform arsenic implantation so as to reduce the fluctuation of the threshold voltage.

The junction depth of the first injection region 4 is deeper, so that good isolation can be formed between the source and drain regions, and the source and drain can be prevented from being subjected to electric leakage such as punch-through.

When the device is conducted, the grid structure is added with grid voltage which is larger than or equal to threshold voltage, so that an inversion layer is formed on the surface of the channel region, and the inversion layer is used as a conductive channel for conducting source and drain; therefore, an inversion layer is formed only on the surface of the channel region and is mainly located in the third implantation region 6, and thus the third implantation region 6 of the embodiment of the invention is mainly used for adjusting the threshold voltage. The experimental structure shows that the xenon doping corresponding to the second injection region 5 does not affect the threshold voltage of the device.

A drain region and a source region are formed in the semiconductor substrate 101 on both sides of the gate structure.

The grid structure comprises a layer of superposed grid dielectric layer and a grid conducting material layer.

The gate dielectric layer is made of silicon oxide, silicon oxynitride or a high-dielectric-constant material; the high dielectric constant material includes hafnium oxide. The grid electrode conducting material layer is a polysilicon grid or a metal grid.

In the embodiment of the present invention, the xenon doping introduced into the second implantation region 5 is used to achieve amorphization of the semiconductor substrate 101, so that the subsequent arsenic implantation of the third implantation region 6 is more uniform, and thus the threshold voltage of the device can be adjusted more stably and accurately.

Compared with the prior art in which silicon implantation is adopted for amorphization, the xenon implantation amorphization can achieve better effects:

as shown in fig. 2A, it is a first photo of an interface between amorphous silicon and crystalline silicon formed by amorphization by Si implantation in the conventional method; amorphous silicon is represented by α -Si, crystalline silicon, is represented by c-Si, and the interface of amorphous silicon and crystalline silicon is shown as reference 401.

As shown in fig. 2B, it is a second photograph of an interface between amorphous silicon and crystalline silicon formed by amorphization using Xe implantation in the embodiment of the present invention; the interface of amorphous silicon and crystalline silicon is shown at 402. The magnification of fig. 2B is the same as fig. 2A, and it can be seen that interface 402 will be flatter than interface 401.

As shown in fig. 2C, it is a third photograph of an interface between amorphous silicon and crystalline silicon formed by amorphization by Si implantation in the conventional method; photograph three of FIG. 2C is at a greater magnification than photograph 2A, which is a drawingIn 2C, the thickness d1 of the damaged layer corresponding to the interface 401 was measured to beA in FIG. 2C representsA thickness d2 of amorphous silicon of

FIG. 2D is a photograph showing a fourth interface between amorphous silicon and crystalline silicon formed by amorphization using Xe implantation in the method according to the embodiment of the present invention. FIG. 2D is the same as FIG. 2C in magnification, and in FIG. 2C, the thickness D3 of the damaged layer corresponding to the interface 402 is measured asA in FIG. 2D denotesA thickness d4 of amorphous silicon ofTherefore, the thickness d3 of the damaged layer corresponding to the interface 402 in the embodiment of the present invention is smaller than the thickness d1 of the damaged layer corresponding to the interface 401 in the prior art. Therefore, the embodiment of the invention has better non-crystallizing effect.

The embodiment of the invention makes special arrangement for the structure of the N well 8 for forming the channel region, the N well 8 is not formed by a single doped structure any more, but is formed by annealing after being divided into an overlapping region formed by a first injection region, a second injection region, a third injection region and a fourth injection region, the embodiment of the invention makes special arrangement for the doped structure of the first injection region, the second injection region, the third injection region and the fourth injection region, and different functional structures are respectively realized, wherein:

the first injection region 4 is doped with phosphorus, and the injection depth of the first injection region 4 is deeper, so that the isolation between the source and the drain can be well realized.

The second injection region 5 is doped with xenon, and the ion implantation process of xenon doping can amorphize the surface of the semiconductor substrate, so that compared with the non-purification realized by silicon injection in the prior art, the amorphization effect realized by xenon injection is better, and finally, the uniform arsenic doping of the third injection region 6 can be improved.

The third injection region 6 is doped with arsenic, the arsenic doping is located on the outermost surface of the channel region and can well adjust the threshold voltage of the device, and an amorphous layer is formed before the arsenic-doped ions are injected, so that the uniformity of the arsenic doping is easily improved, the local fluctuation of the threshold voltage can be reduced, and the product yield can be improved.

Therefore, after the doping structure of the N well 8 is specially set, the embodiment of the invention can reduce the local fluctuation of the threshold voltage and improve the performance of the device and the yield of the product.

Fig. 1A to 1L are schematic diagrams of device structures in steps of a method for manufacturing a P-type MOSFET according to an embodiment of the invention; the manufacturing method of the P-type MOSFET comprises the following steps:

step one, as shown in fig. 1A, a semiconductor substrate 101 is provided, wherein the semiconductor substrate 101 includes a silicon substrate.

Defining an active region on the semiconductor substrate 101, the step of defining the active region comprising:

form field oxide 1 on the semiconductor substrate 101, by field oxide 1 isolates active area, and P type MOSFET forms in the active area.

Forming an N-type deep well 2, comprising the steps of:

forming a pad oxide layer 102;

as shown in fig. 1B, ion implantation of the N-type deep well 2 is performed as indicated by reference numeral 103.

As shown in fig. 1C, an annealing process is performed to form the N-type deep well 2. In fig. 1C, the semiconductor substrate 101 at the bottom of the N-type deep well 2 is not shown.

Since the implantation energy of the ion implantation 103 of the N-type deep well 102 is relatively large, a certain damage effect may be generated on the pad oxide layer 102, and in fig. 1C, the pad oxide layer after the ion implantation 103 is completed is separately denoted by a reference numeral 102 a.

Step two, as shown in fig. 1D, the pad oxide layer 102 is removed before the ion implantation of the N-well 8.

In the method of the embodiment of the invention, the pad oxide layer 102 is removed by adopting a wet etching or plasma etching process;

as shown in fig. 1E, a sacrificial oxide layer 3 is formed.

In the method of the embodiment of the invention, the sacrificial oxide layer 3 is grown by adopting a wet oxygen oxidation process, and the temperature of the wet oxygen oxidation process of the sacrificial oxide layer 3 is 1000-1300 ℃; the thickness of the sacrificial oxide layer 3 is

Step three, performing ion implantation of the N trap 8, comprising the following sub-steps:

as shown in FIG. 1F, a first phosphorus ion implantation 104 is performed, and as shown in FIG. 1G, a first implantation region 4 is formed after the first phosphorus ion implantation 104 is completed, preferably, the implantation energy of the first phosphorus ion implantation 104 is 100 KeV-300 KeV, and the implantation dose is 1 × 10¹³cm^-2～1×10¹⁴cm^-2。

As shown in FIG. 1H, performing a second xenon ion implantation 105, and as shown in FIG. 1I, forming a second implantation region 5 after the second xenon ion implantation 105 is completed, wherein the implantation energy of the second xenon ion implantation 105 is 1 KeV-100 KeV, and the implantation dose is 1 × 10¹⁴cm^-2～1×10¹⁶cm^-2。

Performing a third arsenic ion implantation 106 as shown in FIG. 1J, and forming a third implantation region 6 after the third arsenic ion implantation 106 is completed as shown in FIG. 1K, wherein the implantation energy of the third arsenic ion implantation 106 is 1 KeV-80 KeV, and the implantation dose is 1 × 10¹²cm^-2～1*10¹⁴cm^-2。

As shown in fig. 1K, an overlap region 7 is formed by the first implantation region 4, the second implantation region 5 and the third implantation region 6, and the overlap region 7 is located in the N-type deep well 2.

The junction depth of the first implanted region 4 is greater than the junction depth of the second implanted region 5, and the junction depth of the first implanted region 4 is also greater than the junction depth of the third implanted region 6.

The doping concentration of the third implantation region 6 is used for adjusting the threshold voltage, and before the third arsenic ion implantation 106, the second xenon ion implantation 105 forms an amorphization layer in the semiconductor substrate 101, and the amorphization layer makes the third arsenic ion implantation 106 uniform so as to reduce the fluctuation of the threshold voltage.

Step four, as shown in fig. 1L, annealing the overlap region 7 to form the N well 8.

In the method of the embodiment of the invention, the annealing temperature of the superposition area 7 is 1000-1300 ℃.

And step five, as shown in fig. 1L, removing the sacrificial oxide layer 3.

In the method of the embodiment of the invention, the sacrificial oxide layer 3 is removed by adopting a wet etching or plasma etching process.

And step six, forming a gate structure on the semiconductor substrate 101.

The grid structure comprises a layer of superposed grid dielectric layer and a grid conducting material layer.

The gate dielectric layer is made of silicon oxide, silicon oxynitride or a high-dielectric-constant material; the high dielectric constant material includes hafnium oxide.

The grid electrode conducting material layer is a polysilicon grid or a metal grid.

Seventhly, performing source-drain injection in the N wells 8 at two sides of the grid structure to form a source region and a drain region; the channel region is composed of the N-well 8 covered by the gate structure, and is located between the source region and the drain region.

Further comprising:

and step eight, forming metal silicide, an interlayer film, a contact hole, a through hole and a front metal layer.

Preferably, the metal silicide is nickel silicide, the contact hole is a tungsten-filled contact hole, the through hole is a tungsten through hole, and the front metal layer is of a copper interconnection structure.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.