阅读说明：本技术 一种图形图像联合优化的光刻掩模优化方法、装置及电子设备 (Photoetching mask optimization method and device for joint optimization of graphic images and electronic equipment ) 是由 丁明 施伟杰 于 2019-02-15 设计创作，主要内容包括：本发明涉及集成电路掩模设计领域,尤其涉及一种图形图像联合优化的光刻掩模优化方法、装置及电子设备。所述方法包括步骤：输入主图形；对主图形的边进行分割得到短边,以短边作为主图形优化的第一变量；在相同或者相似的主图形的周围生成相同或者相似的辅助图形采样点,以辅助图形采样点作为主图形优化的第二变量；提供以第一变量和第二变量作为优化变量的目标函数,在每个主图形的周围生成辅助图形采样点的规则是一样的,不受限于主图形的具体位置,保证最终对每个主图形优化的结果的一致性。(The invention relates to the field of integrated circuit mask design, in particular to a photoetching mask optimization method and device for combined optimization of graphic images and electronic equipment. The method comprises the following steps: inputting a main graph; dividing the side of the main graph to obtain a short side, and taking the short side as a first variable for optimizing the main graph; generating the same or similar auxiliary graph sampling points around the same or similar main graphs, and taking the auxiliary graph sampling points as second variables of the main graph optimization; the objective function with the first variable and the second variable as optimization variables is provided, the rules for generating the auxiliary graph sampling points around each main graph are the same, the rules are not limited by the specific positions of the main graphs, and the consistency of the final optimization result of each main graph is ensured.)

1. A method of optimizing a lithographic mask for joint optimization of a pattern image, for optimizing an initial mask, said initial mask comprising at least one main pattern, comprising the steps of:

s1, inputting a main graph;

s2, dividing the side of each main pattern to obtain a short side, and taking the short side as a first variable for optimizing the main patterns;

s3, generating the same or similar auxiliary graph sampling points around the same or similar main graphs, and taking the auxiliary graph sampling points as second variables of main graph optimization;

and S4, providing an objective function with the first variable and the second variable as optimization variables.

2. The method for optimizing a photolithographic mask jointly optimized for graphic images as claimed in claim 1, characterized in that: in the above step S4, the objective function is defined as:

wherein E is a first variable, P is a second variable, wi is the weight of each monitoring point, the monitoring points are a plurality of points arranged on the main pattern and used for evaluating imaging errors, and RI is the intensity of the pattern on the photoresist.

3. The method for optimizing a photolithographic mask jointly optimized for graphic images as claimed in claim 2, characterized in that: the obtaining of the RI comprises the following steps:

s41, rasterizing a mask to be optimized to obtain a rasterized mask image MI, wherein the mask to be optimized comprises an initial mask and a mask after each iteration;

s42, converting the lattice mask image MI into an exposure dose distribution diagram AI;

and S43, obtaining RI through AI calculation of the exposure dose distribution map.

4. A method of optimizing a lithographic mask by joint optimization of graphic images as claimed in claim 3, characterized in that: the above step S41 includes calculating to obtain the rasterized mask image MI with the first variable and the auxiliary pattern sample point information as input values.

5. The graphical image joint optimization light of claim 4

The etching mask optimization method is characterized by comprising the following steps: the above-mentioned

MI(r)＝MI(r,E,P)＝MI₁(r,E)+MI₂(r,P)，

Wherein MI₁(r, E) is obtained by calculating the calculation method from the mask to be optimized to the lattice mask image, and is obtained by performing convolution operation on the mask image determined by E, and MI is₂(r, P) is obtained by interpolation

r is the position coordinate of each main pattern, and the auxiliary pattern sampling point information comprises: the signal value Pj at the jth auxiliary pattern sampling point and the position r (Pj) of the jth auxiliary pattern sampling point, wherein j is 1, 2 and 3 … n, and n is an integer greater than zero.

6. The method for optimizing a photolithographic mask jointly optimized for graphic images as claimed in claim 1, characterized in that: in step S3, an auxiliary pattern generation region is formed around each main pattern, and an auxiliary pattern sampling point is generated in the auxiliary pattern generation region according to a preset rule, which specifically includes the following steps:

s31, setting a minimum variable x1 formed by the auxiliary pattern placement area and a maximum variable x2 formed by the auxiliary pattern placement area;

s32, enlarging the main graph by x1 to obtain a graph A, and enlarging the main graph by x2 to obtain a graph B;

s33, carrying out XOR operation on the graph A and the graph B to obtain the auxiliary graph placement area; and

and S34, generating auxiliary pattern signal sampling points in the auxiliary pattern placement area.

7. The method of optimizing a photolithographic mask jointly optimized for graphic images as recited in claim 6, wherein: dividing the auxiliary graph placement area into a plurality of rectangular blocks, and generating signal sampling points in each rectangular block according to a preset generating distance; the closest distance between the side of the generated pattern A and the side of the main pattern is d1, the closest distance between the side of the generated pattern B and the side of the main pattern is d2, the numerical range of d1 is 20-100 nm, and the numerical range of d2 is 100-400 nm.

8. The method for optimizing a photolithographic mask jointly optimized for graphic images as claimed in claim 1, characterized in that: the method for optimizing a lithography mask by combining and optimizing pattern images further includes step S5, optimizing the objective function by an optimization algorithm to obtain an auxiliary pattern generating point where an auxiliary pattern should be placed in the auxiliary pattern placement region and a displacement size of each short side movement, where the optimization process is performed based on an inverse lithography technique, and the optimization process includes the following two stages:

the first stage is as follows: optimizing the main graph by taking the short side of the main graph as an optimization variable to obtain an initial optimization main graph;

and a second stage: and optimizing the initial optimization main graph by taking the combination of the short sides of the main graph and the auxiliary graph sampling points as optimization variables to further obtain auxiliary graph generating points where auxiliary graphs should be placed in the auxiliary graph placement area and the displacement size of the movement of each short side.

9. A lithographic mask optimization device for joint optimization of a pattern and an image, characterized by: it includes:

an input module: configured to input a master graphic;

cutting the module: configuring a main graph for dividing the side of the main graph to obtain a short side;

an auxiliary graphic placement area generation module: configuring an auxiliary pattern placement area around the main pattern;

an auxiliary pattern sampling point generation module: configuring an auxiliary pattern sampling point in the auxiliary pattern placement area;

an objective function generation module: the method comprises the steps of configuring an objective function which takes a first variable and a second variable as optimization variables; and

an optimization calculation module: and optimizing the objective function based on an inverse lithography technique to obtain an assist pattern generation point at which an assist pattern should be placed in the assist pattern placement area and a displacement size of the movement of each short side.

10. An electronic device, characterized in that: comprising one or more processors;

a storage device for storing one or more programs,

when executed by the one or more processors, cause the one or more processors to implement the method of any one of claims 1-8.

[ technical field ] A method for producing a semiconductor device

The invention relates to the field of integrated circuit mask design, in particular to a photoetching mask optimization method and device for combined optimization of graphic images and electronic equipment.

[ background of the invention ]

Photolithography is one of the most important parts of the integrated circuit fabrication process, and determines the degree of advancement of the integrated circuit fabrication process. A lithography system is generally described as an optical imaging system comprising four basic elements, an illumination source, a mask, a projection objective system and a silicon wafer coated with a photoresist. As the critical dimensions of integrated circuits enter the 45nm technology node and continue to move toward smaller 32nm and even 22nm nodes, the size of the pattern to be exposed is much smaller than the wavelength of the light source in the lithography system. In this case, optical proximity Effects (optical proximity Effects) caused by interference and diffraction Effects of optical waves in the lithography imaging system become more and more significant. This causes the exposure pattern formed on the silicon wafer to be greatly deformed as compared with the mask pattern used, and therefore, when actually designing a mask for a lithography system, it is necessary to consider such an optical proximity effect and previously process the mask pattern so that the exposure pattern obtained on the silicon wafer is closer to the target pattern.

In the existing mask optimization process, the mask is usually required to be subjected to gridding processing, and the final optimization result is limited by the regularity of grid point positions. When the same main pattern is located at different positions of the grid points, the number and the relative positions of the grid points of the auxiliary pattern obtained around the main pattern are different, so that the finally obtained optimized mask pattern is not ideal. As shown in fig. 1A and 1B, including similar main pattern X1 and main pattern X2, the auxiliary pattern grid point generating regions correspond to M1 and M2, and when the main pattern X1 and the main pattern X2 are located at different positions, for example, a larger difference exists between a point O1 close to the vertex P of the main pattern X1 and a point O2 close to the point P2 of the main pattern X2, and if the auxiliary pattern is placed at the points O1 and O2, the main pattern will be affected differently.

[ summary of the invention ]

The invention provides a photoetching mask optimization method and device for jointly optimizing a graphic image and electronic equipment, aiming at solving the problem that the imaging of an optimized mask plate is not ideal due to the fact that the existing mask optimization technology is limited by the influence of lattice point positions.

In order to solve the above technical problem, the present invention provides a method for optimizing a lithography mask by jointly optimizing pattern images, which is used for optimizing an initial mask, wherein the initial mask comprises at least one main pattern, and the method comprises the following steps: s1, inputting a main graph; s2, dividing the side of each main pattern to obtain a short side, and taking the short side as a first variable for optimizing the main patterns; s3, generating the same or similar auxiliary graph sampling points around the same or similar main graphs, and taking the auxiliary graph sampling points as second variables of main graph optimization; and S4, providing an objective function with the first variable and the second variable as optimization variables.

Preferably, in the above step S4, the objective function is defined as:

wherein E is a first variable, P is a second variable, and w_iAnd weighting each monitoring point, wherein the monitoring points are a plurality of points which are arranged on the main graph and used for evaluating imaging errors, and the RI is the intensity of the pattern on the photoresist.

Preferably, the obtaining of the RI comprises the steps of: s41, rasterizing a mask to be optimized to obtain a rasterized mask image MI, wherein the mask to be optimized comprises an initial mask and a mask after each iteration; s42, converting the lattice mask image MI into an exposure dose distribution diagram AI; and S43, obtaining RI through AI calculation of the exposure dose distribution map.

Preferably, the step S41 includes calculating to obtain the lattice-formatted mask image MI by using the first variable and the auxiliary pattern sampling point information as input values.

Preferably, the

MI(r)＝MI(r,E,P)＝MI₁(r,E)+MI₂(r,P)，

Wherein MI₁(r, E) is obtained by calculating the calculation method from the mask to be optimized to the lattice mask image, and is obtained by performing convolution operation on the mask image determined by E, and MI is₂(r, P) is obtained by interpolation

r is the position coordinate of each main pattern, and the auxiliary pattern sampling point information comprises: signal value P at jth auxiliary pattern sampling point_jAnd the position r (P) of the jth auxiliary pattern sampling point_j) And j is 1, 2, 3 … n, and n is an integer greater than zero.

Preferably, in step S3, an auxiliary pattern generating region is formed around each main pattern, and an auxiliary pattern sampling point is generated in the auxiliary pattern generating region according to a preset rule, including the following steps: the step S3 specifically includes the following steps: s31, setting a minimum variable x1 formed by the auxiliary graph generating area and a maximum variable x2 formed by the auxiliary graph generating area; s32, enlarging the main graph by x1 to obtain a graph A, and enlarging the main graph by x2 to obtain a graph B; s33, carrying out XOR operation on the graph A and the graph B to obtain the auxiliary graph generation area; and S34, generating auxiliary pattern signal sampling points in the auxiliary pattern generation area.

Preferably, the auxiliary graph generation region is divided into a plurality of rectangular blocks, and a signal sampling point is generated in each rectangular block according to a preset generation distance; the closest distance between the side of the generated pattern A and the side of the main pattern is d1, the closest distance between the side of the generated pattern B and the side of the main pattern is d2, the numerical range of d1 is 20-100 nm, and the numerical range of d2 is 100-400 nm.

Preferably, the method for optimizing a lithography mask by combining and optimizing pattern images further includes step S5, optimizing the objective function by an optimization algorithm to obtain an auxiliary pattern generation point at which an auxiliary pattern should be generated in the auxiliary pattern generation area and a displacement size of each short edge movement, wherein the optimization process is performed based on an inverse lithography technique, and the optimization process includes the following two stages: the first stage is as follows: optimizing the main graph by taking the short side of the main graph as an optimization variable to obtain an initial optimization main graph; and a second stage: optimizing the initial optimized main pattern with a combination of the short sides of the main pattern and the auxiliary pattern sampling points as optimization variables to further obtain auxiliary pattern generation points at which auxiliary patterns should be generated within the auxiliary pattern generation area and a displacement size of movement of each short side.

The present invention further provides a mask aligner for optimizing a mask pattern by combining a pattern image, comprising: an input module: configured to input a master graphic; cutting the module: configuring a main graph for dividing the side of the main graph to obtain a short side; an auxiliary graphic placement area generation module: configuring an auxiliary pattern placement area around the main pattern; an auxiliary pattern sampling point generation module: configuring an auxiliary pattern sampling point in the auxiliary pattern placement area; an objective function generation module: the method comprises the steps of configuring an objective function which takes a first variable and a second variable as optimization variables; and an optimization calculation module: and optimizing the objective function based on an inverse lithography technique to obtain an assist pattern generation point at which an assist pattern should be placed in the assist pattern placement area and a displacement size of the movement of each short side.

The present invention further provides an electronic device, which includes one or more processors; storage means for storing one or more programs which, when executed by the one or more processors, cause the one or more processors to carry out any of the methods described above.

Compared with the prior art, the same or similar auxiliary graph sampling points are generated around the same or similar main graphs, so that the generated auxiliary graph sampling points are not different due to different specific positions of the main graphs, different auxiliary graph sampling points are generated around the same or similar main graphs without being limited by the rule of grid points, the situation that the auxiliary graphs are finally placed according to the auxiliary graph sampling points are greatly different is avoided, the situation that the optimization results of the same main graphs have larger deviation is avoided, and the final optimization effect of the mask is improved.

In the target function, the auxiliary graph sampling point information is used as an optimization variable, a signal value of each auxiliary graph sampling point can be obtained well according to the optimization algorithm-based process of optimizing the target function, the auxiliary graph sampling points where the auxiliary graphs can be placed are obtained according to the size of the signal values, and therefore the result preparation is reliable, and a good optimization effect is obtained.

In the process of optimizing the objective function, the optimization is divided into two stages, the first stage is based on the limit of the main graph, namely, the first variable is optimized to the main graph, the main graph can be optimized preliminarily, the influence of the optical proximity effect is reduced preliminarily, in the second stage, the main graph which is optimized preliminarily is further optimized by combining the first variable and the second variable, the signal value of the auxiliary graph sampling point used for placing the auxiliary graph obtained after the final optimization is more accurate, and meanwhile, the displacement of the main graph is more accurate.

The photoetching mask optimizing device and the electronic equipment for the combined optimization of the graphic images have the same beneficial effects as the photoetching mask optimizing method for the combined optimization of the graphic images.

[ description of the drawings ]

FIG. 1A is a schematic diagram of a main diagram in the background of the invention;

FIG. 1B is a schematic diagram of a main graph with different positions relative to the grid of FIG. 1A in the background art of the present invention;

FIG. 1C is a schematic flow chart of a method for optimizing a photolithographic mask by jointly optimizing a pattern and an image according to a first embodiment of the present invention;

FIG. 2 is a schematic diagram of an initial mask structure in a lithography mask optimization method for joint optimization of graphic images according to a first embodiment of the present invention;

FIG. 3 is a schematic diagram of the main pattern edge segmentation in the lithography mask optimization method for joint optimization of pattern images according to the first embodiment of the present invention;

FIG. 4 is a flowchart showing details of step S3 in the method for optimizing a photolithographic mask by jointly optimizing graphic images provided in the first embodiment of the present invention;

FIG. 5 is a schematic diagram of an auxiliary pattern sampling point placement area in a lithography mask optimization method for joint optimization of pattern images according to a first embodiment of the present invention;

FIG. 6 is a schematic diagram of auxiliary pattern sampling points generated in the optimization method of a lithography mask by joint optimization of pattern images provided in the first embodiment of the present invention;

FIG. 7 is a flowchart showing details of step S4 in the method for optimizing a photolithographic mask by jointly optimizing graphic images provided in the first embodiment of the present invention;

FIG. 8 is a schematic diagram illustrating the structure of an initial mask in the method for optimizing a lithography mask by jointly optimizing graphic images according to the first embodiment of the present invention;

FIG. 9 is a schematic diagram of auxiliary pattern sampling points generated in the lithography mask optimization method for joint optimization of pattern images provided in the first embodiment of the present invention;

FIG. 10 is a schematic diagram of a main pattern optimized in a lithography mask optimization method for joint optimization of pattern images according to a first embodiment of the present invention;

FIG. 11 is a schematic diagram of an optimized auxiliary pattern in the optimization method of a lithography mask by joint optimization of pattern images according to the first embodiment of the present invention;

FIG. 12 is a schematic diagram of an optimized resist image in a lithography mask optimization method with joint optimization of pattern images provided in the first embodiment of the present invention;

FIG. 13 is a block diagram of a lithographic mask optimization apparatus for joint optimization of a pattern image provided in a second embodiment of the present invention;

fig. 14 is a block schematic diagram of an electronic apparatus provided in a third embodiment of the present invention;

FIG. 15 is a schematic block diagram of a computer system suitable for use with a server implementing an embodiment of the invention.

[ detailed description ] embodiments

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Referring to fig. 1C, a first embodiment of the present invention provides a method for optimizing a lithography mask by jointly optimizing a pattern image, the method being used for optimizing an initial mask, the initial mask including at least one main pattern, the method including the steps of:

s1, inputting a main graph;

in the invention, a design pattern of a target chip is provided firstly, a mask corresponding to the design pattern of the target chip is designed according to the design pattern of the target chip, and the mask is laid according to the photoetching requirement of the design pattern of the target chip. That is, the initially designed mask corresponds to an initial mask including at least one main pattern thereon. In this step, if fig. 2 is an initial mask, the region M is a main pattern. The main pattern is also commonly referred to as an exposure pattern, which is transferred to the semiconductor device after exposure. In this embodiment, the region M is a rectangle, and in other embodiments, the main pattern may be other patterns, which mainly depend on the specific shape of the initial mask, such as a trapezoid, an irregular polygon, a regular polygon, and other patterns. Optionally, the input main graphic exists in GDS format.

Referring again to fig. 1C, a method for optimizing a lithography mask by jointly optimizing a pattern and an image further includes the steps of:

s2, dividing the side of each main pattern to obtain a short side, and taking the short side as a first variable for optimizing the main patterns;

referring to fig. 3, the edge of the main pattern is mainly cut into short edges of small line segments, each short edge is marked as a different type according to different positions of the short edge, and the short edges at different positions are used as basic units for processing in the optimization process to obtain different optimization variables. The cutting treatment enables the corrected object to be more definite, single and accurate, and the problem that the situation is too complex when the main graph is integrally optimized is solved. In this step, the correction strategy with the short edge as the first variable to optimize is mainly the movement of the corresponding line segment. And selecting different moving directions and different moving step lengths according to the difference of different line segment positions and the imaging characteristics of patterns on the photoresist, stepping sequentially, and performing repeated iteration operation until a final optimization result is obtained.

Referring again to fig. 1C, a method for optimizing a lithography mask by jointly optimizing a pattern and an image further includes the steps of:

s3, generating the same or similar auxiliary graph sampling points around the same or similar main graphs, and taking the auxiliary graph sampling points as second variables of main graph optimization;

in order to eliminate the effect of the Optical Proximity effect, the main pattern on the initial mask is not the same as the desired lithography pattern, and the main pattern needs to be processed by Optical Proximity Correction (OPC), and furthermore, as the feature size enters the 90nm range, the line width of the main pattern is even 1/3 which is only the wavelength of light, besides the necessary Optical Proximity Correction process, it is usually necessary to set a Sub-sized auxiliary pattern around the main pattern, i.e. Sub-resolution auxiliary pattern technology (SRAF). The auxiliary patterns are only arranged on the photoetching mask plate, the patterns are not transferred to the semiconductor device after actual exposure, and the effects of increasing the focusing depth of the adjacent main patterns and improving the exposure accuracy are achieved. Therefore, in this step, the auxiliary pattern placement area is an area for placing an auxiliary pattern. In this step, the same or similar main pattern is understood to be a main pattern with the same or similar shape and size, such as a positive direction, rectangle, trapezoid or other irregular pattern with the same size. For another example, if one main pattern is a square and the other main pattern is a pattern that approximates to a square, the two patterns are considered to be similar. Referring to fig. 4, as an embodiment, the step S3 specifically includes the following steps:

s31, setting a minimum variable x1 formed by the auxiliary pattern placement area and a maximum variable x2 formed by the auxiliary pattern placement area;

in this step, the minimum variable x1 and the maximum variable x2 are expansion coefficients of the main graph, respectively, wherein the minimum variable x1 is less than or equal to the maximum variable x2, the minimum variable x1 is greater than or equal to zero, and the maximum variable x2 is not equal to zero.

Referring to fig. 4 again, step S3 further includes the following steps:

s32, enlarging the main graph by x1 to obtain a graph A, and enlarging the main graph by x2 to obtain a graph B; the setting of the minimum variable x1 and the maximum variable x2 may be performed as follows: the closest distance between the side of the generated pattern A and the side of the main pattern is d1, the closest distance between the side of the generated pattern B and the side of the main pattern is d2, specifically, the numerical range of d1 is 20-100 nm, and the numerical range of d2 is 100-400 nm.

In this step, the pattern a and the pattern B are shown in fig. 5.

Referring to fig. 5 again, step S3 further includes the following steps:

s33, carrying out XOR operation on the graph A and the graph B to obtain the auxiliary graph placement area;

in this step, the auxiliary pattern placement area, i.e., the area C formed by the edges of the pattern a and the pattern B, i.e., the corresponding filling area in fig. 5, is shown, and the outline of the auxiliary pattern placement area is consistent with the outline of the main pattern.

Referring to fig. 5 again, step S3 further includes the following steps:

and S34, generating auxiliary pattern signal sampling points in the auxiliary pattern placement area.

In this step, the auxiliary pattern signal sampling points are used as the second variable for the optimization of the main pattern. And after the auxiliary pattern signal sampling points are generated, giving each auxiliary pattern signal sampling point an initial signal value of 0, and in the optimization process, when the signal value of the auxiliary pattern signal sampling point exceeds a set threshold value, generating an auxiliary pattern at the position of the auxiliary pattern signal sampling corresponding to the point, otherwise, not placing the auxiliary pattern.

In this step, the auxiliary pattern sampling points are generated according to a preset rule. Specifically, the preset rule may be: and a plurality of rows of auxiliary pattern sampling points are arranged, the distance between any two adjacent auxiliary pattern sampling points in the same row is x, the row spacing of any two adjacent rows is also x, and the size of the x value can be adjusted according to the actual optimization effect in the specific optimization process.

In some other embodiments, in order to generate the auxiliary pattern sampling points more quickly and accurately, the auxiliary pattern placement area may be divided into a plurality of rectangular blocks, and the auxiliary pattern sampling points are generated at a set pitch x in each rectangular block.

Please refer to fig. 6, which shows the auxiliary pattern sampling points generated when d1 is 40nm and d2 is 120 nm. In fig. 6, the shape and size of each main pattern are consistent, and the positions of the main patterns are different, so that it can be seen that the arrangement of the auxiliary pattern sampling points outside each main pattern is the same, and is not influenced by the specific position of the main pattern, that is, the same or similar auxiliary pattern sampling points are generated around each main pattern.

Referring again to fig. 1C, a method for optimizing a lithography mask by jointly optimizing a pattern and an image further includes the steps of:

s4, providing an objective function with the first variable and the second variable as optimization variables; and

s5, optimizing the objective function by an optimization algorithm to obtain an auxiliary figure generation point where an auxiliary figure should be placed in the auxiliary figure placement area and the size and direction of the movement of each short side.

In step S4, as an embodiment, the objective function is defined as:

wherein E is a first variable, P is a second variable, and w_iFor the weight of each monitoring point, which is a plurality of points disposed on the side of the main figure for evaluating imaging errors, typically by calculating a mask that is iteratively optimized during the optimization processThe plate acquires a difference between the imaged pattern on the silicon wafer and the target pattern. Wherein the main pattern comprises the main pattern of the initial mask and the main pattern after each iteration. w is a_iAre values obtained based on human experience. The RI is the intensity of the pattern (Resist Image) on the photoresist.

Referring to fig. 7, the obtaining of the RI includes the following steps:

s41, rasterizing a mask to be optimized to obtain a rasterized mask image MI, wherein the mask to be optimized comprises an initial mask and a mask after each iteration;

in this step, in the step S41 described above including calculating with the first variable and the auxiliary pattern sample point information as input values to obtain the lattice-pixelated mask image MI, the definition MI may be expressed by the following expression:

MI(r)＝MI(r,E,P)＝MI₁(r,E)+MI₂(r,P)

where r is the position coordinate of each main pattern, specifically, it can be represented by a coordinate value at a vertex of the main pattern. Wherein MI₁The (r, E) is obtained by calculating the calculation method from the mask pattern to the grid point mask pattern, namely converting the mask pattern into a two-dimensional image. Specifically, the method can be obtained by performing convolution operation on the mask pattern determined by the first variable E, and specifically includes the following steps:

s411, obtaining a low-pass filter matrix (convolution kernel) through convolution operation;

s412, calculating each pixel point in the mask graph, calculating the product of the neighborhood pixel of each pixel point and the corresponding element of the low-pass filter matrix, and adding the values of the corresponding elements to obtain a characteristic value representing the position of the pixel, thereby forming a characteristic graph related to the mask graph.

It can be seen that the eigenvalues on the profile correspond to MI₁(r, E). It should be noted that, in this step, the convolution operation performed on the mask pattern determined by E is a commonly used image filtering convolution operation algorithm, and details are not described here.

In some specific embodiments, MI₂(rP) is calculated by interpolation, which can be expressed in particular by the expression:

where r is the position coordinate of each main pattern, specifically, it may be represented by a coordinate value at a vertex of the main pattern, Pj is a signal value at a jth auxiliary pattern sampling point, and r (Pj) is a position of the jth auxiliary pattern sampling point. As can be seen, the auxiliary pattern sampling point information includes: the method comprises the steps of obtaining a signal value Pj at a j-th auxiliary pattern sampling point, coordinate values r of each pixel of a mask pattern and positions r (Pj) of the j-th auxiliary pattern sampling point, wherein j is 1, 2 and 3 … n, and n is an integer larger than zero. In the subsequent optimization process, in the process of optimizing the objective function, an optimization algorithm is used for optimizing Pj, the initial value of Pj is 0, and in the optimization process, when the value of Pj exceeds a set threshold value, the auxiliary graph can be placed at the auxiliary graph sampling point corresponding to Pj.

Referring again to fig. 7, the obtaining of the RI further includes the following steps:

s42, converting the lattice mask image MI into an exposure dose distribution diagram AI;

in this step, AI is obtained mainly from TCC theory calculation of optical imaging, and specifically, AI can be expressed by the following expression:

in the formula, λ_lIs the intrinsic coefficient of the item l, h_lThe matrix coefficients are transmitted for the item l.

Specifically, the AI calculation mainly includes the following steps:

s421, calculating a cross transfer coefficient matrix;

s422, calculating a partial coherent kernel function;

and S423, calculating to obtain the exposure dose distribution diagram AI based on the partial coherence kernel function.

In step S421, the cross transfer coefficient matrix may be calculated by a conventional analytical method, an integral method, or a fourier transform method. The Fourier transform method can adapt to different types of light sources and has a faster calculation rate.

In step S422, the four-dimensional cross transfer coefficient matrix is first expressed as a two-dimensional matrix, and then eigenvalue decomposition is performed on the two-dimensional matrix to obtain the eigen coefficients and eigenvectors of the matrix. The calculated eigenvectors correspond to the partial coherence kernel function. In this step, the cross transfer coefficient matrix is subjected to eigenvalue decomposition mainly based on the optical imaging model Hopkins (Hopkins statistic), and the first l terms are retained, each term being represented by an eigen coefficient and an eigenvector (transmission matrix coefficient). Thus obtaining the i term eigen coefficient lambda_lAnd the l item transmission matrix coefficient h_l。

The first l term that remains is the value that has a large impact on the result, while the last l term is substantially close to zero and can therefore be ignored.

In step S423, the eigen coefficients of the aerial image calculated by using the coherent imaging model for each kernel function obtained in step S422 are weighted and summed to obtain an exposure dose distribution map AI.

Referring again to fig. 7, the obtaining of the RI further includes the following steps:

and S43, obtaining RI through AI calculation of the exposure dose distribution map.

In this step, the RI can be obtained starting from the exposure dose profile AI and taking into account some chemical effects of the resist.

In some embodiments, the RI may be obtained by, for example, the following function:

in the formula, θ is a constant representing the length scale of the diffusion effect, and threshold is a cutoff constant, i.e. a set threshold.

Referring again to fig. 1C, a method for optimizing a lithography mask by jointly optimizing a pattern and an image further includes the steps of:

s5, optimizing the objective function by an optimization algorithm to obtain an auxiliary figure generation point at which an auxiliary figure should be generated within the auxiliary figure generation area and a displacement size of the movement of each short side.

In the step, the optimization algorithm comprises a conjugate gradient method, a quasi-Newton method, L-BFGSB and other optimization methods.

Specifically, in the optimization process, the first derivatives of the first variable and the second variable to the objective function Cost need to be calculated.

The specific calculation process of the first derivative is as follows:

1)

2)

wherein, in formula 2), exceptExcept for this, the calculation of the remaining equations is the same as the conventional procedure of I L T (Inverse lithography, Inverse L iterative Technology), and will not be described herein again.

In the present embodiment, an L-BFGSB algorithm is mainly used for illustration, a group of square M with a width of 62nm and a period of 409nm as shown in fig. 8 is used as a main pattern input, as shown in fig. 9, auxiliary pattern sampling points are generated in the range of [40nm, 120nm ] in the main pattern M, and it can be clearly seen that the number and relative positions of the auxiliary pattern sampling points generated around the main pattern are consistent and are not affected by a specific grid.

Meanwhile, in the present embodiment, a plurality of exposure conditions were used for the test, specifically including standard exposure conditions (NC), exposure dose + 3% (PD3), exposure dose-3% (ND3), defocus +40nm (PF40), defocus-40 nm (NF 40). The standard exposure condition means that the photoetching machine is in an ideal working state, namely the exposure value is at a set standard value, the lens is focused on the set standard value, and no deviation exists.

The optimization process is mainly divided into a first stage and a second stage:

the first stage is as follows: and optimizing the main graph by taking the short side of the main graph as an optimization variable. The exposure dose distribution diagram AI of the initial mask is calculated, the objective function is calculated according to the required pattern and the calculated exposure dose distribution diagram AI, the specific calculation process is as the above steps S41-S43, which is not repeated herein, so that the position of the upper edge of the mask is adjusted to obtain the next mask, then the exposure dose distribution diagram AI is continuously calculated, the objective function is calculated again to adjust the mask, and the steps are repeated, and finally the design mask after the initial optimization is obtained when the objective function reaches a smaller value. Optionally, the number of iterations in this stage is 15. As shown in fig. 10, the dashed line box is the main graph after optimization.

And a second stage: the combination of the short edge of the main graph and the auxiliary graph sampling point is used as an optimization variable, in the phase, the edge of the main graph moves, and meanwhile, the signal value of the auxiliary graph sampling point is used as a result for feedback, namely when the edge of the main graph moves, the signal value of the corresponding auxiliary graph sampling point is also larger than a set threshold value, and then the auxiliary graph sampling point where the auxiliary graph needs to be placed is obtained. In this stage, an auxiliary graphic acquisition point where an auxiliary graphic can be placed is obtained through 30 iterations. As shown in fig. 11, is the optimized auxiliary image.

It can be seen that the optimization in the second stage is based on what has been done after the primary optimization of the primary pattern in the first stage.

The result of the combined optimization of the pattern images in this embodiment is calculated, and the resist image is obtained as shown in fig. 12, and statistical analysis is performed on EPE (edge positioning error) and pvhand (distribution width of EPE when a certain detection point is under different exposure conditions) to obtain the following values:

exposure conditions	Maximum EPE(nm)
		NC	0.50
PD3	1.59
		ND3	1.15
PF40	1.75
		NF40	0.77

Here, the EPE is an error between the edge of the pattern on the silicon wafer calculated by the objective function and the actually required pattern (target pattern).

Pvband refers to the width of the EPE distribution under different exposure conditions.

Maximum Pvband＝2.97nm。

Therefore, the photoetching mask optimization method based on the graphic image joint optimization provided by the invention has a better optimization effect.

Referring to fig. 13, a second embodiment of the present invention provides a combined optimization apparatus 200 for graphics and images, which includes an input module 201, a cutting module 202, an auxiliary graphics placement region generating module 203, an auxiliary graphics sampling point generating module 204, an objective function generating module 205, and an optimization calculating module 206.

An input module 201 configured to input a main graphic;

a cutting module 202 configured to segment the side of the main pattern to obtain a short side;

an auxiliary graphic placement area generation module 203 configured to form an auxiliary graphic placement area around the main graphic;

an auxiliary pattern sampling point generating module 204 configured to generate auxiliary pattern sampling points in the auxiliary pattern placement region;

an objective function generation module 205 configured to provide an objective function with the first variable and the second variable as optimization variables; and

an optimization calculation module 206 configured to optimize the objective function based on an inverse lithography technique to obtain an assist pattern generation point where an assist pattern should be placed in the assist pattern placement area and a displacement size of each short side movement.

Referring to fig. 14, a third embodiment of the invention provides an electronic device 300, which includes one or more processors 302;

a storage 301 for storing one or more programs,

when executed by the one or more processors 302, cause the one or more processors 302 to implement any of the steps of the model-based data processing method as provided by the first implementation.

Referring now to FIG. 15, a block diagram of a computer system 800 suitable for use with a terminal device/server implementing an embodiment of the present invention is shown. The terminal device/server shown in fig. 15 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present application.

As shown in fig. 15, the computer system 800 includes a Central Processing Unit (CPU)801 that can perform various appropriate actions and processes in accordance with a program stored in a Read Only Memory (ROM)802 or a program loaded from a storage section 808 into a Random Access Memory (RAM) 803. In the RAM 803, various programs and data necessary for the operation of the system 800 are also stored. The CPU 801, ROM 802, and RAM 803 are connected to each other via a bus 804. An input/output (I/O) interface 805 is also connected to bus 804.

To the I/O interface 805, AN input section 806 including a keyboard, a mouse, and the like, AN output section 807 including a network interface card such as a Cathode Ray Tube (CRT), a liquid crystal display (L CD), and the like, a speaker, and the like, a storage section 808 including a hard disk, and the like, and a communication section 809 including a network interface card such as a L AN card, a modem, and the like are connected, the communication section 809 performs communication processing via a network such as the internet, a drive 810 is also connected to the I/O interface 805 as necessary, a removable medium 811 such as a magnetic disk, AN optical disk, a magneto-optical disk, a semiconductor memory, and the like is mounted on the drive 810 as necessary, so that a computer program read out therefrom is mounted into the storage section 808 as.

According to an embodiment of the present disclosure, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method illustrated in the flow chart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication section 809 and/or installed from the removable medium 811. The computer program performs the above-described functions defined in the method of the present invention when executed by the Central Processing Unit (CPU) 801. It should be noted that the computer readable medium of the present invention can be a computer readable signal medium or a computer readable storage medium or any combination of the two. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples of the computer readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Computer program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including AN object oriented programming language such as Java, Smalltalk, C + +, and conventional procedural programming languages, such as the "C" programming language or similar programming languages.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

The units described in the embodiments of the present invention may be implemented by software or hardware. The described units may also be provided in a processor, and may be described as: a processor comprises an input module, a cutting module, an auxiliary graph placement area generation module, an auxiliary graph sampling point generation module, an objective function generation module and an optimization calculation module. Where the names of the cells do not in some cases constitute a limitation on the cells themselves, for example, the input module may also be described as "for inputting a master graphic". As another aspect, the present invention also provides a computer-readable medium, which may be contained in the apparatus described in the above embodiments; or may be present separately and not assembled into the device. The computer readable medium carries one or more programs which, when executed by the apparatus, cause the apparatus to: dividing the side of the main graph to obtain a short side based on the input main graph, forming an auxiliary graph placing area around the main graph by taking the short side as a first variable for optimizing the main graph, generating auxiliary graph sampling points in the auxiliary graph placing area according to a preset rule, and taking the auxiliary graph sampling points as a second variable for optimizing the main graph; providing an objective function with a first variable and a second variable as optimization variables; and optimizing the objective function by an optimization algorithm to obtain an auxiliary pattern generation point where an auxiliary pattern should be placed within the auxiliary pattern placement area and a size and a direction of movement of each short side.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit of the present invention are intended to be included within the scope of the present invention.