阅读说明：本技术 缺陷图形特征参数的分析方法 (Method for analyzing characteristic parameters of defect pattern ) 是由 李萌 王英磊 曾鼎程 胡展源 于 2020-04-28 设计创作，主要内容包括：本发明公开了一种缺陷图形特征参数的分析方法,包括步骤：步骤一、进行晶圆的缺陷测试并提取各缺陷的第一坐标；步骤二、将各第一坐标转换为对应的版图上的第二坐标；步骤三、在版图上添加缺陷标记层,缺陷标记层在各第二坐标处形成一个对应的缺陷标记图形；步骤四、标记出版图中被分析图层与缺陷标记图形所接触的版图图形并作为版图缺陷图形；步骤五、获取版图缺陷图形的特征参数。本发明能提高缺陷图形特征参数的提取效率,并能实现对缺陷图形特征参数进行全面和准确的分析。(The invention discloses a method for analyzing characteristic parameters of a defect graph, which comprises the following steps: firstly, carrying out defect test on a wafer and extracting a first coordinate of each defect; step two, converting each first coordinate into a second coordinate on the corresponding layout; adding a defect marking layer on the layout, wherein the defect marking layer forms a corresponding defect marking graph at each second coordinate; marking a layout graph in the layout, which is contacted with the analyzed layer and the defect marking graph, and taking the graph as a layout defect graph; and fifthly, acquiring characteristic parameters of the layout defect graph. The invention can improve the extraction efficiency of the characteristic parameters of the defect pattern and can realize the comprehensive and accurate analysis of the characteristic parameters of the defect pattern.)

1. A method for analyzing defect pattern characteristic parameters is characterized by comprising the following steps:

firstly, carrying out defect testing on a wafer, and extracting a first coordinate of each defect when the defect is obtained through testing, wherein the first coordinate is a coordinate of the defect on the wafer;

converting each first coordinate into a corresponding second coordinate, wherein the second coordinate is a coordinate corresponding to the first coordinate on the layout;

adding a defect marking layer on the layout, wherein the defect marking layer forms a corresponding defect marking graph at each second coordinate;

step four, the layout comprises a plurality of layers, the layer needing defect analysis is an analyzed layer, other layers except the analyzed layer are related layers, and the layout graph contacted by the analyzed layer and the defect marking graph in the layout is marked and used as a layout defect graph;

and fifthly, acquiring characteristic parameters of the layout defect graph.

2. The method for analyzing the characteristic parameters of the defect pattern as claimed in claim 1, wherein:

the test machines for performing the defect test in the first step include a K L a test machine, a TEM machine and a CDSEM machine.

3. The method for analyzing the characteristic parameters of the defect pattern as claimed in claim 1, wherein: the third step comprises the following sub-steps:

step 31, calculating the vertex coordinates of the corresponding defect marking graph on the basis of the second coordinates;

and step 32, forming the defect mark graph corresponding to the defect mark layer on the layout according to the vertex coordinates of the defect mark graph.

4. The method for analyzing the characteristic parameters of the defect pattern as set forth in claim 3, wherein: the defect mark pattern is formed using OPC software in step 32.

5. The method for analyzing the characteristic parameters of the defect pattern as claimed in claim 1, wherein: and in the fourth step, OPC software is adopted to mark to form the layout defect graph.

6. The method for analyzing the characteristic parameters of the defect pattern as claimed in claim 1, wherein: and fifthly, acquiring the characteristic parameters of the layout defect graph by adopting OPC software.

7. The method for analyzing the characteristic parameters of the defect pattern as set forth in claim 3, wherein: the second coordinate is the center of the defect marking graph; or, the second coordinate is not the center of the defect mark pattern.

8. The method for analyzing the characteristic parameters of the defect pattern as claimed in claim 3 or 7, wherein: the defect marking graph is a regular graph or an irregular graph generated on the basis of the vertex coordinates of the defect marking graph.

9. The method for analyzing the characteristic parameters of the defect pattern as set forth in claim 8, wherein: the regular graph includes a polygon and a curve graph.

10. The method for analyzing the characteristic parameters of the defect pattern as set forth in claim 8, wherein: and determining the size information of the defect marking graph according to the error range of the first coordinate measured by the testing machine for the defect test.

11. The method for analyzing the characteristic parameters of the defect pattern as set forth in claim 10, wherein: the size information of the defect mark pattern comprises the length of the corresponding line and the size of the enclosed area.

12. The method for analyzing the characteristic parameters of the defect pattern as claimed in claim 1, wherein: in the fifth step, the characteristic parameters of the layout defect graph comprise: the length, the width and the spacing of the layout defect graphs and the spacing and the surrounding value of the layout defect graphs and the layout graphs of the adjacent related layers.

13. The method for analyzing the characteristic parameters of the defect pattern as set forth in claim 12, wherein: and part of the defects is layout related defects.

14. The method for analyzing the characteristic parameters of the defect pattern as set forth in claim 13, wherein: the fifth step is followed by the steps of:

carrying out statistical analysis on the characteristic parameters of the layout defect graph;

determining two groups of specification parameters according to statistical analysis, wherein the first group of specification parameters are characteristic parameters of a layout graph to be modified and are used for capturing the layout defect graph corresponding to the layout related defects in the analyzed layer of the layout; the second group of specification parameters are target values which need to be modified by the layout defect graphs corresponding to the layout related defects and are taken as modification targets of the captured layout defect graphs;

finding the layout defect graphs corresponding to all the layout related defects according to the first group of specification parameters;

and performing OPC modification on the captured corresponding layout defect graph according to the second group of specification parameters to eliminate or reduce the layout related defects.

15. The method for analyzing the characteristic parameters of the defect pattern as set forth in claim 14, wherein: and in OPC modification, modifying the characteristic parameters of the corresponding layout defect graph into the range of the second group of specification parameters.

16. The method for analyzing the characteristic parameters of the defect pattern as set forth in claim 14, wherein: the statistical analysis is based on the length, width or spacing of the layout defect pattern itself.

17. The method for analyzing the characteristic parameters of the defect pattern as claimed in claim 1, wherein: the wafer comprises a monocrystalline silicon wafer.

Technical Field

The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for analyzing characteristic parameters of a defect pattern.

Background

Various types of defects (defects) are often generated during semiconductor manufacturing, and removing defects will improve the yield of chips. In chip research and development and production, for part of defects, the layout can be reasonably modified through OPC (optical proximity correction), so that the layout is more friendly to subsequent processes, and the number of related defects is eliminated or reduced.

The premise that the OPC processes the related graph is to accurately obtain the characteristic parameters of the related defect graph. However, for wafer (wafer) testing, only the coordinate information of defect can be obtained. According to the traditional mode, OPC searches for relevant graphs one by one according to coordinates, carries out manual measurement, and obtains characteristic information of relevant defect graphs according to measurement results. However, this approach is inefficient; when the number of the defects is large, such as hundreds, the measurement cannot be taken for each defect, thereby limiting the comprehensiveness and accuracy of the parameters of the defect graph.

Disclosure of Invention

The technical problem to be solved by the invention is to provide an analysis method for the characteristic parameters of the defect graph, which can improve the extraction efficiency of the characteristic parameters of the defect graph and can realize the comprehensive and accurate analysis of the characteristic parameters of the defect graph.

In order to solve the technical problem, the method for analyzing the characteristic parameters of the defect graph provided by the invention comprises the following steps:

the method comprises the steps of firstly, carrying out defect testing on a wafer, and extracting a first coordinate of each defect when the defect is obtained through testing, wherein the first coordinate is a coordinate of the defect on the wafer.

And step two, converting each first coordinate into a corresponding second coordinate, wherein the second coordinate is a coordinate corresponding to the first coordinate on the layout.

And thirdly, adding a defect mark layer on the layout, wherein the defect mark layer forms a corresponding defect mark (error marker) pattern at each second coordinate.

And fourthly, the layout comprises a plurality of layers, the layer needing defect analysis is an analyzed layer, other layers except the analyzed layer are related layers, and the layout graph contacted by the analyzed layer and the defect marking graph in the layout is marked and used as the layout defect graph.

And fifthly, acquiring characteristic parameters of the layout defect graph.

In a further improvement, the testing machines for performing the defect testing in the step one include a K L a testing machine, a TEM machine, and a CDSEM machine.

The further improvement is that the third step comprises the following sub-steps:

and 31, calculating the vertex coordinates of the corresponding defect mark graph on the basis of the second coordinates.

And step 32, forming the defect mark graph corresponding to the defect mark layer on the layout according to the vertex coordinates of the defect mark graph.

In a further refinement, the defect mark pattern is formed using OPC software in step 32.

The further improvement is that OPC software is adopted to mark in the fourth step to form the layout defect graph.

And the further improvement is that OPC software is adopted to obtain the characteristic parameters of the layout defect graph in the fifth step.

In a further improvement, the second coordinate is a center of the defect mark pattern; or, the second coordinate is not the center of the defect mark pattern.

In a further improvement, the defect marking pattern is a regular pattern or an irregular pattern generated based on the vertex coordinates of the defect marking pattern.

In a further refinement, the regular pattern includes a polygon and a curved pattern.

In a further improvement, the dimension information of the defect marking pattern is determined according to an error range of the first coordinate measured by the testing machine for the defect test.

In a further improvement, the size information of the defect mark pattern includes the length of the corresponding line and the size of the enclosed area.

In a further improvement, in the fifth step, the characteristic parameters of the layout defect pattern include: the length, the width and the spacing of the layout defect graphs and the spacing and the surrounding value of the layout defect graphs and the layout graphs of the adjacent related layers.

In a further improvement, part of the defects are layout-related defects.

The further improvement is that the step five is followed by the step:

and carrying out statistical analysis on the characteristic parameters of the layout defect graph.

Determining two groups of specification parameters according to statistical analysis, wherein the first group of specification parameters are characteristic parameters of a layout graph to be modified and are used for capturing the layout defect graph corresponding to the layout related defects in the analyzed layer of the layout; and the second group of specification parameters are target values to be modified of the layout defect graphs corresponding to the layout related defects, and are used as modification targets of the captured layout defect graphs.

And finding the layout defect graphs corresponding to all the layout related defects according to the first group of specification parameters.

And performing OPC modification on the captured corresponding layout defect graph according to the second group of specification parameters to eliminate or reduce the layout related defects.

In the OPC modification, the characteristic parameters of the corresponding layout defect graph are modified to be within the range of the second group of specification parameters.

In a further improvement, the statistical analysis is based on the length, width or spacing of the layout defect pattern itself.

In a further refinement, the wafer comprises a monocrystalline silicon wafer.

The method can directly form the defect marking graph on the layout after converting the first coordinate of the defect obtained by testing into the corresponding second coordinate on the layout, and can automatically mark the defect graph of the publishing graph on the layout according to the defect marking graph so as to obtain the characteristic parameters of the defect graph of the layout.

The extraction efficiency of the defect graphic characteristic parameters is high, so that the defect graphic characteristic parameters can be extracted from all defects, and the defect graphic characteristic parameters can be comprehensively analyzed.

On the basis of comprehensive analysis, through statistical analysis, the method can obtain a first group of specification parameters and a second group of specification parameters related to the layout related defects through the analysis result of the feature parameters of the defect pattern, can capture the layout defect pattern corresponding to the layout related defects in the layout through the first group of specification parameters, and can carry out OPC modification on the captured layout defect pattern through the second group of specification parameters, so that the method can accurately obtain all the layout related defects in the defects, and can realize accurate analysis on the feature parameters of the defect pattern; on the basis of accurately analyzing the characteristic parameters of the defect graph and finding out all related defects of the layout, the defect quantity can be eliminated and reduced by carrying out OPC correction.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

FIG. 1 is a flow chart of a method for analyzing characteristic parameters of a defect pattern according to an embodiment of the present invention;

FIG. 2 is a layout after a defect marker pattern is generated in the method for analyzing feature parameters of a defect pattern according to an embodiment of the present invention;

FIG. 3A is an analysis diagram formed by statistical analysis based on the width of the layout defect pattern itself in the embodiment of the present invention;

fig. 3B is an analysis diagram formed by performing statistical analysis based on the length of the layout defect pattern itself in the embodiment of the present invention.

Detailed Description

FIG. 1 is a flow chart of a method for analyzing characteristic parameters of a defect pattern according to an embodiment of the present invention; as shown in fig. 2, the layout 1 after generating the defect mark pattern 4 in the method for analyzing the characteristic parameters of the defect pattern according to the embodiment of the present invention; the method for analyzing the characteristic parameters of the defect graph comprises the following steps:

the method comprises the steps of firstly, carrying out defect testing on a wafer, and extracting a first coordinate of each defect when the defect is obtained through testing, wherein the first coordinate is a coordinate of the defect on the wafer.

The wafer is typically a monocrystalline silicon wafer.

Preferably, the testing machines for performing the defect testing include a K L a testing machine, a TEM machine, and a CDSEM machine.

And step two, converting each first coordinate into a corresponding second coordinate, wherein the second coordinate is a coordinate corresponding to the first coordinate on the layout 1.

And thirdly, adding a defect marking layer on the layout 1, wherein the defect marking layer forms a corresponding defect marking graph 4 at each second coordinate, as shown by a hollow graph corresponding to the mark 4 in fig. 2.

In the embodiment of the invention, the third step comprises the following sub-steps:

and 31, calculating the vertex coordinates of the corresponding defect mark graph 4 on the basis of the second coordinates.

The second coordinate is the center of the defect mark pattern 4; alternatively, the second coordinate is not the center of the defect mark pattern 4, and the defect mark pattern 4 is disposed near the second coordinate.

And 32, forming the defect mark graph 4 corresponding to the defect mark layer on the layout 1 according to the vertex coordinates of the defect mark graph 4. The defect mark pattern 4 is formed in step 32 using OPC software.

The defect mark pattern 4 is a regular pattern or an irregular pattern generated based on the vertex coordinates of the defect mark pattern 4. The regular graph includes a polygon and a curve graph. The defect mark patterns 4 are shown as rectangular squares in fig. 2.

And determining the size information of the defect marking graph according to the error range of the first coordinate measured by the testing machine for the defect test. The size information of the defect mark pattern 4 includes the length of the corresponding line and the size of the enclosed area. The dimension, such as the side length, of the defect mark pattern 4 is given by considering the error of the first coordinate, which is a coordinate given by a testing device, i.e. a testing machine for the defect test, and the coordinate given by the testing device has a certain deviation relative to the real coordinate, so that the error marker needs to be enlarged to the approximate size of the error of the device, so that the position of the real layout defect pattern can be contacted.

And step four, the layout comprises a plurality of layers, the layer needing defect analysis is an analyzed layer 2, and other layers except the analyzed layer 2 are related layers 3, the analyzed layer 2 is shown as an oblique line graph corresponding to the mark 2 in fig. 2, and the related layers 3 are shown as a solid graph corresponding to the mark 3 in fig. 2. As can be seen in fig. 2, the defect marking pattern 4 is in contact with the pattern of the layer 2 to be analyzed in the vicinity. And marking the layout graph contacted by the analyzed layer and the defect marking graph in the layout as a layout defect graph.

Preferably, OPC software is adopted to mark the layout defect pattern.

And fifthly, acquiring characteristic parameters of the layout defect graph.

Preferably, in the fifth step, OPC software is adopted to obtain the characteristic parameters of the layout defect graph.

In the embodiment of the invention, in the fifth step, the characteristic parameters of the layout defect graph comprise: the length, the width and the spacing of the layout defect graphs and the spacing and the surrounding value of the layout defect graphs and the layout graphs of the adjacent related layers.

Generally, part of the defects are layout related defects, and the layout related defects comprise defects which can be eliminated through OPC modification of a layout; and when the layout has no space for further modification through OPC, the layout related defects cannot be eliminated through OPC modification, but the parameter analysis method of the defect graphic characteristic parameter analysis method provided by the embodiment of the invention is still meaningful. The layout-related defects can be eliminated by OPC modification of layout 1. In order to eliminate the layout related defects, the method further comprises the following step after the fifth step:

and carrying out statistical analysis on the characteristic parameters of the layout defect graph. The statistical analysis is based on the length, width or spacing of the layout defect pattern itself. As shown in fig. 3A, the analysis diagram is formed by performing statistical analysis based on the width of the layout defect pattern itself in the embodiment of the present invention, and it can be seen that the number of the layout defect patterns corresponding to different widths is different. As shown in fig. 3B, the analysis graph is formed by performing statistical analysis based on the length of the layout defect graph itself in the embodiment of the present invention, and it can be seen that the number of the layout defect graphs corresponding to different widths is different. More desirably, statistical analysis maps based on other dimensions can also be formed.

Determining two groups of specification parameters according to statistical analysis, wherein the first group of specification parameters are characteristic parameters of a layout graph to be modified and are used for capturing the layout defect graph corresponding to the layout related defects in the analyzed layer of the layout; and the second group of specification parameters are target values to be modified of the layout defect graphs corresponding to the layout related defects, and are used as modification targets of the captured layout defect graphs.

And finding the layout defect graphs corresponding to all the layout related defects according to the first group of specification parameters.

And performing OPC modification on the captured corresponding layout defect graph according to the second group of specification parameters to eliminate or reduce the layout related defects. And in OPC modification, modifying the characteristic parameters of the corresponding layout defect graph into the range of the second group of specification parameters.

Now, the following is explained with reference to fig. 3A: as shown in fig. 3A, the first condition of the first set of specification parameters that can be obtained is a graph width range corresponding to the mark 101, that is, during the process of capturing the corresponding layout defect graph, all the layout graphs within the graph width range corresponding to the mark 101 are captured as the layout defect graphs corresponding to the layout-related defects, for example, when the graph width range corresponding to the mark 101 is 100nm to 180nm, the first set of specification parameters may be defined as a graph width range of 100nm to 180nm, and all the layout graphs having a width of 100nm to 180nm are captured as the layout defect graphs; the captured layout defect graphs usually comprise layout graphs corresponding to the layout related defects detected in the first step; the method also comprises a layout pattern corresponding to the layout related defects which are not detected in the step one, and at this time, although the captured layout defect patterns do not form defects and are detected in the step one, the layout defect patterns are high-risk structures and may form defects at any time, so that the coverage range of the layout defect patterns captured by the method provided by the embodiment of the invention is wider and more comprehensive than that of the layout pattern corresponding to the defects detected in the step one.

Fig. 3B shows a length distribution diagram of the layout defect pattern, the second condition of the first set of specification parameters that can be obtained is the lower limit of the pattern length corresponding to the mark 102, and the layout defect pattern is obtained when the pattern length is greater than the lower limit of the pattern length of the mark 102.

In actual processing, two condition ranges corresponding to the mark 101 and the mark 102 are generally combined as the first set of specification parameters, and the OPC processing direction and thus the second set of specification parameters can be obtained by combining with the OPC experience, for example, the width of the layout pattern corresponding to each layout-related defect can be expanded to exceed the upper limit range of the mark 101. For example: if the width range of the layout defect graph is 100 nm-180 nm, the defects can be eliminated if the width of the layout defect graph is expanded to be more than 180nm, so that the second group of specification parameters can be defined as the graph width of more than 180 nm.

According to the embodiment of the invention, after the first coordinate of the defect obtained by testing is converted into the corresponding second coordinate on the layout 1, the defect marking graph 4 can be directly formed on the layout 1, and the layout defect graph can be automatically marked on the layout 1 according to the defect marking graph 4, so that the characteristic parameters of the layout defect graph can be obtained.

The defect pattern characteristic parameters are extracted from all defects, so that the defect pattern characteristic parameters can be comprehensively analyzed.

On the basis of comprehensive analysis, through statistical analysis, the embodiment of the invention can obtain a first group of specification parameters and a second group of specification parameters related to the layout related defects through the analysis result of the feature parameters of the defect pattern, can capture the layout defect pattern corresponding to the layout related defects in the layout through the first group of specification parameters, and can carry out OPC modification on the captured layout defect pattern through the second group of specification parameters, so that the invention can accurately obtain all the layout related defects in the defects, and can realize accurate analysis on the feature parameters of the defect pattern; on the basis of accurately analyzing the characteristic parameters of the defect graph and finding out all related defects of the layout, the defect quantity can be eliminated and reduced by carrying out OPC correction.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.